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From: Sergey Fedorov <serge.fdrv@gmail.com>
To: Pranith Kumar <bobby.prani@gmail.com>,
	Richard Henderson <rth@twiddle.net>,
	"open list:All patches CC here" <qemu-devel@nongnu.org>
Cc: serge.fdrv@linaro.org, alex.bennee@linaro.org
Subject: Re: [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier
Date: Thu, 2 Jun 2016 19:30:18 +0300	[thread overview]
Message-ID: <57505F1A.3020808@gmail.com> (raw)
In-Reply-To: <20160531183928.29406-2-bobby.prani@gmail.com>

On 31/05/16 21:39, Pranith Kumar wrote:
> diff --git a/tcg/README b/tcg/README
> index f4a8ac1..cfe79d7 100644
> --- a/tcg/README
> +++ b/tcg/README
> @@ -402,6 +402,23 @@ double-word product T0.  The later is returned in two single-word outputs.
>  
>  Similar to mulu2, except the two inputs T1 and T2 are signed.
>  
> +********* Memory Barrier support
> +
> +* mb <$arg>
> +
> +Generate a target memory barrier instruction to ensure memory ordering as being
> +enforced by a corresponding guest memory barrier instruction. The ordering
> +enforced by the backend may be stricter than the ordering required by the guest.
> +It cannot be weaker. This opcode takes an optional constant argument if required
> +to generate the appropriate barrier instruction. The backend should take care to
> +emit the target barrier instruction only when necessary i.e., for SMP guests and
> +when MTTCG is enabled.
> +
> +The guest translators should generate this opcode for all guest instructions
> +which have ordering side effects.

I think we need to extend TCG load/store instruction attributes to
provide information about guest ordering requirements and leave this TCG
operation only for explicit barrier instruction translation.

> +
> +Please see docs/atomics.txt for more information on memory barriers.
> +
>  ********* 64-bit guest on 32-bit host support
>  
>  The following opcodes are internal to TCG.  Thus they are to be implemented by
> diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c
> index f554b86..a6f01a7 100644
> --- a/tcg/tcg-op.c
> +++ b/tcg/tcg-op.c
> @@ -143,6 +143,12 @@ void tcg_gen_op6(TCGContext *ctx, TCGOpcode opc, TCGArg a1, TCGArg a2,
>      tcg_emit_op(ctx, opc, pi);
>  }
>  
> +void tcg_gen_mb(TCGArg a)
> +{
> +    /* ??? Enable only when MTTCG is enabled.  */
> +    tcg_gen_op1(&tcg_ctx, INDEX_op_mb, 0);

Yes, this could be a right place to check for MTTCG enabled and number
of CPUs emulated. If we do it here, then we should adjust the
documentation stating that the backend should take care of it.

Kind regards,
Sergey

  parent reply	other threads:[~2016-06-02 16:30 UTC|newest]

Thread overview: 61+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2016-05-31 18:39 [Qemu-devel] [RFC v2 PATCH 00/13] tcg: Add fence gen support Pranith Kumar
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 01/13] Introduce TCGOpcode for memory barrier Pranith Kumar
2016-05-31 20:24   ` Richard Henderson
2016-06-01 18:43     ` Pranith Kumar
2016-06-01 21:35       ` Richard Henderson
2016-06-02 16:18         ` Sergey Fedorov
2016-06-02 16:30   ` Sergey Fedorov [this message]
2016-06-02 18:42     ` Pranith Kumar
2016-06-02 20:36       ` Richard Henderson
2016-06-02 20:36     ` Richard Henderson
2016-06-02 20:38       ` Sergey Fedorov
2016-06-02 21:18         ` Richard Henderson
2016-06-02 21:37           ` Sergey Fedorov
2016-06-03  1:08             ` Richard Henderson
2016-06-03 15:16               ` Sergey Fedorov
2016-06-03 15:45                 ` Richard Henderson
2016-06-03 16:06                   ` Sergey Fedorov
2016-06-03 18:30               ` Pranith Kumar
2016-06-03 19:49                 ` Sergey Fedorov
2016-06-03 20:43                   ` Peter Maydell
2016-06-03 21:33                     ` Sergey Fedorov
2016-06-06 16:19                   ` Alex Bennée
2016-06-03 18:27           ` Pranith Kumar
2016-06-03 19:52             ` Sergey Fedorov
2016-06-06 15:44             ` Sergey Fedorov
2016-06-06 15:47               ` Pranith Kumar
2016-06-06 15:49                 ` Sergey Fedorov
2016-06-06 15:58                   ` Pranith Kumar
2016-06-06 16:14                     ` Sergey Fedorov
2016-06-06 17:11                       ` Pranith Kumar
2016-06-06 19:23                         ` Richard Henderson
2016-06-06 19:28                           ` Pranith Kumar
2016-06-06 20:30                             ` Sergey Fedorov
2016-06-06 21:00                               ` Peter Maydell
2016-06-06 21:49                                 ` Sergey Fedorov
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 02/13] tcg/i386: Add support for fence Pranith Kumar
2016-05-31 20:27   ` Richard Henderson
2016-06-01 18:49     ` Pranith Kumar
2016-06-01 21:17       ` Richard Henderson
2016-06-01 21:44         ` Pranith Kumar
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 03/13] tcg/aarch64: " Pranith Kumar
2016-05-31 18:59   ` Claudio Fontana
2016-05-31 20:34   ` Richard Henderson
2016-06-16 22:03     ` Pranith Kumar
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 04/13] tcg/arm: " Pranith Kumar
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 05/13] tcg/ia64: " Pranith Kumar
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 06/13] tcg/mips: " Pranith Kumar
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 07/13] tcg/ppc: " Pranith Kumar
2016-05-31 20:41   ` Richard Henderson
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 08/13] tcg/s390: " Pranith Kumar
2016-06-02 19:31   ` Sergey Fedorov
2016-06-02 20:38     ` Richard Henderson
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 09/13] tcg/sparc: " Pranith Kumar
2016-05-31 20:45   ` Richard Henderson
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 10/13] tcg/tci: " Pranith Kumar
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 11/13] target-arm: Generate fences in ARMv7 frontend Pranith Kumar
2016-06-02 19:37   ` Sergey Fedorov
2016-06-04 14:50     ` Pranith Kumar
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 12/13] target-alpha: Generate fence op Pranith Kumar
2016-05-31 18:39 ` [Qemu-devel] [RFC v2 PATCH 13/13] tcg: Generate fences only for SMP MTTCG guests Pranith Kumar
2016-05-31 18:46 ` [Qemu-devel] [RFC v2 PATCH 00/13] tcg: Add fence gen support Pranith Kumar

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