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From: "Kulkarni, Vandita" <vandita.kulkarni@intel.com>
To: "Shankar, Uma" <uma.shankar@intel.com>,
	"intel-gfx@lists.freedesktop.org"
	<intel-gfx@lists.freedesktop.org>
Cc: "Nikula, Jani" <jani.nikula@intel.com>
Subject: Re: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
Date: Thu, 21 Mar 2019 13:53:15 +0000	[thread overview]
Message-ID: <57510F3E2013164E925CD03ED7512A3B7FEAF969@BGSMSX110.gar.corp.intel.com> (raw)
In-Reply-To: <E7C9878FBA1C6D42A1CA3F62AEB6945F81F8A5F7@BGSMSX104.gar.corp.intel.com>


> -----Original Message-----
> From: Shankar, Uma
> Sent: Wednesday, March 20, 2019 5:19 PM
> To: Kulkarni, Vandita <vandita.kulkarni@intel.com>; intel-
> gfx@lists.freedesktop.org
> Cc: Nikula, Jani <jani.nikula@intel.com>; Chauhan, Madhav
> <madhav.chauhan@intel.com>
> Subject: RE: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
> 
> 
> 
> >-----Original Message-----
> >From: Kulkarni, Vandita
> >Sent: Wednesday, March 20, 2019 3:39 PM
> >To: intel-gfx@lists.freedesktop.org
> >Cc: Nikula, Jani <jani.nikula@intel.com>; Shankar, Uma
> ><uma.shankar@intel.com>; Chauhan, Madhav <madhav.chauhan@intel.com>;
> >Kulkarni, Vandita <vandita.kulkarni@intel.com>
> >Subject: [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated
> 
> You can drop dsi from commit header. Just drm/i915/icl/ should be good.
> Also update header as Ungate ddi clocks if gated
Okay.
> 
> >
> >IO enable sequencing needs ddi clocks enabled.
> >These clocks will be gated at the later point in the enable sequence.
> >
> >Signed-off-by: Vandita Kulkarni <vandita.kulkarni@intel.com>
> >---
> > drivers/gpu/drm/i915/icl_dsi.c | 8 ++++++++
> > 1 file changed, 8 insertions(+)
> >
> >diff --git a/drivers/gpu/drm/i915/icl_dsi.c
> >b/drivers/gpu/drm/i915/icl_dsi.c index beb30d9..f02504d 100644
> >--- a/drivers/gpu/drm/i915/icl_dsi.c
> >+++ b/drivers/gpu/drm/i915/icl_dsi.c
> >@@ -589,6 +589,14 @@ static void gen11_dsi_map_pll(struct intel_encoder
> >*encoder,
> > 		val |= DPCLKA_CFGCR0_DDI_CLK_SEL(pll->info->id, port);
> > 	}
> > 	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> >+
> >+	/* make sure that the ddi clocks are not gated */
> >+	val = I915_READ(DPCLKA_CFGCR0_ICL);
> >+	for_each_dsi_port(port, intel_dsi->ports) {
> >+		val &= ~DPCLKA_CFGCR0_DDI_CLK_OFF(port);
> >+	}
> >+	I915_WRITE(DPCLKA_CFGCR0_ICL, val);
> >+
> > 	POSTING_READ(DPCLKA_CFGCR0_ICL);
> 
> I think you can reuse the val from top and avoid an extra write to the same
> register.
At this point we ideally have the clocks gated and we need to ungate it. We must write to this register.
Accordingly, will fix the commit header too.

Thanks.
Vandita
> 
> Otherwise change looks ok to me. With above comments fixed,
> Reviewed-by: Uma Shankar <uma.shankar@intel.com>
> 
> >
> > 	mutex_unlock(&dev_priv->dpll_lock);
> >--
> >1.9.1

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  reply	other threads:[~2019-03-21 13:53 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2019-03-20 10:08 [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Vandita Kulkarni
2019-03-20 10:08 ` [PATCH 2/2] drm/i915/icl/dsi: Fix port disable sequence Vandita Kulkarni
2019-03-20 11:07   ` Imre Deak
2019-03-20 12:02     ` Shankar, Uma
2019-03-21 13:57       ` Kulkarni, Vandita
2019-03-21 13:56     ` Kulkarni, Vandita
2019-03-20 11:49 ` [PATCH 1/2] drm/i915/icl/dsi: Ungate clocks if gated Shankar, Uma
2019-03-21 13:53   ` Kulkarni, Vandita [this message]
2019-03-22  7:48     ` Kulkarni, Vandita
2019-03-22  8:18       ` Shankar, Uma
2019-03-20 14:28 ` ✓ Fi.CI.BAT: success for series starting with [1/2] " Patchwork
2019-03-20 19:01 ` ✓ Fi.CI.IGT: " Patchwork

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