From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933438AbcFJQuR (ORCPT ); Fri, 10 Jun 2016 12:50:17 -0400 Received: from mail-pa0-f66.google.com ([209.85.220.66]:33061 "EHLO mail-pa0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751951AbcFJQuN (ORCPT ); Fri, 10 Jun 2016 12:50:13 -0400 Message-ID: <575AEFC0.1070304@gmail.com> Date: Fri, 10 Jun 2016 09:50:08 -0700 From: David Daney User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:17.0) Gecko/20130625 Thunderbird/17.0.7 MIME-Version: 1.0 To: Marc Zyngier CC: David Daney , Mark Rutland , Andrew Lunn , Krzysztof Kozlowski , Hou Zhiqiang , Liu Gang , Masahiro Yamada , Mingkai Hu , Florian Fainelli , Kevin Hilman , Daniel Lezcano , Michal Simek , linux-samsung-soc@vger.kernel.org, Kukjin Kim , bcm-kernel-feedback-list@broadcom.com, =?ISO-8859-1?Q?S=F6ren_Brinkman?= =?ISO-8859-1?Q?n?= , Sebastian Hesselbarth , Jason Cooper , Ray Jui , Tirumalesh Chalamarla , Rob Herring , Yuan Yao , Wenbin Song , Jan Glauber , Gregory Clement , linux-amlogic@lists.infradead.org, Thomas Gleixner , linux-arm-kernel@lists.infradead.org, Rajesh Bhagat , Scott Branden , Duc Dang , linux-kernel@vger.kernel.org, Carlo Caione , Dinh Nguyen Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger References: <1465235791-7064-1-git-send-email-marc.zyngier@arm.com> <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> <5759B143.9070503@caviumnetworks.com> <5759DA3A.4070905@gmail.com> <20160610082324.2a0967b0@arm.com> In-Reply-To: <20160610082324.2a0967b0@arm.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 06/10/2016 12:23 AM, Marc Zyngier wrote: > On Thu, 09 Jun 2016 14:06:02 -0700 > David Daney wrote: > >> I spoke too soon... >> >> On 06/09/2016 11:11 AM, David Daney wrote: >>> On 06/06/2016 10:56 AM, Marc Zyngier wrote: >>>> The ARM architected timer specification mandates that the interrupt >>>> associated with each timer is level triggered (which corresponds to >>>> the "counter >= comparator" condition). >>>> >>>> A number of DTs are being remarkably creative, declaring the interrupt >>>> to be edge triggered. A quick look at the TRM for the corresponding ARM >>>> CPUs clearly shows that this is wrong, and I've corrected those. >>>> For non-ARM designs (and in the absence of a publicly available TRM), >>>> I've made them active low as well, which can't be completely wrong >>>> as the GIC cannot disinguish between level low and level high. >>>> >>>> The respective maintainers are of course welcome to prove me wrong. >>>> >>>> While I was at it, I took the liberty to fix a couple of related issue, >>>> such as some spurious affinity bits on ThunderX, and their complete >>>> absence on ls1043a (both of which seem to be related to copy-pasting >>>> from other DTs). >>>> >>>> Signed-off-by: Marc Zyngier >>>> --- >>>> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- >>>> 10 files changed, 40 insertions(+), 40 deletions(-) >>>> >>> [...] >>>> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> index 2eb9b22..382d86f 100644 >>>> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> @@ -354,10 +354,10 @@ >>>> >>>> timer { >>>> compatible = "arm,armv8-timer"; >>>> - interrupts = <1 13 0xff01>, >>>> - <1 14 0xff01>, >>>> - <1 11 0xff01>, >>>> - <1 10 0xff01>; >>>> + interrupts = <1 13 8>, >>>> + <1 14 8>, >>>> + <1 11 8>, >>>> + <1 10 8>; >> >> >> NAK! >> >> According to arm,gic-v3.txt the trigger value must be either 1 or 4: >> >> The 3rd cell is the flags, encoded as follows: >> bits[3:0] trigger type and level flags. >> 1 = edge triggered >> 4 = level triggered > > Which is a bug in the binding description. PPIs can be any trigger > (just look at the TRM for CPUs that have devices connected to a PPI to > be convinced - most of them are level low). > > This doesn't mean that you can distinguish level-high from level-low > in a programmatic way. But the HW definitely can handle it. > > I'll update the GICv3 binding to reflect this. > > Now, coming back to your NAK: is level-low the right or wrong trigger > for your implementation of the architected timers? > For the Cavium Thunder implementation of GIC-v3, there is no concept of high and low. All we have is asserted and not-asserted, we have chosen to map the concept of an asserted level-triggered source to IRQ_TYPE_LEVEL_HIGH, and the transition from not-asserted to asserted on an edge triggered source to IRQ_TYPE_EDGE_RISING. Looking and the code and specifications, I don't see in irq-gic-v3.c or PRD03-GENC-010745-35 any indication that the concepts of "high" and "low" exist either, although I certainly could have missed something. David Daney From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Daney Subject: Re: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger Date: Fri, 10 Jun 2016 09:50:08 -0700 Message-ID: <575AEFC0.1070304@gmail.com> References: <1465235791-7064-1-git-send-email-marc.zyngier@arm.com> <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> <5759B143.9070503@caviumnetworks.com> <5759DA3A.4070905@gmail.com> <20160610082324.2a0967b0@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from mail-pa0-f66.google.com ([209.85.220.66]:33061 "EHLO mail-pa0-f66.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751951AbcFJQuN (ORCPT ); Fri, 10 Jun 2016 12:50:13 -0400 In-Reply-To: <20160610082324.2a0967b0@arm.com> Sender: linux-samsung-soc-owner@vger.kernel.org List-Id: linux-samsung-soc@vger.kernel.org To: Marc Zyngier Cc: David Daney , Mark Rutland , Andrew Lunn , Krzysztof Kozlowski , Hou Zhiqiang , Liu Gang , Masahiro Yamada , Mingkai Hu , Florian Fainelli , Kevin Hilman , Daniel Lezcano , Michal Simek , linux-samsung-soc@vger.kernel.org, Kukjin Kim , bcm-kernel-feedback-list@broadcom.com, =?ISO-8859-1?Q?S=F6ren_Brinkman?= =?ISO-8859-1?Q?n?= , Sebastian Hesselbarth , Jason Cooper , Ray Jui , Tirumalesh Chalamarla , Rob Herring Yuan Yao On 06/10/2016 12:23 AM, Marc Zyngier wrote: > On Thu, 09 Jun 2016 14:06:02 -0700 > David Daney wrote: > >> I spoke too soon... >> >> On 06/09/2016 11:11 AM, David Daney wrote: >>> On 06/06/2016 10:56 AM, Marc Zyngier wrote: >>>> The ARM architected timer specification mandates that the interrupt >>>> associated with each timer is level triggered (which corresponds to >>>> the "counter >= comparator" condition). >>>> >>>> A number of DTs are being remarkably creative, declaring the interrupt >>>> to be edge triggered. A quick look at the TRM for the corresponding ARM >>>> CPUs clearly shows that this is wrong, and I've corrected those. >>>> For non-ARM designs (and in the absence of a publicly available TRM), >>>> I've made them active low as well, which can't be completely wrong >>>> as the GIC cannot disinguish between level low and level high. >>>> >>>> The respective maintainers are of course welcome to prove me wrong. >>>> >>>> While I was at it, I took the liberty to fix a couple of related issue, >>>> such as some spurious affinity bits on ThunderX, and their complete >>>> absence on ls1043a (both of which seem to be related to copy-pasting >>>> from other DTs). >>>> >>>> Signed-off-by: Marc Zyngier >>>> --- >>>> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- >>>> 10 files changed, 40 insertions(+), 40 deletions(-) >>>> >>> [...] >>>> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> index 2eb9b22..382d86f 100644 >>>> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> @@ -354,10 +354,10 @@ >>>> >>>> timer { >>>> compatible = "arm,armv8-timer"; >>>> - interrupts = <1 13 0xff01>, >>>> - <1 14 0xff01>, >>>> - <1 11 0xff01>, >>>> - <1 10 0xff01>; >>>> + interrupts = <1 13 8>, >>>> + <1 14 8>, >>>> + <1 11 8>, >>>> + <1 10 8>; >> >> >> NAK! >> >> According to arm,gic-v3.txt the trigger value must be either 1 or 4: >> >> The 3rd cell is the flags, encoded as follows: >> bits[3:0] trigger type and level flags. >> 1 = edge triggered >> 4 = level triggered > > Which is a bug in the binding description. PPIs can be any trigger > (just look at the TRM for CPUs that have devices connected to a PPI to > be convinced - most of them are level low). > > This doesn't mean that you can distinguish level-high from level-low > in a programmatic way. But the HW definitely can handle it. > > I'll update the GICv3 binding to reflect this. > > Now, coming back to your NAK: is level-low the right or wrong trigger > for your implementation of the architected timers? > For the Cavium Thunder implementation of GIC-v3, there is no concept of high and low. All we have is asserted and not-asserted, we have chosen to map the concept of an asserted level-triggered source to IRQ_TYPE_LEVEL_HIGH, and the transition from not-asserted to asserted on an edge triggered source to IRQ_TYPE_EDGE_RISING. Looking and the code and specifications, I don't see in irq-gic-v3.c or PRD03-GENC-010745-35 any indication that the concepts of "high" and "low" exist either, although I certainly could have missed something. David Daney From mboxrd@z Thu Jan 1 00:00:00 1970 From: ddaney.cavm@gmail.com (David Daney) Date: Fri, 10 Jun 2016 09:50:08 -0700 Subject: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger In-Reply-To: <20160610082324.2a0967b0@arm.com> References: <1465235791-7064-1-git-send-email-marc.zyngier@arm.com> <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> <5759B143.9070503@caviumnetworks.com> <5759DA3A.4070905@gmail.com> <20160610082324.2a0967b0@arm.com> Message-ID: <575AEFC0.1070304@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 06/10/2016 12:23 AM, Marc Zyngier wrote: > On Thu, 09 Jun 2016 14:06:02 -0700 > David Daney wrote: > >> I spoke too soon... >> >> On 06/09/2016 11:11 AM, David Daney wrote: >>> On 06/06/2016 10:56 AM, Marc Zyngier wrote: >>>> The ARM architected timer specification mandates that the interrupt >>>> associated with each timer is level triggered (which corresponds to >>>> the "counter >= comparator" condition). >>>> >>>> A number of DTs are being remarkably creative, declaring the interrupt >>>> to be edge triggered. A quick look at the TRM for the corresponding ARM >>>> CPUs clearly shows that this is wrong, and I've corrected those. >>>> For non-ARM designs (and in the absence of a publicly available TRM), >>>> I've made them active low as well, which can't be completely wrong >>>> as the GIC cannot disinguish between level low and level high. >>>> >>>> The respective maintainers are of course welcome to prove me wrong. >>>> >>>> While I was at it, I took the liberty to fix a couple of related issue, >>>> such as some spurious affinity bits on ThunderX, and their complete >>>> absence on ls1043a (both of which seem to be related to copy-pasting >>>> from other DTs). >>>> >>>> Signed-off-by: Marc Zyngier >>>> --- >>>> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- >>>> 10 files changed, 40 insertions(+), 40 deletions(-) >>>> >>> [...] >>>> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> index 2eb9b22..382d86f 100644 >>>> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> @@ -354,10 +354,10 @@ >>>> >>>> timer { >>>> compatible = "arm,armv8-timer"; >>>> - interrupts = <1 13 0xff01>, >>>> - <1 14 0xff01>, >>>> - <1 11 0xff01>, >>>> - <1 10 0xff01>; >>>> + interrupts = <1 13 8>, >>>> + <1 14 8>, >>>> + <1 11 8>, >>>> + <1 10 8>; >> >> >> NAK! >> >> According to arm,gic-v3.txt the trigger value must be either 1 or 4: >> >> The 3rd cell is the flags, encoded as follows: >> bits[3:0] trigger type and level flags. >> 1 = edge triggered >> 4 = level triggered > > Which is a bug in the binding description. PPIs can be any trigger > (just look at the TRM for CPUs that have devices connected to a PPI to > be convinced - most of them are level low). > > This doesn't mean that you can distinguish level-high from level-low > in a programmatic way. But the HW definitely can handle it. > > I'll update the GICv3 binding to reflect this. > > Now, coming back to your NAK: is level-low the right or wrong trigger > for your implementation of the architected timers? > For the Cavium Thunder implementation of GIC-v3, there is no concept of high and low. All we have is asserted and not-asserted, we have chosen to map the concept of an asserted level-triggered source to IRQ_TYPE_LEVEL_HIGH, and the transition from not-asserted to asserted on an edge triggered source to IRQ_TYPE_EDGE_RISING. Looking and the code and specifications, I don't see in irq-gic-v3.c or PRD03-GENC-010745-35 any indication that the concepts of "high" and "low" exist either, although I certainly could have missed something. David Daney From mboxrd@z Thu Jan 1 00:00:00 1970 From: ddaney.cavm@gmail.com (David Daney) Date: Fri, 10 Jun 2016 09:50:08 -0700 Subject: [PATCH v3 2/2] arm64: dts: Fix broken architected timer interrupt trigger In-Reply-To: <20160610082324.2a0967b0@arm.com> References: <1465235791-7064-1-git-send-email-marc.zyngier@arm.com> <1465235791-7064-3-git-send-email-marc.zyngier@arm.com> <5759B143.9070503@caviumnetworks.com> <5759DA3A.4070905@gmail.com> <20160610082324.2a0967b0@arm.com> Message-ID: <575AEFC0.1070304@gmail.com> To: linus-amlogic@lists.infradead.org List-Id: linus-amlogic.lists.infradead.org On 06/10/2016 12:23 AM, Marc Zyngier wrote: > On Thu, 09 Jun 2016 14:06:02 -0700 > David Daney wrote: > >> I spoke too soon... >> >> On 06/09/2016 11:11 AM, David Daney wrote: >>> On 06/06/2016 10:56 AM, Marc Zyngier wrote: >>>> The ARM architected timer specification mandates that the interrupt >>>> associated with each timer is level triggered (which corresponds to >>>> the "counter >= comparator" condition). >>>> >>>> A number of DTs are being remarkably creative, declaring the interrupt >>>> to be edge triggered. A quick look at the TRM for the corresponding ARM >>>> CPUs clearly shows that this is wrong, and I've corrected those. >>>> For non-ARM designs (and in the absence of a publicly available TRM), >>>> I've made them active low as well, which can't be completely wrong >>>> as the GIC cannot disinguish between level low and level high. >>>> >>>> The respective maintainers are of course welcome to prove me wrong. >>>> >>>> While I was at it, I took the liberty to fix a couple of related issue, >>>> such as some spurious affinity bits on ThunderX, and their complete >>>> absence on ls1043a (both of which seem to be related to copy-pasting >>>> from other DTs). >>>> >>>> Signed-off-by: Marc Zyngier >>>> --- >>>> arch/arm64/boot/dts/altera/socfpga_stratix10.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/amlogic/meson-gxbb.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/apm/apm-storm.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/broadcom/ns2.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/cavium/thunder-88xx.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/exynos/exynos7.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/marvell/armada-ap806.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/socionext/uniphier-ph1-ld20.dtsi | 8 ++++---- >>>> arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 8 ++++---- >>>> 10 files changed, 40 insertions(+), 40 deletions(-) >>>> >>> [...] >>>> diff --git a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> index 2eb9b22..382d86f 100644 >>>> --- a/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> +++ b/arch/arm64/boot/dts/cavium/thunder-88xx.dtsi >>>> @@ -354,10 +354,10 @@ >>>> >>>> timer { >>>> compatible = "arm,armv8-timer"; >>>> - interrupts = <1 13 0xff01>, >>>> - <1 14 0xff01>, >>>> - <1 11 0xff01>, >>>> - <1 10 0xff01>; >>>> + interrupts = <1 13 8>, >>>> + <1 14 8>, >>>> + <1 11 8>, >>>> + <1 10 8>; >> >> >> NAK! >> >> According to arm,gic-v3.txt the trigger value must be either 1 or 4: >> >> The 3rd cell is the flags, encoded as follows: >> bits[3:0] trigger type and level flags. >> 1 = edge triggered >> 4 = level triggered > > Which is a bug in the binding description. PPIs can be any trigger > (just look at the TRM for CPUs that have devices connected to a PPI to > be convinced - most of them are level low). > > This doesn't mean that you can distinguish level-high from level-low > in a programmatic way. But the HW definitely can handle it. > > I'll update the GICv3 binding to reflect this. > > Now, coming back to your NAK: is level-low the right or wrong trigger > for your implementation of the architected timers? > For the Cavium Thunder implementation of GIC-v3, there is no concept of high and low. All we have is asserted and not-asserted, we have chosen to map the concept of an asserted level-triggered source to IRQ_TYPE_LEVEL_HIGH, and the transition from not-asserted to asserted on an edge triggered source to IRQ_TYPE_EDGE_RISING. Looking and the code and specifications, I don't see in irq-gic-v3.c or PRD03-GENC-010745-35 any indication that the concepts of "high" and "low" exist either, although I certainly could have missed something. David Daney