From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S932864AbcGEHam (ORCPT ); Tue, 5 Jul 2016 03:30:42 -0400 Received: from mx08-00178001.pphosted.com ([91.207.212.93]:47929 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751354AbcGEHai (ORCPT ); Tue, 5 Jul 2016 03:30:38 -0400 Subject: Re: [PATCH 2/4] dt-bindings: Document the STM32 reset bindings To: Philipp Zabel References: <1467640052-6770-1-git-send-email-gabriel.fernandez@st.com> <1467640052-6770-2-git-send-email-gabriel.fernandez@st.com> <1467653766.2224.76.camel@pengutronix.de> CC: Rob Herring , Mark Rutland , Maxime Coquelin , Russell King , , , , , From: Gabriel Fernandez Message-ID: <577B6200.3070406@st.com> Date: Tue, 5 Jul 2016 09:30:08 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <1467653766.2224.76.camel@pengutronix.de> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.48.0.158] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-07-05_03:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Philipp, On 07/04/2016 07:36 PM, Philipp Zabel wrote: > Am Montag, den 04.07.2016, 15:47 +0200 schrieb gabriel.fernandez@st.com: >> From: Maxime Coquelin >> >> This adds documentation of device tree bindings for the >> STM32 reset controller. >> >> Signed-off-by: Maxime Coquelin > The way I understand Documentation/SubmittingPatches, this should also > have your Signed-off-by. ok >> --- >> .../devicetree/bindings/reset/st,stm32-rcc.txt | 50 ++++++++++++++++++++++ >> 1 file changed, 50 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-rcc.txt >> >> diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt >> new file mode 100644 >> index 0000000..333080c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt >> @@ -0,0 +1,50 @@ >> +STMicroelectronics STM32 Peripheral Reset Controller >> +==================================================== >> + >> +The RCC IP is both a reset and a clock controller. This documentation only >> +documents the reset part. >> + >> +Please also refer to reset.txt in this directory for common reset >> +controller binding usage. >> + >> +Required properties: >> +- compatible: Should be "st,stm32-rcc" >> +- reg: should be register base and length as documented in the >> + datasheet >> +- #reset-cells: 1, see below >> + >> +example: >> + >> +rcc: reset@40023800 { >> + #reset-cells = <1>; >> + compatible = "st,stm32-rcc"; >> + reg = <0x40023800 0x400>; >> +}; >> + >> +Specifying softreset control of devices >> +======================================= >> + >> +Device nodes should specify the reset channel required in their "resets" >> +property, containing a phandle to the reset device node and an index specifying >> +which channel to use. >> +The index is the bit number within the RCC registers bank, starting from RCC >> +base address. >> +It is calculated as: index = register_offset / 4 * 32 + bit_offset. >> +Where bit_offset is the bit offset within the register. >> +For example, for CRC reset: >> + crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 > I see you decided to keep the register offset encoded in the reset > index. > >> + >> +To simplify the usagen and to share bit definition with the clock driver of > s/usagen/usage/ ok >> +the RCC IP, macros are available to generate the index in human-readble >> +format. >> + >> +For STM32F4 series, the macro are available here: >> + - include/dt-bindings/mfd/stm32f4-rcc.h > If DT and ARM/STI and maintainers agree with the binding and header > macros, I'm inclined to take patches 1-3. > > regards > Philipp > Thanks! Best Regards Gabriel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gabriel Fernandez Subject: Re: [PATCH 2/4] dt-bindings: Document the STM32 reset bindings Date: Tue, 5 Jul 2016 09:30:08 +0200 Message-ID: <577B6200.3070406@st.com> References: <1467640052-6770-1-git-send-email-gabriel.fernandez@st.com> <1467640052-6770-2-git-send-email-gabriel.fernandez@st.com> <1467653766.2224.76.camel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1467653766.2224.76.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Philipp Zabel Cc: Rob Herring , Mark Rutland , Maxime Coquelin , Russell King , patrice.chotard-qxv4g6HH51o@public.gmane.org, alexandre.torgue-qxv4g6HH51o@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org Hi Philipp, On 07/04/2016 07:36 PM, Philipp Zabel wrote: > Am Montag, den 04.07.2016, 15:47 +0200 schrieb gabriel.fernandez-qxv4g6HH51o@public.gmane.org: >> From: Maxime Coquelin >> >> This adds documentation of device tree bindings for the >> STM32 reset controller. >> >> Signed-off-by: Maxime Coquelin > The way I understand Documentation/SubmittingPatches, this should also > have your Signed-off-by. ok >> --- >> .../devicetree/bindings/reset/st,stm32-rcc.txt | 50 ++++++++++++++++++++++ >> 1 file changed, 50 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-rcc.txt >> >> diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt >> new file mode 100644 >> index 0000000..333080c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt >> @@ -0,0 +1,50 @@ >> +STMicroelectronics STM32 Peripheral Reset Controller >> +==================================================== >> + >> +The RCC IP is both a reset and a clock controller. This documentation only >> +documents the reset part. >> + >> +Please also refer to reset.txt in this directory for common reset >> +controller binding usage. >> + >> +Required properties: >> +- compatible: Should be "st,stm32-rcc" >> +- reg: should be register base and length as documented in the >> + datasheet >> +- #reset-cells: 1, see below >> + >> +example: >> + >> +rcc: reset@40023800 { >> + #reset-cells = <1>; >> + compatible = "st,stm32-rcc"; >> + reg = <0x40023800 0x400>; >> +}; >> + >> +Specifying softreset control of devices >> +======================================= >> + >> +Device nodes should specify the reset channel required in their "resets" >> +property, containing a phandle to the reset device node and an index specifying >> +which channel to use. >> +The index is the bit number within the RCC registers bank, starting from RCC >> +base address. >> +It is calculated as: index = register_offset / 4 * 32 + bit_offset. >> +Where bit_offset is the bit offset within the register. >> +For example, for CRC reset: >> + crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 > I see you decided to keep the register offset encoded in the reset > index. > >> + >> +To simplify the usagen and to share bit definition with the clock driver of > s/usagen/usage/ ok >> +the RCC IP, macros are available to generate the index in human-readble >> +format. >> + >> +For STM32F4 series, the macro are available here: >> + - include/dt-bindings/mfd/stm32f4-rcc.h > If DT and ARM/STI and maintainers agree with the binding and header > macros, I'm inclined to take patches 1-3. > > regards > Philipp > Thanks! Best Regards Gabriel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: gabriel.fernandez@st.com (Gabriel Fernandez) Date: Tue, 5 Jul 2016 09:30:08 +0200 Subject: [PATCH 2/4] dt-bindings: Document the STM32 reset bindings In-Reply-To: <1467653766.2224.76.camel@pengutronix.de> References: <1467640052-6770-1-git-send-email-gabriel.fernandez@st.com> <1467640052-6770-2-git-send-email-gabriel.fernandez@st.com> <1467653766.2224.76.camel@pengutronix.de> Message-ID: <577B6200.3070406@st.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Philipp, On 07/04/2016 07:36 PM, Philipp Zabel wrote: > Am Montag, den 04.07.2016, 15:47 +0200 schrieb gabriel.fernandez at st.com: >> From: Maxime Coquelin >> >> This adds documentation of device tree bindings for the >> STM32 reset controller. >> >> Signed-off-by: Maxime Coquelin > The way I understand Documentation/SubmittingPatches, this should also > have your Signed-off-by. ok >> --- >> .../devicetree/bindings/reset/st,stm32-rcc.txt | 50 ++++++++++++++++++++++ >> 1 file changed, 50 insertions(+) >> create mode 100644 Documentation/devicetree/bindings/reset/st,stm32-rcc.txt >> >> diff --git a/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt >> new file mode 100644 >> index 0000000..333080c >> --- /dev/null >> +++ b/Documentation/devicetree/bindings/reset/st,stm32-rcc.txt >> @@ -0,0 +1,50 @@ >> +STMicroelectronics STM32 Peripheral Reset Controller >> +==================================================== >> + >> +The RCC IP is both a reset and a clock controller. This documentation only >> +documents the reset part. >> + >> +Please also refer to reset.txt in this directory for common reset >> +controller binding usage. >> + >> +Required properties: >> +- compatible: Should be "st,stm32-rcc" >> +- reg: should be register base and length as documented in the >> + datasheet >> +- #reset-cells: 1, see below >> + >> +example: >> + >> +rcc: reset at 40023800 { >> + #reset-cells = <1>; >> + compatible = "st,stm32-rcc"; >> + reg = <0x40023800 0x400>; >> +}; >> + >> +Specifying softreset control of devices >> +======================================= >> + >> +Device nodes should specify the reset channel required in their "resets" >> +property, containing a phandle to the reset device node and an index specifying >> +which channel to use. >> +The index is the bit number within the RCC registers bank, starting from RCC >> +base address. >> +It is calculated as: index = register_offset / 4 * 32 + bit_offset. >> +Where bit_offset is the bit offset within the register. >> +For example, for CRC reset: >> + crc = AHB1RSTR_offset / 4 * 32 + CRCRST_bit_offset = 0x10 / 4 * 32 + 12 = 140 > I see you decided to keep the register offset encoded in the reset > index. > >> + >> +To simplify the usagen and to share bit definition with the clock driver of > s/usagen/usage/ ok >> +the RCC IP, macros are available to generate the index in human-readble >> +format. >> + >> +For STM32F4 series, the macro are available here: >> + - include/dt-bindings/mfd/stm32f4-rcc.h > If DT and ARM/STI and maintainers agree with the binding and header > macros, I'm inclined to take patches 1-3. > > regards > Philipp > Thanks! Best Regards Gabriel