From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1752730AbcGFHpI (ORCPT ); Wed, 6 Jul 2016 03:45:08 -0400 Received: from mx07-00178001.pphosted.com ([62.209.51.94]:3565 "EHLO mx07-00178001.pphosted.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751031AbcGFHpD (ORCPT ); Wed, 6 Jul 2016 03:45:03 -0400 Subject: Re: [PATCH 3/4] drivers: reset: Add STM32 reset driver To: Philipp Zabel References: <1467640052-6770-1-git-send-email-gabriel.fernandez@st.com> <1467640052-6770-3-git-send-email-gabriel.fernandez@st.com> <1467725309.2978.63.camel@pengutronix.de> CC: Rob Herring , Mark Rutland , Maxime Coquelin , Russell King , , , , , From: Gabriel Fernandez Message-ID: <577CB6DD.5040502@st.com> Date: Wed, 6 Jul 2016 09:44:29 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.8.0 MIME-Version: 1.0 In-Reply-To: <1467725309.2978.63.camel@pengutronix.de> Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit X-Originating-IP: [10.48.0.158] X-Proofpoint-Virus-Version: vendor=fsecure engine=2.50.10432:,, definitions=2016-07-06_05:,, signatures=0 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Philipp, On 07/05/2016 03:28 PM, Philipp Zabel wrote: > Am Montag, den 04.07.2016, 15:47 +0200 schrieb gabriel.fernandez@st.com: >> From: Gabriel Fernandez >> >> The STM32 MCUs family IPs can be reset by accessing some registers >> from the RCC block. >> >> The list of available reset lines is documented in the DT bindings. >> >> Signed-off-by: Maxime Coquelin >> Signed-off-by: Gabriel Fernandez >> --- >> drivers/reset/Makefile | 1 + >> drivers/reset/reset-stm32.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 114 insertions(+) >> create mode 100644 drivers/reset/reset-stm32.c >> >> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile >> index 03dc1bb..3776b7b 100644 >> --- a/drivers/reset/Makefile >> +++ b/drivers/reset/Makefile >> @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o >> obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o >> obj-$(CONFIG_MACH_PISTACHIO) += reset-pistachio.o >> obj-$(CONFIG_ARCH_MESON) += reset-meson.o >> +obj-$(CONFIG_ARCH_STM32) += reset-stm32.o >> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o >> obj-$(CONFIG_ARCH_STI) += sti/ >> obj-$(CONFIG_ARCH_HISI) += hisilicon/ >> diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c >> new file mode 100644 >> index 0000000..be42bff >> --- /dev/null >> +++ b/drivers/reset/reset-stm32.c >> @@ -0,0 +1,113 @@ >> +/* >> + * Copyright (C) Maxime Coquelin 2015 >> + * Author: Maxime Coquelin >> + * License terms: GNU General Public License (GPL), version 2 >> + * >> + * Heavily based on sunxi driver from Maxime Ripard. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +struct stm32_reset_data { >> + spinlock_t lock; >> + void __iomem *membase; >> + struct reset_controller_dev rcdev; >> +}; >> + >> +static int stm32_reset_assert(struct reset_controller_dev *rcdev, >> + unsigned long id) >> +{ >> + struct stm32_reset_data *data = container_of(rcdev, >> + struct stm32_reset_data, >> + rcdev); >> + int bank = id / BITS_PER_LONG; >> + int offset = id % BITS_PER_LONG; >> + unsigned long flags; >> + u32 reg; >> + >> + spin_lock_irqsave(&data->lock, flags); >> + >> + reg = readl_relaxed(data->membase + (bank * 4)); >> + writel_relaxed(reg | BIT(offset), data->membase + (bank * 4)); > Please also switch to the non-relaxed variants. It shouldn't make a > difference here, and as Arnd points out, reduces the risk of new > developers using readl/writel_relaxed without thinking about the > consequences. > Further, this will make the stm32, sunxi, and socfpga accessors look the > same. I'd like to try and combine them after this is merged. > > regards > Philipp > ok no problem, i will fix it. Thanks Gabriel From mboxrd@z Thu Jan 1 00:00:00 1970 From: Gabriel Fernandez Subject: Re: [PATCH 3/4] drivers: reset: Add STM32 reset driver Date: Wed, 6 Jul 2016 09:44:29 +0200 Message-ID: <577CB6DD.5040502@st.com> References: <1467640052-6770-1-git-send-email-gabriel.fernandez@st.com> <1467640052-6770-3-git-send-email-gabriel.fernandez@st.com> <1467725309.2978.63.camel@pengutronix.de> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1467725309.2978.63.camel-bIcnvbaLZ9MEGnE8C9+IrQ@public.gmane.org> Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Philipp Zabel Cc: Rob Herring , Mark Rutland , Maxime Coquelin , Russell King , patrice.chotard-qxv4g6HH51o@public.gmane.org, alexandre.torgue-qxv4g6HH51o@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: devicetree@vger.kernel.org Hi Philipp, On 07/05/2016 03:28 PM, Philipp Zabel wrote: > Am Montag, den 04.07.2016, 15:47 +0200 schrieb gabriel.fernandez-qxv4g6HH51o@public.gmane.org: >> From: Gabriel Fernandez >> >> The STM32 MCUs family IPs can be reset by accessing some registers >> from the RCC block. >> >> The list of available reset lines is documented in the DT bindings. >> >> Signed-off-by: Maxime Coquelin >> Signed-off-by: Gabriel Fernandez >> --- >> drivers/reset/Makefile | 1 + >> drivers/reset/reset-stm32.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 114 insertions(+) >> create mode 100644 drivers/reset/reset-stm32.c >> >> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile >> index 03dc1bb..3776b7b 100644 >> --- a/drivers/reset/Makefile >> +++ b/drivers/reset/Makefile >> @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o >> obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o >> obj-$(CONFIG_MACH_PISTACHIO) += reset-pistachio.o >> obj-$(CONFIG_ARCH_MESON) += reset-meson.o >> +obj-$(CONFIG_ARCH_STM32) += reset-stm32.o >> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o >> obj-$(CONFIG_ARCH_STI) += sti/ >> obj-$(CONFIG_ARCH_HISI) += hisilicon/ >> diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c >> new file mode 100644 >> index 0000000..be42bff >> --- /dev/null >> +++ b/drivers/reset/reset-stm32.c >> @@ -0,0 +1,113 @@ >> +/* >> + * Copyright (C) Maxime Coquelin 2015 >> + * Author: Maxime Coquelin >> + * License terms: GNU General Public License (GPL), version 2 >> + * >> + * Heavily based on sunxi driver from Maxime Ripard. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +struct stm32_reset_data { >> + spinlock_t lock; >> + void __iomem *membase; >> + struct reset_controller_dev rcdev; >> +}; >> + >> +static int stm32_reset_assert(struct reset_controller_dev *rcdev, >> + unsigned long id) >> +{ >> + struct stm32_reset_data *data = container_of(rcdev, >> + struct stm32_reset_data, >> + rcdev); >> + int bank = id / BITS_PER_LONG; >> + int offset = id % BITS_PER_LONG; >> + unsigned long flags; >> + u32 reg; >> + >> + spin_lock_irqsave(&data->lock, flags); >> + >> + reg = readl_relaxed(data->membase + (bank * 4)); >> + writel_relaxed(reg | BIT(offset), data->membase + (bank * 4)); > Please also switch to the non-relaxed variants. It shouldn't make a > difference here, and as Arnd points out, reduces the risk of new > developers using readl/writel_relaxed without thinking about the > consequences. > Further, this will make the stm32, sunxi, and socfpga accessors look the > same. I'd like to try and combine them after this is merged. > > regards > Philipp > ok no problem, i will fix it. Thanks Gabriel -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: gabriel.fernandez@st.com (Gabriel Fernandez) Date: Wed, 6 Jul 2016 09:44:29 +0200 Subject: [PATCH 3/4] drivers: reset: Add STM32 reset driver In-Reply-To: <1467725309.2978.63.camel@pengutronix.de> References: <1467640052-6770-1-git-send-email-gabriel.fernandez@st.com> <1467640052-6770-3-git-send-email-gabriel.fernandez@st.com> <1467725309.2978.63.camel@pengutronix.de> Message-ID: <577CB6DD.5040502@st.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Philipp, On 07/05/2016 03:28 PM, Philipp Zabel wrote: > Am Montag, den 04.07.2016, 15:47 +0200 schrieb gabriel.fernandez at st.com: >> From: Gabriel Fernandez >> >> The STM32 MCUs family IPs can be reset by accessing some registers >> from the RCC block. >> >> The list of available reset lines is documented in the DT bindings. >> >> Signed-off-by: Maxime Coquelin >> Signed-off-by: Gabriel Fernandez >> --- >> drivers/reset/Makefile | 1 + >> drivers/reset/reset-stm32.c | 113 ++++++++++++++++++++++++++++++++++++++++++++ >> 2 files changed, 114 insertions(+) >> create mode 100644 drivers/reset/reset-stm32.c >> >> diff --git a/drivers/reset/Makefile b/drivers/reset/Makefile >> index 03dc1bb..3776b7b 100644 >> --- a/drivers/reset/Makefile >> +++ b/drivers/reset/Makefile >> @@ -4,6 +4,7 @@ obj-$(CONFIG_ARCH_SOCFPGA) += reset-socfpga.o >> obj-$(CONFIG_ARCH_BERLIN) += reset-berlin.o >> obj-$(CONFIG_MACH_PISTACHIO) += reset-pistachio.o >> obj-$(CONFIG_ARCH_MESON) += reset-meson.o >> +obj-$(CONFIG_ARCH_STM32) += reset-stm32.o >> obj-$(CONFIG_ARCH_SUNXI) += reset-sunxi.o >> obj-$(CONFIG_ARCH_STI) += sti/ >> obj-$(CONFIG_ARCH_HISI) += hisilicon/ >> diff --git a/drivers/reset/reset-stm32.c b/drivers/reset/reset-stm32.c >> new file mode 100644 >> index 0000000..be42bff >> --- /dev/null >> +++ b/drivers/reset/reset-stm32.c >> @@ -0,0 +1,113 @@ >> +/* >> + * Copyright (C) Maxime Coquelin 2015 >> + * Author: Maxime Coquelin >> + * License terms: GNU General Public License (GPL), version 2 >> + * >> + * Heavily based on sunxi driver from Maxime Ripard. >> + */ >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +struct stm32_reset_data { >> + spinlock_t lock; >> + void __iomem *membase; >> + struct reset_controller_dev rcdev; >> +}; >> + >> +static int stm32_reset_assert(struct reset_controller_dev *rcdev, >> + unsigned long id) >> +{ >> + struct stm32_reset_data *data = container_of(rcdev, >> + struct stm32_reset_data, >> + rcdev); >> + int bank = id / BITS_PER_LONG; >> + int offset = id % BITS_PER_LONG; >> + unsigned long flags; >> + u32 reg; >> + >> + spin_lock_irqsave(&data->lock, flags); >> + >> + reg = readl_relaxed(data->membase + (bank * 4)); >> + writel_relaxed(reg | BIT(offset), data->membase + (bank * 4)); > Please also switch to the non-relaxed variants. It shouldn't make a > difference here, and as Arnd points out, reduces the risk of new > developers using readl/writel_relaxed without thinking about the > consequences. > Further, this will make the stm32, sunxi, and socfpga accessors look the > same. I'd like to try and combine them after this is merged. > > regards > Philipp > ok no problem, i will fix it. Thanks Gabriel