From mboxrd@z Thu Jan 1 00:00:00 1970 From: Ziyuan Xu Date: Thu, 14 Jul 2016 23:51:34 +0800 Subject: [U-Boot] [PATCH v4 3/4] rockchip: rk3288: add fastboot support In-Reply-To: <668c3bbc-a3fb-04ca-7223-298166b5895d@rock-chips.com> References: <1468479155-1796-1-git-send-email-xzy.xu@rock-chips.com> <1468479155-1796-4-git-send-email-xzy.xu@rock-chips.com> <668c3bbc-a3fb-04ca-7223-298166b5895d@rock-chips.com> Message-ID: <5787B506.9030208@rock-chips.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi William, On 2016?07?14? 19:06, William.wu wrote: > Hi Ziyuan Xu? > > > On 2016/7/14 14:52, Ziyuan Xu wrote: >> From: Xu Ziyuan >> >> Enable fastboot feature on rk3288. >> >> This path doesn't support the fastboot flash function command entirely. >> We will hit "cannot find partition" assertion without specified >> partition environment. Define gpt partition layout in specified board >> such as firefly-rk3288, then enjoy it! >> >> Signed-off-by: Ziyuan Xu >> >> --- >> >> Changes in v4: >> - Add fifo size for rk3288 >> - Get usb_phy's dt_node >> >> Changes in v3: >> - Achieve UOC_CON_OFFSET physical address from DT >> >> Changes in v2: >> - Achieve the regs_phy from DT >> - Update comments a little >> >> arch/arm/dts/rk3288.dtsi | 1 + >> arch/arm/mach-rockchip/board.c | 72 >> +++++++++++++++++++++++++++++++++++++++++ >> include/configs/rk3288_common.h | 26 +++++++++++++++ >> 3 files changed, 99 insertions(+) >> >> diff --git a/arch/arm/dts/rk3288.dtsi b/arch/arm/dts/rk3288.dtsi >> index 3dab0fc..bcf051a 100644 >> --- a/arch/arm/dts/rk3288.dtsi >> +++ b/arch/arm/dts/rk3288.dtsi >> @@ -454,6 +454,7 @@ >> interrupts = ; >> clocks = <&cru HCLK_OTG0>; >> clock-names = "otg"; >> + dr_mode = "otg"; >> phys = <&usbphy0>; >> phy-names = "usb2-phy"; >> status = "disabled"; >> diff --git a/arch/arm/mach-rockchip/board.c >> b/arch/arm/mach-rockchip/board.c >> index 816540e..ab41877 100644 >> --- a/arch/arm/mach-rockchip/board.c >> +++ b/arch/arm/mach-rockchip/board.c >> @@ -52,6 +52,78 @@ void lowlevel_init(void) >> { >> } >> +#if defined(CONFIG_USB_GADGET) && defined(CONFIG_USB_GADGET_DWC2_OTG) >> +#include >> +#include >> + >> +static struct dwc2_plat_otg_data rk3288_otg_data = { >> + .rx_fifo_sz = 512, >> + .np_tx_fifo_sz = 16, >> + .tx_fifo_sz = 512, >> +}; >> + > rk3288 otg port total fifo size is only 0x3cc ?972?this value is in > terms of 32-bit words?? > read from GHWCFG3 register bit[31:16], it's smaller than the total > fifo size you configured. > I understand what you concern, but fifo size is in terms of 1 byte above, please take a look on v4 2/4(http://patchwork.ozlabs.org/patch/648237/).I remove >> 2 on the former code. Let me know if you still disagree with it. Thanks! >> +int board_usb_init(int index, enum usb_init_type init) >> +{ >> + int node, phy_node; >> + const char *mode; >> + bool matched = false; >> + const void *blob = gd->fdt_blob; >> + u32 grf_phy_offset; >> + >> + /* find the usb_otg node */ >> + node = fdt_node_offset_by_compatible(blob, -1, >> + "rockchip,rk3288-usb"); >> + >> + while (node > 0) { >> + mode = fdt_getprop(blob, node, "dr_mode", NULL); >> + if (mode && strcmp(mode, "otg") == 0) { >> + matched = true; >> + break; >> + } >> + >> + node = fdt_node_offset_by_compatible(blob, node, >> + "rockchip,rk3288-usb"); >> + } >> + if (!matched) { >> + debug("Not found usb_otg device\n"); >> + return -ENODEV; >> + } >> + rk3288_otg_data.regs_otg = fdtdec_get_addr(blob, node, "reg"); >> + >> + node = fdtdec_lookup_phandle(blob, node, "phys"); >> + if (node <= 0) { >> + debug("Not found usb phy device\n"); >> + return -ENODEV; >> + } >> + >> + phy_node = fdt_parent_offset(blob, node); >> + if (phy_node <= 0) { >> + debug("Not found usb phy device\n"); >> + return -ENODEV; >> + } >> + >> + rk3288_otg_data.phy_of_node = phy_node; >> + grf_phy_offset = fdtdec_get_addr(blob, node, "reg"); >> + >> + /* find the grf node */ >> + node = fdt_node_offset_by_compatible(blob, -1, >> + "rockchip,rk3288-grf"); >> + if (node <= 0) { >> + debug("Not found grf device\n"); >> + return -ENODEV; >> + } >> + rk3288_otg_data.regs_phy = grf_phy_offset + >> + fdtdec_get_addr(blob, node, "reg"); >> + >> + return dwc2_udc_probe(&rk3288_otg_data); >> +} >> + >> +int board_usb_cleanup(int index, enum usb_init_type init) >> +{ >> + return 0; >> +} >> +#endif >> + >> static int do_clock(cmd_tbl_t *cmdtp, int flag, int argc, >> char * const argv[]) >> { >> diff --git a/include/configs/rk3288_common.h >> b/include/configs/rk3288_common.h >> index 8adc26f..2040cdd 100644 >> --- a/include/configs/rk3288_common.h >> +++ b/include/configs/rk3288_common.h >> @@ -79,6 +79,32 @@ >> #define CONFIG_SPI >> #define CONFIG_SF_DEFAULT_SPEED 20000000 >> +/* usb otg */ >> +#define CONFIG_USB_GADGET >> +#define CONFIG_USB_GADGET_DUALSPEED >> +#define CONFIG_USB_GADGET_DWC2_OTG >> +#define CONFIG_ROCKCHIP_USB2_PHY >> +#define CONFIG_USB_GADGET_VBUS_DRAW 0 >> + >> +/* fastboot */ >> +#define CONFIG_CMD_FASTBOOT >> +#define CONFIG_USB_FUNCTION_FASTBOOT >> +#define CONFIG_FASTBOOT_FLASH >> +#define CONFIG_FASTBOOT_FLASH_MMC_DEV 1 /* eMMC */ >> +/* stroe safely fastboot buffer data to the middle of bank */ >> +#define CONFIG_FASTBOOT_BUF_ADDR (CONFIG_SYS_SDRAM_BASE \ >> + + SDRAM_BANK_SIZE / 2) >> +#define CONFIG_FASTBOOT_BUF_SIZE 0x08000000 >> + >> +#define CONFIG_USB_GADGET_DOWNLOAD >> +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" >> +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 >> +#define CONFIG_G_DNL_PRODUCT_NUM 0x320a >> + >> +/* Enable gpt partition table */ >> +#define CONFIG_CMD_GPT >> +#define CONFIG_EFI_PARTITION >> + >> #ifndef CONFIG_SPL_BUILD >> #include > > > >