From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:51764) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPDpq-0007ph-VO for qemu-devel@nongnu.org; Mon, 18 Jul 2016 15:04:11 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bPDpk-0003SX-Vm for qemu-devel@nongnu.org; Mon, 18 Jul 2016 15:04:09 -0400 Received: from mail-lf0-x232.google.com ([2a00:1450:4010:c07::232]:33930) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bPDpk-0003SK-OC for qemu-devel@nongnu.org; Mon, 18 Jul 2016 15:04:04 -0400 Received: by mail-lf0-x232.google.com with SMTP id l69so81571159lfg.1 for ; Mon, 18 Jul 2016 12:04:04 -0700 (PDT) References: <1468851450-9863-1-git-send-email-pbonzini@redhat.com> <578D0938.2050004@gmail.com> <578D0A60.4020608@gmail.com> <8c52110d-c009-087c-be04-3920d97af323@redhat.com> <578D0CD6.3080005@gmail.com> <4c479cb3-a8ef-caab-4dbc-3bfd014c7a0a@redhat.com> <578D0F42.4040203@gmail.com> <84ba6ace-e0bd-515a-5194-2e6704d22805@redhat.com> <578D1126.4060803@gmail.com> <578D1285.8060303@gmail.com> <67224898-07f6-d7a1-283f-a764f51a4993@redhat.com> From: Sergey Fedorov Message-ID: <578D2821.6010408@gmail.com> Date: Mon, 18 Jul 2016 22:04:01 +0300 MIME-Version: 1.0 In-Reply-To: <67224898-07f6-d7a1-283f-a764f51a4993@redhat.com> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH] atomics: add volatile_read/volatile_set List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Paolo Bonzini , qemu-devel@nongnu.org Cc: sergey.fedorov@linaro.org, alex.bennee@linaro.org On 18/07/16 20:58, Paolo Bonzini wrote: > > On 18/07/2016 19:31, Sergey Fedorov wrote: >> On 18/07/16 20:28, Paolo Bonzini wrote: >>> On 18/07/2016 19:25, Sergey Fedorov wrote: >>>>>> @@ -753,14 +753,14 @@ static inline void cpu_get_invalid_tb_cpu_state(target_ulong *pc, >>>>>> target_ulong *cs_base, >>>>>> uint32_t *flags) >>>>>> { >>>>>> - *cs_base = -1; /* npc must be a multible of 4 */ >>>>>> + *flags = TB_FLAG_MMU_MASK; >>>>>> } >>>> Hmm, not sure if it is really simpler to follow. Maybe " |= 1;" anyway? >>> |= 1 has the problem that tb_mark_invalid doesn't pass TB's tuple into >>> cpu_get_invalid_tb_cpu_state, and I didn't want to change that. I'll >>> add a comment, >>> >>> /* TB_FLAG_MMU_MASK is not a valid MMU index, which makes it is an >>> * impossible flag combination for valid TBs. >>> */ >>> >> I wonder if using a dedicated field to mark TBs invalid would be so slow >> that we couldn't afford it... > We could, but it would be slower too. :) How much performance do we really need and how much performance can we loose introducing such a flag? We should yet gain something reducing tb_lock contention. Maybe it is worthwhile to use a dedicated flag to keep code more clear? There's always a question of balance between code structure and maintainability (future of the TCG) on one hand and performance (present of the TCG) on the other hand. Kind regards, Sergey > > "Just make flags=-1 invalid" is probably a valid one too. There are > many ways to implement it: use less than 32 bits (or equivalently > reserve one bit for invalid TBs), ensure some combos are invalid, etc. > It would probably be valid for all current targets, since no one uses 32 > bits. ARM is the closest to exhausting flag space probably. > > Still, I like your patches very much so I'd like to proceed with them, > only with some changes to fix compilation on 32-bit hosts. > > Paolo