From: Jaehoon Chung <jh80.chung@samsung.com>
To: u-boot@lists.denx.de
Subject: [U-Boot] [PATCH 2/2] mmc: rockchip: add clock init
Date: Mon, 25 Jul 2016 14:09:44 +0900 [thread overview]
Message-ID: <57959F18.1090609@samsung.com> (raw)
In-Reply-To: <1469422259-16952-3-git-send-email-kever.yang@rock-chips.com>
Hi Kever,
On 07/25/2016 01:50 PM, Kever Yang wrote:
> Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
> ---
>
> drivers/mmc/rockchip_sdhci.c | 10 +++++++++-
> include/configs/rk3399_common.h | 2 +-
> 2 files changed, 10 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/mmc/rockchip_sdhci.c b/drivers/mmc/rockchip_sdhci.c
> index 023c29b..a761a86 100644
> --- a/drivers/mmc/rockchip_sdhci.c
> +++ b/drivers/mmc/rockchip_sdhci.c
> @@ -7,6 +7,7 @@
> */
>
> #include <common.h>
> +#include <clk.h>
> #include <dm.h>
> #include <fdtdec.h>
> #include <libfdt.h>
> @@ -32,15 +33,22 @@ static int arasan_sdhci_probe(struct udevice *dev)
> struct rockchip_sdhc_plat *plat = dev_get_platdata(dev);
> struct rockchip_sdhc *prv = dev_get_priv(dev);
> struct sdhci_host *host = &prv->host;
> + struct clk clk;
> int ret;
> u32 caps;
>
> host->version = sdhci_readw(host, SDHCI_HOST_VERSION);
> host->quirks = SDHCI_QUIRK_WAIT_SEND_CMD;
>
> + ret = clk_get_by_index(dev, 0, &clk);
> + if (ret < 0)
> + debug("%s get clock fail\n", __func__);
> +
> + ret = clk_set_rate(&clk, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ);
Even if failed to get the clk, clk_set_rate() is called...right?
> +
> caps = sdhci_readl(host, SDHCI_CAPABILITIES);
> ret = sdhci_setup_cfg(&plat->cfg, dev->name, host->bus_width,
> - caps, CONFIG_ROCKCHIP_SDHCI_MAX_FREQ, EMMC_MIN_FREQ,
> + caps, ret, EMMC_MIN_FREQ,
Don't use "ret"..use the meaningful variable for maximum clock.
> host->version, host->quirks, 0);
>
> host->mmc = &plat->mmc;
> diff --git a/include/configs/rk3399_common.h b/include/configs/rk3399_common.h
> index 6ce1aa7..eacbe4b 100644
> --- a/include/configs/rk3399_common.h
> +++ b/include/configs/rk3399_common.h
> @@ -32,7 +32,7 @@
> #define CONFIG_GENERIC_MMC
> #define CONFIG_SDHCI
> #define CONFIG_BOUNCE_BUFFER
> -#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ 200000000
> +#define CONFIG_ROCKCHIP_SDHCI_MAX_FREQ (198*1000000)
Why change from 200MHz to 198MHz?
Best Regards,
Jaehoon Chung
>
> #define CONFIG_FAT_WRITE
>
>
next prev parent reply other threads:[~2016-07-25 5:09 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-07-25 4:50 [U-Boot] [PATCH 0/2] rk3399: add soc basic driver support Kever Yang
2016-07-25 4:50 ` [U-Boot] [PATCH 1/2] rk3399: add basic soc driver Kever Yang
2016-07-25 6:58 ` Kever Yang
2016-07-28 3:11 ` Simon Glass
2016-07-25 4:50 ` [U-Boot] [PATCH 2/2] mmc: rockchip: add clock init Kever Yang
2016-07-25 5:09 ` Jaehoon Chung [this message]
2016-07-25 7:34 ` Kever Yang
2016-07-28 3:11 ` Simon Glass
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