From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751811AbcHAHxN (ORCPT ); Mon, 1 Aug 2016 03:53:13 -0400 Received: from mailout2.samsung.com ([203.254.224.25]:45122 "EHLO mailout2.samsung.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750707AbcHAHwc (ORCPT ); Mon, 1 Aug 2016 03:52:32 -0400 MIME-version: 1.0 Content-type: text/plain; charset=UTF-8 X-AuditID: cbfee68d-f79286d000007a9a-7e-579efd293825 Content-transfer-encoding: 8BIT Message-id: <579EFD28.5070404@samsung.com> Date: Mon, 01 Aug 2016 16:41:28 +0900 From: Chanwoo Choi User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:31.0) Gecko/20100101 Thunderbird/31.6.0 To: Lin Huang , heiko@sntech.de Cc: tixy@linaro.org, dbasehore@chromium.org, airlied@linux.ie, mturquette@baylibre.com, typ@rock-chips.com, sboyd@codeaurora.org, linux-kernel@vger.kernel.org, dri-devel@lists.freedesktop.org, dianders@chromium.org, linux-rockchip@lists.infradead.org, kyungmin.park@samsung.com, myungjoo.ham@samsung.com, linux-arm-kernel@lists.infradead.org, mark.yao@rock-chips.com Subject: Re: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller References: <1469779021-10426-1-git-send-email-hl@rock-chips.com> <1469779021-10426-6-git-send-email-hl@rock-chips.com> In-reply-to: <1469779021-10426-6-git-send-email-hl@rock-chips.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFnrJIsWRmVeSWpSXmKPExsWyRsSkUFfz77xwg2/PpC16z51ksni1eQ+b xdllB9ksrnx9z2bx/9FrVosfG04xW5xtesNusenxNVaLy7vmsFl8evCf2WLHlANMFhdPuVrc blzBZvHjTDeLxcL599ktZq+ucxDweH+jld1jdsNFFo/Lfb1MHneu7WHz2P7tAavH/e7jTB6b l9R7/J21n8Wjb8sqRo/t1+Yxe3zeJBfAHcVlk5Kak1mWWqRvl8CVsaXhKGvBEp+Ka9dXsjYw PrftYuTkkBAwkfi/5QYThC0mceHeerYuRi4OIYEVjBLL511hgyk6sv0RO4gtJLCUUeLntQgQ m1dAUOLH5HssXYwcHMwC8hJHLmWDhJkF1CUmzVvEDDHnAaPEj/mP2CDqtSTOnzgMNodFQFXi xKMJrCA2G1B8/4sbbCBzRAUiJLpPVIKERQSMJM5+mc8EModZ4AeTxIedq8HmCAsESLSemsEK seAso8T09a+YQRKcAk4Sb2c0MUMcfYRD4uAsXYhlAhLfJh8CO1RCQFZi0wGoEkmJgytusExg FJuF5J1ZCO/MQvLOAkbmVYyiqQXJBcVJ6UWGesWJucWleel6yfm5mxiBKeD0v2e9OxhvH7A+ xCjAwajEw3sjd164EGtiWXFl7iFGU6AjJjJLiSbnAxNNXkm8obGZkYWpiamxkbmlmZI4r6LU z2AhgfTEktTs1NSC1KL4otKc1OJDjEwcnFINjGuf/etUSGo4bFJh/G3BvrLE1z+LjZ8ofLlW 6PakaZX+CaFr7N8Cotd/PvBJYnPQOmfG6rNrlnmJ5C5ImVJzyvVLeLrQ8ZrLTDU88ZL1jEH7 22oZ1r2u2SM3+VSoqNImsQsqSan7vmh5Ve7/vj77vsvB0HKmuiwbkRMlk/QFz/8xSJCKLGyz UWIpzkg01GIuKk4EABCqhCT8AgAA X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFtrOKsWRmVeSWpSXmKPExsVy+t9jAV3Nv/PCDW7MELHoPXeSyeLV5j1s FmeXHWSzuPL1PZvF/0evWS1+bDjFbHG26Q27xabH11gtLu+aw2bx6cF/ZosdUw4wWVw85Wpx u3EFm8WPM90sFgvn32e3mL26zkHA4/2NVnaP2Q0XWTwu9/Uyedy5tofNY/u3B6we97uPM3ls XlLv8XfWfhaPvi2rGD22X5vH7PF5k1wAd1QDo01GamJKapFCal5yfkpmXrqtkndwvHO8qZmB oa6hpYW5kkJeYm6qrZKLT4CuW2YO0D9KCmWJOaVAoYDE4mIlfTtME0JD3HQtYBojdH1DguB6 jAzQQMIaxowtDUdZC5b4VFy7vpK1gfG5bRcjJ4eEgInEke2P2CFsMYkL99azgdhCAksZJX5e iwCxeQUEJX5MvsfSxcjBwSwgL3HkUjZImFlAXWLSvEXMXYxcQOUPGCV+zH/EBlGvJXH+xGGw mSwCqhInHk1gBbHZgOL7X9xgA5kjKhAh0X2iEiQsImAkcfbLfCaQOcwCP5gkPuxcDTZHWCBA ovXUDFaIBWcZJaavf8UMkuAUcJJ4O6OJeQKjwCwk981CuG8WkvsWMDKvYpRILUguKE5KzzXK Sy3XK07MLS7NS9dLzs/dxAhONM+kdzAe3uV+iFGAg1GJh1dDbl64EGtiWXFl7iFGCQ5mJRHe xT+BQrwpiZVVqUX58UWlOanFhxhNgR6cyCwlmpwPTIJ5JfGGxiZmRpZG5oYWRsbmSuK8j/+v CxMSSE8sSc1OTS1ILYLpY+LglGpglAm7f3+t3InblwK5riyL/ZUoIPQ7dWFO05lJJ1+ovXma vLg1fgtPTc0ZN+W6pa/Evp733Ow+l8XdNbrkRGucn9Ij/qdfL0/j0744zbT2Q1puf8zp/35P T969ccfc20GZq/RXMHvb/7CA4H1MJzr8+56pH5h6I0XyQPd8fot/S/Z68LUtmugnrMRSnJFo qMVcVJwIANijIXBKAwAA DLP-Filter: Pass X-MTR: 20000000000000000@CPGS X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Lin, Because you remove the 'RFC' prefix on patch title, I think that you better to make the documentation as following: - Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt Regards, Chanwoo Choi On 2016년 07월 29일 16:56, Lin Huang wrote: > on rk3399 platform, there is dfi conroller can monitor > ddr load, base on this result, we can do ddr freqency > scaling. > > Signed-off-by: Lin Huang > Acked-by: Chanwoo Choi > --- > Changes in v4: > - None > > Changes in v3: > - None > > Changes in v2: > - use clk_disable_unprepare and clk_enable_prepare > - remove clk_enable_prepare in probe > - remove rockchip_dfi_remove function > > Changes in v1: > - None > > drivers/devfreq/event/Kconfig | 7 + > drivers/devfreq/event/Makefile | 1 + > drivers/devfreq/event/rockchip-dfi.c | 253 +++++++++++++++++++++++++++++++++++ > 3 files changed, 261 insertions(+) > create mode 100644 drivers/devfreq/event/rockchip-dfi.c > > diff --git a/drivers/devfreq/event/Kconfig b/drivers/devfreq/event/Kconfig > index a11720a..ff9279f 100644 > --- a/drivers/devfreq/event/Kconfig > +++ b/drivers/devfreq/event/Kconfig > @@ -22,4 +22,11 @@ config DEVFREQ_EVENT_EXYNOS_PPMU > (Platform Performance Monitoring Unit) counters to estimate the > utilization of each module. > > +config DEVFREQ_EVENT_ROCKCHIP_DFI > + tristate "ROCKCHIP DFI DEVFREQ event Driver" > + depends on ARCH_ROCKCHIP > + help > + This add the devfreq-event driver for Rockchip SoC. It provides DFI > + (DDR Monitor Module) driver to count ddr load. > + > endif # PM_DEVFREQ_EVENT > diff --git a/drivers/devfreq/event/Makefile b/drivers/devfreq/event/Makefile > index be146ea..e3f88fc 100644 > --- a/drivers/devfreq/event/Makefile > +++ b/drivers/devfreq/event/Makefile > @@ -1,2 +1,3 @@ > # Exynos DEVFREQ Event Drivers > obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o > +obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o > diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c > new file mode 100644 > index 0000000..96a0307 > --- /dev/null > +++ b/drivers/devfreq/event/rockchip-dfi.c > @@ -0,0 +1,253 @@ > +/* > + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd > + * Author: Lin Huang > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define RK3399_DMC_NUM_CH 2 > + > +/* DDRMON_CTRL */ > +#define DDRMON_CTRL 0x04 > +#define CLR_DDRMON_CTRL (0x1f0000 << 0) > +#define LPDDR4_EN (0x10001 << 4) > +#define HARDWARE_EN (0x10001 << 3) > +#define LPDDR3_EN (0x10001 << 2) > +#define SOFTWARE_EN (0x10001 << 1) > +#define TIME_CNT_EN (0x10001 << 0) > + > +#define DDRMON_CH0_COUNT_NUM 0x28 > +#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c > +#define DDRMON_CH1_COUNT_NUM 0x3c > +#define DDRMON_CH1_DFI_ACCESS_NUM 0x40 > + > +/* pmu grf */ > +#define PMUGRF_OS_REG2 0x308 > +#define DDRTYPE_SHIFT 13 > +#define DDRTYPE_MASK 7 > + > +enum { > + DDR3 = 3, > + LPDDR3 = 6, > + LPDDR4 = 7, > + UNUSED = 0xFF > +}; > + > +struct dmc_usage { > + u32 access; > + u32 total; > +}; > + > +struct rockchip_dfi { > + struct devfreq_event_dev *edev; > + struct devfreq_event_desc *desc; > + struct dmc_usage ch_usage[RK3399_DMC_NUM_CH]; > + struct device *dev; > + void __iomem *regs; > + struct regmap *regmap_pmu; > + struct clk *clk; > +}; > + > +static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + void __iomem *dfi_regs = info->regs; > + u32 val; > + u32 ddr_type; > + > + /* get ddr type */ > + regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val); > + ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK; > + > + /* clear DDRMON_CTRL setting */ > + writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); > + > + /* set ddr type to dfi */ > + if (ddr_type == LPDDR3) > + writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); > + else if (ddr_type == LPDDR4) > + writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); > + > + /* enable count, use software mode */ > + writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL); > +} > + > +static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + void __iomem *dfi_regs = info->regs; > + u32 val; > + > + val = readl_relaxed(dfi_regs + DDRMON_CTRL); > + val &= ~SOFTWARE_EN; > + writel_relaxed(val, dfi_regs + DDRMON_CTRL); > +} > + > +static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + u32 tmp, max = 0; > + u32 i, busier_ch = 0; > + void __iomem *dfi_regs = info->regs; > + > + rockchip_dfi_stop_hardware_counter(edev); > + > + /* Find out which channel is busier */ > + for (i = 0; i < RK3399_DMC_NUM_CH; i++) { > + info->ch_usage[i].access = readl_relaxed(dfi_regs + > + DDRMON_CH0_DFI_ACCESS_NUM + i * 20); > + info->ch_usage[i].total = readl_relaxed(dfi_regs + > + DDRMON_CH0_COUNT_NUM + i * 20); > + tmp = info->ch_usage[i].access; > + if (tmp > max) { > + busier_ch = i; > + max = tmp; > + } > + } > + rockchip_dfi_start_hardware_counter(edev); > + > + return busier_ch; > +} > + > +static int rockchip_dfi_disable(struct devfreq_event_dev *edev) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + > + rockchip_dfi_stop_hardware_counter(edev); > + clk_disable_unprepare(info->clk); > + > + return 0; > +} > + > +static int rockchip_dfi_enable(struct devfreq_event_dev *edev) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + int ret; > + > + ret = clk_prepare_enable(info->clk); > + if (ret) { > + dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret); > + return ret; > + } > + > + rockchip_dfi_start_hardware_counter(edev); > + return 0; > +} > + > +static int rockchip_dfi_set_event(struct devfreq_event_dev *edev) > +{ > + return 0; > +} > + > +static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, > + struct devfreq_event_data *edata) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + int busier_ch; > + > + busier_ch = rockchip_dfi_get_busier_ch(edev); > + > + edata->load_count = info->ch_usage[busier_ch].access; > + edata->total_count = info->ch_usage[busier_ch].total; > + > + return 0; > +} > + > +static const struct devfreq_event_ops rockchip_dfi_ops = { > + .disable = rockchip_dfi_disable, > + .enable = rockchip_dfi_enable, > + .get_event = rockchip_dfi_get_event, > + .set_event = rockchip_dfi_set_event, > +}; > + > +static const struct of_device_id rockchip_dfi_id_match[] = { > + { .compatible = "rockchip,rk3399-dfi" }, > + { }, > +}; > + > +static int rockchip_dfi_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct rockchip_dfi *data; > + struct resource *res; > + struct devfreq_event_desc *desc; > + struct device_node *np = pdev->dev.of_node, *node; > + > + data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + data->regs = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(data->regs)) > + return PTR_ERR(data->regs); > + > + data->clk = devm_clk_get(dev, "pclk_ddr_mon"); > + if (IS_ERR(data->clk)) { > + dev_err(dev, "Cannot get the clk dmc_clk\n"); > + return PTR_ERR(data->clk); > + }; > + > + /* try to find the optional reference to the pmu syscon */ > + node = of_parse_phandle(np, "rockchip,pmu", 0); > + if (node) { > + data->regmap_pmu = syscon_node_to_regmap(node); > + if (IS_ERR(data->regmap_pmu)) > + return PTR_ERR(data->regmap_pmu); > + } > + data->dev = dev; > + > + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); > + if (!desc) > + return -ENOMEM; > + > + desc->ops = &rockchip_dfi_ops; > + desc->driver_data = data; > + desc->name = np->name; > + data->desc = desc; > + > + data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc); > + if (IS_ERR(data->edev)) { > + dev_err(&pdev->dev, > + "failed to add devfreq-event device\n"); > + return PTR_ERR(data->edev); > + } > + > + platform_set_drvdata(pdev, data); > + > + return 0; > +} > + > +static struct platform_driver rockchip_dfi_driver = { > + .probe = rockchip_dfi_probe, > + .driver = { > + .name = "rockchip-dfi", > + .of_match_table = rockchip_dfi_id_match, > + }, > +}; > +module_platform_driver(rockchip_dfi_driver); > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Lin Huang "); > +MODULE_DESCRIPTION("Rockchip dfi driver"); > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chanwoo Choi Subject: Re: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller Date: Mon, 01 Aug 2016 16:41:28 +0900 Message-ID: <579EFD28.5070404@samsung.com> References: <1469779021-10426-1-git-send-email-hl@rock-chips.com> <1469779021-10426-6-git-send-email-hl@rock-chips.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-reply-to: <1469779021-10426-6-git-send-email-hl-TNX95d0MmH7DzftRWevZcw@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "Linux-rockchip" Errors-To: linux-rockchip-bounces+glpar-linux-rockchip=m.gmane.org-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org To: Lin Huang , heiko-4mtYJXux2i+zQB+pC5nmwQ@public.gmane.org Cc: tixy-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org, typ-TNX95d0MmH7DzftRWevZcw@public.gmane.org, airlied-cv59FeDIM0c@public.gmane.org, mturquette-rdvid1DuHRBWk0Htik3J/w@public.gmane.org, dbasehore-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, sboyd-sgV2jX0FEOL9JmXXK+q4OQ@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, dri-devel-PD4FTy7X32lNgt0PjOBp9y5qC8QIuHrW@public.gmane.org, dianders-F7+t8E8rja9g9hUCZPvPmw@public.gmane.org, linux-rockchip-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, kyungmin.park-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org, myungjoo.ham-Sze3O3UU22JBDgjK7y7TUQ@public.gmane.org, linux-arm-kernel-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org, mark.yao-TNX95d0MmH7DzftRWevZcw@public.gmane.org List-Id: linux-rockchip.vger.kernel.org SGkgTGluLAoKQmVjYXVzZSB5b3UgcmVtb3ZlIHRoZSAnUkZDJyBwcmVmaXggb24gcGF0Y2ggdGl0 bGUsCkkgdGhpbmsgdGhhdCB5b3UgYmV0dGVyIHRvIG1ha2UgdGhlIGRvY3VtZW50YXRpb24gYXMg Zm9sbG93aW5nOiAKLSBEb2N1bWVudGF0aW9uL2RldmljZXRyZWUvYmluZGluZ3MvZGV2ZnJlcS9l dmVudC9yb2NrY2hpcC1kZmkudHh0CgpSZWdhcmRzLApDaGFud29vIENob2kKCk9uIDIwMTbrhYQg MDfsm5QgMjnsnbwgMTY6NTYsIExpbiBIdWFuZyB3cm90ZToKPiBvbiByazMzOTkgcGxhdGZvcm0s IHRoZXJlIGlzIGRmaSBjb25yb2xsZXIgY2FuIG1vbml0b3IKPiBkZHIgbG9hZCwgYmFzZSBvbiB0 aGlzIHJlc3VsdCwgd2UgY2FuIGRvIGRkciBmcmVxZW5jeQo+IHNjYWxpbmcuCj4gCj4gU2lnbmVk LW9mZi1ieTogTGluIEh1YW5nIDxobEByb2NrLWNoaXBzLmNvbT4KPiBBY2tlZC1ieTogQ2hhbndv byBDaG9pIDxjdzAwLmNob2lAc2Ftc3VuZy5jb20+Cj4gLS0tCj4gQ2hhbmdlcyBpbiB2NDoKPiAt IE5vbmUKPiAKPiBDaGFuZ2VzIGluIHYzOgo+IC0gTm9uZQo+IAo+IENoYW5nZXMgaW4gdjI6Cj4g LSB1c2UgY2xrX2Rpc2FibGVfdW5wcmVwYXJlIGFuZCBjbGtfZW5hYmxlX3ByZXBhcmUKPiAtIHJl bW92ZSBjbGtfZW5hYmxlX3ByZXBhcmUgaW4gcHJvYmUKPiAtIHJlbW92ZSByb2NrY2hpcF9kZmlf cmVtb3ZlIGZ1bmN0aW9uCj4gCj4gQ2hhbmdlcyBpbiB2MToKPiAtIE5vbmUKPiAKPiAgZHJpdmVy cy9kZXZmcmVxL2V2ZW50L0tjb25maWcgICAgICAgIHwgICA3ICsKPiAgZHJpdmVycy9kZXZmcmVx L2V2ZW50L01ha2VmaWxlICAgICAgIHwgICAxICsKPiAgZHJpdmVycy9kZXZmcmVxL2V2ZW50L3Jv Y2tjaGlwLWRmaS5jIHwgMjUzICsrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrKysrCj4g IDMgZmlsZXMgY2hhbmdlZCwgMjYxIGluc2VydGlvbnMoKykKPiAgY3JlYXRlIG1vZGUgMTAwNjQ0 IGRyaXZlcnMvZGV2ZnJlcS9ldmVudC9yb2NrY2hpcC1kZmkuYwo+IAo+IGRpZmYgLS1naXQgYS9k cml2ZXJzL2RldmZyZXEvZXZlbnQvS2NvbmZpZyBiL2RyaXZlcnMvZGV2ZnJlcS9ldmVudC9LY29u ZmlnCj4gaW5kZXggYTExNzIwYS4uZmY5Mjc5ZiAxMDA2NDQKPiAtLS0gYS9kcml2ZXJzL2RldmZy ZXEvZXZlbnQvS2NvbmZpZwo+ICsrKyBiL2RyaXZlcnMvZGV2ZnJlcS9ldmVudC9LY29uZmlnCj4g QEAgLTIyLDQgKzIyLDExIEBAIGNvbmZpZyBERVZGUkVRX0VWRU5UX0VYWU5PU19QUE1VCj4gIAkg IChQbGF0Zm9ybSBQZXJmb3JtYW5jZSBNb25pdG9yaW5nIFVuaXQpIGNvdW50ZXJzIHRvIGVzdGlt YXRlIHRoZQo+ICAJICB1dGlsaXphdGlvbiBvZiBlYWNoIG1vZHVsZS4KPiAgCj4gK2NvbmZpZyBE RVZGUkVRX0VWRU5UX1JPQ0tDSElQX0RGSQo+ICsJdHJpc3RhdGUgIlJPQ0tDSElQIERGSSBERVZG UkVRIGV2ZW50IERyaXZlciIKPiArCWRlcGVuZHMgb24gQVJDSF9ST0NLQ0hJUAo+ICsJaGVscAo+ ICsJICBUaGlzIGFkZCB0aGUgZGV2ZnJlcS1ldmVudCBkcml2ZXIgZm9yIFJvY2tjaGlwIFNvQy4g SXQgcHJvdmlkZXMgREZJCj4gKwkgIChERFIgTW9uaXRvciBNb2R1bGUpIGRyaXZlciB0byBjb3Vu dCBkZHIgbG9hZC4KPiArCj4gIGVuZGlmICMgUE1fREVWRlJFUV9FVkVOVAo+IGRpZmYgLS1naXQg YS9kcml2ZXJzL2RldmZyZXEvZXZlbnQvTWFrZWZpbGUgYi9kcml2ZXJzL2RldmZyZXEvZXZlbnQv TWFrZWZpbGUKPiBpbmRleCBiZTE0NmVhLi5lM2Y4OGZjIDEwMDY0NAo+IC0tLSBhL2RyaXZlcnMv ZGV2ZnJlcS9ldmVudC9NYWtlZmlsZQo+ICsrKyBiL2RyaXZlcnMvZGV2ZnJlcS9ldmVudC9NYWtl ZmlsZQo+IEBAIC0xLDIgKzEsMyBAQAo+ICAjIEV4eW5vcyBERVZGUkVRIEV2ZW50IERyaXZlcnMK PiAgb2JqLSQoQ09ORklHX0RFVkZSRVFfRVZFTlRfRVhZTk9TX1BQTVUpICs9IGV4eW5vcy1wcG11 Lm8KPiArb2JqLSQoQ09ORklHX0RFVkZSRVFfRVZFTlRfUk9DS0NISVBfREZJKSArPSByb2NrY2hp cC1kZmkubwo+IGRpZmYgLS1naXQgYS9kcml2ZXJzL2RldmZyZXEvZXZlbnQvcm9ja2NoaXAtZGZp LmMgYi9kcml2ZXJzL2RldmZyZXEvZXZlbnQvcm9ja2NoaXAtZGZpLmMKPiBuZXcgZmlsZSBtb2Rl IDEwMDY0NAo+IGluZGV4IDAwMDAwMDAuLjk2YTAzMDcKPiAtLS0gL2Rldi9udWxsCj4gKysrIGIv ZHJpdmVycy9kZXZmcmVxL2V2ZW50L3JvY2tjaGlwLWRmaS5jCj4gQEAgLTAsMCArMSwyNTMgQEAK PiArLyoKPiArICogQ29weXJpZ2h0IChjKSAyMDE2LCBGdXpob3UgUm9ja2NoaXAgRWxlY3Ryb25p Y3MgQ28uLCBMdGQKPiArICogQXV0aG9yOiBMaW4gSHVhbmcgPGhsQHJvY2stY2hpcHMuY29tPgo+ ICsgKgo+ICsgKiBUaGlzIHByb2dyYW0gaXMgZnJlZSBzb2Z0d2FyZTsgeW91IGNhbiByZWRpc3Ry aWJ1dGUgaXQgYW5kL29yIG1vZGlmeSBpdAo+ICsgKiB1bmRlciB0aGUgdGVybXMgYW5kIGNvbmRp dGlvbnMgb2YgdGhlIEdOVSBHZW5lcmFsIFB1YmxpYyBMaWNlbnNlLAo+ICsgKiB2ZXJzaW9uIDIs IGFzIHB1Ymxpc2hlZCBieSB0aGUgRnJlZSBTb2Z0d2FyZSBGb3VuZGF0aW9uLgo+ICsgKgo+ICsg KiBUaGlzIHByb2dyYW0gaXMgZGlzdHJpYnV0ZWQgaW4gdGhlIGhvcGUgaXQgd2lsbCBiZSB1c2Vm dWwsIGJ1dCBXSVRIT1VUCj4gKyAqIEFOWSBXQVJSQU5UWTsgd2l0aG91dCBldmVuIHRoZSBpbXBs aWVkIHdhcnJhbnR5IG9mIE1FUkNIQU5UQUJJTElUWSBvcgo+ICsgKiBGSVRORVNTIEZPUiBBIFBB UlRJQ1VMQVIgUFVSUE9TRS4gIFNlZSB0aGUgR05VIEdlbmVyYWwgUHVibGljIExpY2Vuc2UgZm9y Cj4gKyAqIG1vcmUgZGV0YWlscy4KPiArICovCj4gKwo+ICsjaW5jbHVkZSA8bGludXgvY2xrLmg+ Cj4gKyNpbmNsdWRlIDxsaW51eC9kZXZmcmVxLWV2ZW50Lmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9r ZXJuZWwuaD4KPiArI2luY2x1ZGUgPGxpbnV4L2Vyci5oPgo+ICsjaW5jbHVkZSA8bGludXgvaW5p dC5oPgo+ICsjaW5jbHVkZSA8bGludXgvaW8uaD4KPiArI2luY2x1ZGUgPGxpbnV4L21mZC9zeXNj b24uaD4KPiArI2luY2x1ZGUgPGxpbnV4L21vZHVsZS5oPgo+ICsjaW5jbHVkZSA8bGludXgvcGxh dGZvcm1fZGV2aWNlLmg+Cj4gKyNpbmNsdWRlIDxsaW51eC9yZWdtYXAuaD4KPiArI2luY2x1ZGUg PGxpbnV4L3NsYWIuaD4KPiArI2luY2x1ZGUgPGxpbnV4L2xpc3QuaD4KPiArI2luY2x1ZGUgPGxp bnV4L29mLmg+Cj4gKwo+ICsjZGVmaW5lIFJLMzM5OV9ETUNfTlVNX0NICTIKPiArCj4gKy8qIERE Uk1PTl9DVFJMICovCj4gKyNkZWZpbmUgRERSTU9OX0NUUkwJMHgwNAo+ICsjZGVmaW5lIENMUl9E RFJNT05fQ1RSTAkoMHgxZjAwMDAgPDwgMCkKPiArI2RlZmluZSBMUEREUjRfRU4JKDB4MTAwMDEg PDwgNCkKPiArI2RlZmluZSBIQVJEV0FSRV9FTgkoMHgxMDAwMSA8PCAzKQo+ICsjZGVmaW5lIExQ RERSM19FTgkoMHgxMDAwMSA8PCAyKQo+ICsjZGVmaW5lIFNPRlRXQVJFX0VOCSgweDEwMDAxIDw8 IDEpCj4gKyNkZWZpbmUgVElNRV9DTlRfRU4JKDB4MTAwMDEgPDwgMCkKPiArCj4gKyNkZWZpbmUg RERSTU9OX0NIMF9DT1VOVF9OVU0JCTB4MjgKPiArI2RlZmluZSBERFJNT05fQ0gwX0RGSV9BQ0NF U1NfTlVNCTB4MmMKPiArI2RlZmluZSBERFJNT05fQ0gxX0NPVU5UX05VTQkJMHgzYwo+ICsjZGVm aW5lIEREUk1PTl9DSDFfREZJX0FDQ0VTU19OVU0JMHg0MAo+ICsKPiArLyogcG11IGdyZiAqLwo+ ICsjZGVmaW5lIFBNVUdSRl9PU19SRUcyCTB4MzA4Cj4gKyNkZWZpbmUgRERSVFlQRV9TSElGVAkx Mwo+ICsjZGVmaW5lIEREUlRZUEVfTUFTSwk3Cj4gKwo+ICtlbnVtIHsKPiArCUREUjMgPSAzLAo+ ICsJTFBERFIzID0gNiwKPiArCUxQRERSNCA9IDcsCj4gKwlVTlVTRUQgPSAweEZGCj4gK307Cj4g Kwo+ICtzdHJ1Y3QgZG1jX3VzYWdlIHsKPiArCXUzMiBhY2Nlc3M7Cj4gKwl1MzIgdG90YWw7Cj4g K307Cj4gKwo+ICtzdHJ1Y3Qgcm9ja2NoaXBfZGZpIHsKPiArCXN0cnVjdCBkZXZmcmVxX2V2ZW50 X2RldiAqZWRldjsKPiArCXN0cnVjdCBkZXZmcmVxX2V2ZW50X2Rlc2MgKmRlc2M7Cj4gKwlzdHJ1 Y3QgZG1jX3VzYWdlIGNoX3VzYWdlW1JLMzM5OV9ETUNfTlVNX0NIXTsKPiArCXN0cnVjdCBkZXZp Y2UgKmRldjsKPiArCXZvaWQgX19pb21lbSAqcmVnczsKPiArCXN0cnVjdCByZWdtYXAgKnJlZ21h cF9wbXU7Cj4gKwlzdHJ1Y3QgY2xrICpjbGs7Cj4gK307Cj4gKwo+ICtzdGF0aWMgdm9pZCByb2Nr Y2hpcF9kZmlfc3RhcnRfaGFyZHdhcmVfY291bnRlcihzdHJ1Y3QgZGV2ZnJlcV9ldmVudF9kZXYg KmVkZXYpCj4gK3sKPiArCXN0cnVjdCByb2NrY2hpcF9kZmkgKmluZm8gPSBkZXZmcmVxX2V2ZW50 X2dldF9kcnZkYXRhKGVkZXYpOwo+ICsJdm9pZCBfX2lvbWVtICpkZmlfcmVncyA9IGluZm8tPnJl Z3M7Cj4gKwl1MzIgdmFsOwo+ICsJdTMyIGRkcl90eXBlOwo+ICsKPiArCS8qIGdldCBkZHIgdHlw ZSAqLwo+ICsJcmVnbWFwX3JlYWQoaW5mby0+cmVnbWFwX3BtdSwgUE1VR1JGX09TX1JFRzIsICZ2 YWwpOwo+ICsJZGRyX3R5cGUgPSAodmFsID4+IEREUlRZUEVfU0hJRlQpICYgRERSVFlQRV9NQVNL Owo+ICsKPiArCS8qIGNsZWFyIEREUk1PTl9DVFJMIHNldHRpbmcgKi8KPiArCXdyaXRlbF9yZWxh eGVkKENMUl9ERFJNT05fQ1RSTCwgZGZpX3JlZ3MgKyBERFJNT05fQ1RSTCk7Cj4gKwo+ICsJLyog c2V0IGRkciB0eXBlIHRvIGRmaSAqLwo+ICsJaWYgKGRkcl90eXBlID09IExQRERSMykKPiArCQl3 cml0ZWxfcmVsYXhlZChMUEREUjNfRU4sIGRmaV9yZWdzICsgRERSTU9OX0NUUkwpOwo+ICsJZWxz ZSBpZiAoZGRyX3R5cGUgPT0gTFBERFI0KQo+ICsJCXdyaXRlbF9yZWxheGVkKExQRERSNF9FTiwg ZGZpX3JlZ3MgKyBERFJNT05fQ1RSTCk7Cj4gKwo+ICsJLyogZW5hYmxlIGNvdW50LCB1c2Ugc29m dHdhcmUgbW9kZSAqLwo+ICsJd3JpdGVsX3JlbGF4ZWQoU09GVFdBUkVfRU4sIGRmaV9yZWdzICsg RERSTU9OX0NUUkwpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgdm9pZCByb2NrY2hpcF9kZmlfc3RvcF9o YXJkd2FyZV9jb3VudGVyKHN0cnVjdCBkZXZmcmVxX2V2ZW50X2RldiAqZWRldikKPiArewo+ICsJ c3RydWN0IHJvY2tjaGlwX2RmaSAqaW5mbyA9IGRldmZyZXFfZXZlbnRfZ2V0X2RydmRhdGEoZWRl dik7Cj4gKwl2b2lkIF9faW9tZW0gKmRmaV9yZWdzID0gaW5mby0+cmVnczsKPiArCXUzMiB2YWw7 Cj4gKwo+ICsJdmFsID0gcmVhZGxfcmVsYXhlZChkZmlfcmVncyArIEREUk1PTl9DVFJMKTsKPiAr CXZhbCAmPSB+U09GVFdBUkVfRU47Cj4gKwl3cml0ZWxfcmVsYXhlZCh2YWwsIGRmaV9yZWdzICsg RERSTU9OX0NUUkwpOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IHJvY2tjaGlwX2RmaV9nZXRfYnVz aWVyX2NoKHN0cnVjdCBkZXZmcmVxX2V2ZW50X2RldiAqZWRldikKPiArewo+ICsJc3RydWN0IHJv Y2tjaGlwX2RmaSAqaW5mbyA9IGRldmZyZXFfZXZlbnRfZ2V0X2RydmRhdGEoZWRldik7Cj4gKwl1 MzIgdG1wLCBtYXggPSAwOwo+ICsJdTMyIGksIGJ1c2llcl9jaCA9IDA7Cj4gKwl2b2lkIF9faW9t ZW0gKmRmaV9yZWdzID0gaW5mby0+cmVnczsKPiArCj4gKwlyb2NrY2hpcF9kZmlfc3RvcF9oYXJk d2FyZV9jb3VudGVyKGVkZXYpOwo+ICsKPiArCS8qIEZpbmQgb3V0IHdoaWNoIGNoYW5uZWwgaXMg YnVzaWVyICovCj4gKwlmb3IgKGkgPSAwOyBpIDwgUkszMzk5X0RNQ19OVU1fQ0g7IGkrKykgewo+ ICsJCWluZm8tPmNoX3VzYWdlW2ldLmFjY2VzcyA9IHJlYWRsX3JlbGF4ZWQoZGZpX3JlZ3MgKwo+ ICsJCQkJRERSTU9OX0NIMF9ERklfQUNDRVNTX05VTSArIGkgKiAyMCk7Cj4gKwkJaW5mby0+Y2hf dXNhZ2VbaV0udG90YWwgPSByZWFkbF9yZWxheGVkKGRmaV9yZWdzICsKPiArCQkJCUREUk1PTl9D SDBfQ09VTlRfTlVNICsgaSAqIDIwKTsKPiArCQl0bXAgPSBpbmZvLT5jaF91c2FnZVtpXS5hY2Nl c3M7Cj4gKwkJaWYgKHRtcCA+IG1heCkgewo+ICsJCQlidXNpZXJfY2ggPSBpOwo+ICsJCQltYXgg PSB0bXA7Cj4gKwkJfQo+ICsJfQo+ICsJcm9ja2NoaXBfZGZpX3N0YXJ0X2hhcmR3YXJlX2NvdW50 ZXIoZWRldik7Cj4gKwo+ICsJcmV0dXJuIGJ1c2llcl9jaDsKPiArfQo+ICsKPiArc3RhdGljIGlu dCByb2NrY2hpcF9kZmlfZGlzYWJsZShzdHJ1Y3QgZGV2ZnJlcV9ldmVudF9kZXYgKmVkZXYpCj4g K3sKPiArCXN0cnVjdCByb2NrY2hpcF9kZmkgKmluZm8gPSBkZXZmcmVxX2V2ZW50X2dldF9kcnZk YXRhKGVkZXYpOwo+ICsKPiArCXJvY2tjaGlwX2RmaV9zdG9wX2hhcmR3YXJlX2NvdW50ZXIoZWRl dik7Cj4gKwljbGtfZGlzYWJsZV91bnByZXBhcmUoaW5mby0+Y2xrKTsKPiArCj4gKwlyZXR1cm4g MDsKPiArfQo+ICsKPiArc3RhdGljIGludCByb2NrY2hpcF9kZmlfZW5hYmxlKHN0cnVjdCBkZXZm cmVxX2V2ZW50X2RldiAqZWRldikKPiArewo+ICsJc3RydWN0IHJvY2tjaGlwX2RmaSAqaW5mbyA9 IGRldmZyZXFfZXZlbnRfZ2V0X2RydmRhdGEoZWRldik7Cj4gKwlpbnQgcmV0Owo+ICsKPiArCXJl dCA9IGNsa19wcmVwYXJlX2VuYWJsZShpbmZvLT5jbGspOwo+ICsJaWYgKHJldCkgewo+ICsJCWRl dl9lcnIoJmVkZXYtPmRldiwgImZhaWxlZCB0byBlbmFibGUgZGZpIGNsazogJWRcbiIsIHJldCk7 Cj4gKwkJcmV0dXJuIHJldDsKPiArCX0KPiArCj4gKwlyb2NrY2hpcF9kZmlfc3RhcnRfaGFyZHdh cmVfY291bnRlcihlZGV2KTsKPiArCXJldHVybiAwOwo+ICt9Cj4gKwo+ICtzdGF0aWMgaW50IHJv Y2tjaGlwX2RmaV9zZXRfZXZlbnQoc3RydWN0IGRldmZyZXFfZXZlbnRfZGV2ICplZGV2KQo+ICt7 Cj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArc3RhdGljIGludCByb2NrY2hpcF9kZmlfZ2V0X2V2 ZW50KHN0cnVjdCBkZXZmcmVxX2V2ZW50X2RldiAqZWRldiwKPiArCQkJCSAgc3RydWN0IGRldmZy ZXFfZXZlbnRfZGF0YSAqZWRhdGEpCj4gK3sKPiArCXN0cnVjdCByb2NrY2hpcF9kZmkgKmluZm8g PSBkZXZmcmVxX2V2ZW50X2dldF9kcnZkYXRhKGVkZXYpOwo+ICsJaW50IGJ1c2llcl9jaDsKPiAr Cj4gKwlidXNpZXJfY2ggPSByb2NrY2hpcF9kZmlfZ2V0X2J1c2llcl9jaChlZGV2KTsKPiArCj4g KwllZGF0YS0+bG9hZF9jb3VudCA9IGluZm8tPmNoX3VzYWdlW2J1c2llcl9jaF0uYWNjZXNzOwo+ ICsJZWRhdGEtPnRvdGFsX2NvdW50ID0gaW5mby0+Y2hfdXNhZ2VbYnVzaWVyX2NoXS50b3RhbDsK PiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ICsKPiArc3RhdGljIGNvbnN0IHN0cnVjdCBkZXZmcmVx X2V2ZW50X29wcyByb2NrY2hpcF9kZmlfb3BzID0gewo+ICsJLmRpc2FibGUgPSByb2NrY2hpcF9k ZmlfZGlzYWJsZSwKPiArCS5lbmFibGUgPSByb2NrY2hpcF9kZmlfZW5hYmxlLAo+ICsJLmdldF9l dmVudCA9IHJvY2tjaGlwX2RmaV9nZXRfZXZlbnQsCj4gKwkuc2V0X2V2ZW50ID0gcm9ja2NoaXBf ZGZpX3NldF9ldmVudCwKPiArfTsKPiArCj4gK3N0YXRpYyBjb25zdCBzdHJ1Y3Qgb2ZfZGV2aWNl X2lkIHJvY2tjaGlwX2RmaV9pZF9tYXRjaFtdID0gewo+ICsJeyAuY29tcGF0aWJsZSA9ICJyb2Nr Y2hpcCxyazMzOTktZGZpIiB9LAo+ICsJeyB9LAo+ICt9Owo+ICsKPiArc3RhdGljIGludCByb2Nr Y2hpcF9kZmlfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikKPiArewo+ICsJc3Ry dWN0IGRldmljZSAqZGV2ID0gJnBkZXYtPmRldjsKPiArCXN0cnVjdCByb2NrY2hpcF9kZmkgKmRh dGE7Cj4gKwlzdHJ1Y3QgcmVzb3VyY2UgKnJlczsKPiArCXN0cnVjdCBkZXZmcmVxX2V2ZW50X2Rl c2MgKmRlc2M7Cj4gKwlzdHJ1Y3QgZGV2aWNlX25vZGUgKm5wID0gcGRldi0+ZGV2Lm9mX25vZGUs ICpub2RlOwo+ICsKPiArCWRhdGEgPSBkZXZtX2t6YWxsb2MoZGV2LCBzaXplb2Yoc3RydWN0IHJv Y2tjaGlwX2RmaSksIEdGUF9LRVJORUwpOwo+ICsJaWYgKCFkYXRhKQo+ICsJCXJldHVybiAtRU5P TUVNOwo+ICsKPiArCXJlcyA9IHBsYXRmb3JtX2dldF9yZXNvdXJjZShwZGV2LCBJT1JFU09VUkNF X01FTSwgMCk7Cj4gKwlkYXRhLT5yZWdzID0gZGV2bV9pb3JlbWFwX3Jlc291cmNlKCZwZGV2LT5k ZXYsIHJlcyk7Cj4gKwlpZiAoSVNfRVJSKGRhdGEtPnJlZ3MpKQo+ICsJCXJldHVybiBQVFJfRVJS KGRhdGEtPnJlZ3MpOwo+ICsKPiArCWRhdGEtPmNsayA9IGRldm1fY2xrX2dldChkZXYsICJwY2xr X2Rkcl9tb24iKTsKPiArCWlmIChJU19FUlIoZGF0YS0+Y2xrKSkgewo+ICsJCWRldl9lcnIoZGV2 LCAiQ2Fubm90IGdldCB0aGUgY2xrIGRtY19jbGtcbiIpOwo+ICsJCXJldHVybiBQVFJfRVJSKGRh dGEtPmNsayk7Cj4gKwl9Owo+ICsKPiArCS8qIHRyeSB0byBmaW5kIHRoZSBvcHRpb25hbCByZWZl cmVuY2UgdG8gdGhlIHBtdSBzeXNjb24gKi8KPiArCW5vZGUgPSBvZl9wYXJzZV9waGFuZGxlKG5w LCAicm9ja2NoaXAscG11IiwgMCk7Cj4gKwlpZiAobm9kZSkgewo+ICsJCWRhdGEtPnJlZ21hcF9w bXUgPSBzeXNjb25fbm9kZV90b19yZWdtYXAobm9kZSk7Cj4gKwkJaWYgKElTX0VSUihkYXRhLT5y ZWdtYXBfcG11KSkKPiArCQkJcmV0dXJuIFBUUl9FUlIoZGF0YS0+cmVnbWFwX3BtdSk7Cj4gKwl9 Cj4gKwlkYXRhLT5kZXYgPSBkZXY7Cj4gKwo+ICsJZGVzYyA9IGRldm1fa3phbGxvYyhkZXYsIHNp emVvZigqZGVzYyksIEdGUF9LRVJORUwpOwo+ICsJaWYgKCFkZXNjKQo+ICsJCXJldHVybiAtRU5P TUVNOwo+ICsKPiArCWRlc2MtPm9wcyA9ICZyb2NrY2hpcF9kZmlfb3BzOwo+ICsJZGVzYy0+ZHJp dmVyX2RhdGEgPSBkYXRhOwo+ICsJZGVzYy0+bmFtZSA9IG5wLT5uYW1lOwo+ICsJZGF0YS0+ZGVz YyA9IGRlc2M7Cj4gKwo+ICsJZGF0YS0+ZWRldiA9IGRldm1fZGV2ZnJlcV9ldmVudF9hZGRfZWRl digmcGRldi0+ZGV2LCBkZXNjKTsKPiArCWlmIChJU19FUlIoZGF0YS0+ZWRldikpIHsKPiArCQlk ZXZfZXJyKCZwZGV2LT5kZXYsCj4gKwkJCSJmYWlsZWQgdG8gYWRkIGRldmZyZXEtZXZlbnQgZGV2 aWNlXG4iKTsKPiArCQlyZXR1cm4gUFRSX0VSUihkYXRhLT5lZGV2KTsKPiArCX0KPiArCj4gKwlw bGF0Zm9ybV9zZXRfZHJ2ZGF0YShwZGV2LCBkYXRhKTsKPiArCj4gKwlyZXR1cm4gMDsKPiArfQo+ ICsKPiArc3RhdGljIHN0cnVjdCBwbGF0Zm9ybV9kcml2ZXIgcm9ja2NoaXBfZGZpX2RyaXZlciA9 IHsKPiArCS5wcm9iZQk9IHJvY2tjaGlwX2RmaV9wcm9iZSwKPiArCS5kcml2ZXIgPSB7Cj4gKwkJ Lm5hbWUJPSAicm9ja2NoaXAtZGZpIiwKPiArCQkub2ZfbWF0Y2hfdGFibGUgPSByb2NrY2hpcF9k ZmlfaWRfbWF0Y2gsCj4gKwl9LAo+ICt9Owo+ICttb2R1bGVfcGxhdGZvcm1fZHJpdmVyKHJvY2tj aGlwX2RmaV9kcml2ZXIpOwo+ICsKPiArTU9EVUxFX0xJQ0VOU0UoIkdQTCB2MiIpOwo+ICtNT0RV TEVfQVVUSE9SKCJMaW4gSHVhbmcgPGhsQHJvY2stY2hpcHMuY29tPiIpOwo+ICtNT0RVTEVfREVT Q1JJUFRJT04oIlJvY2tjaGlwIGRmaSBkcml2ZXIiKTsKPiAKCgpfX19fX19fX19fX19fX19fX19f X19fX19fX19fX19fX19fX19fX19fX19fX19fXwpMaW51eC1yb2NrY2hpcCBtYWlsaW5nIGxpc3QK TGludXgtcm9ja2NoaXBAbGlzdHMuaW5mcmFkZWFkLm9yZwpodHRwOi8vbGlzdHMuaW5mcmFkZWFk Lm9yZy9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4LXJvY2tjaGlwCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: cw00.choi@samsung.com (Chanwoo Choi) Date: Mon, 01 Aug 2016 16:41:28 +0900 Subject: [PATCH v4 5/7] PM / devfreq: event: support rockchip dfi controller In-Reply-To: <1469779021-10426-6-git-send-email-hl@rock-chips.com> References: <1469779021-10426-1-git-send-email-hl@rock-chips.com> <1469779021-10426-6-git-send-email-hl@rock-chips.com> Message-ID: <579EFD28.5070404@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Lin, Because you remove the 'RFC' prefix on patch title, I think that you better to make the documentation as following: - Documentation/devicetree/bindings/devfreq/event/rockchip-dfi.txt Regards, Chanwoo Choi On 2016? 07? 29? 16:56, Lin Huang wrote: > on rk3399 platform, there is dfi conroller can monitor > ddr load, base on this result, we can do ddr freqency > scaling. > > Signed-off-by: Lin Huang > Acked-by: Chanwoo Choi > --- > Changes in v4: > - None > > Changes in v3: > - None > > Changes in v2: > - use clk_disable_unprepare and clk_enable_prepare > - remove clk_enable_prepare in probe > - remove rockchip_dfi_remove function > > Changes in v1: > - None > > drivers/devfreq/event/Kconfig | 7 + > drivers/devfreq/event/Makefile | 1 + > drivers/devfreq/event/rockchip-dfi.c | 253 +++++++++++++++++++++++++++++++++++ > 3 files changed, 261 insertions(+) > create mode 100644 drivers/devfreq/event/rockchip-dfi.c > > diff --git a/drivers/devfreq/event/Kconfig b/drivers/devfreq/event/Kconfig > index a11720a..ff9279f 100644 > --- a/drivers/devfreq/event/Kconfig > +++ b/drivers/devfreq/event/Kconfig > @@ -22,4 +22,11 @@ config DEVFREQ_EVENT_EXYNOS_PPMU > (Platform Performance Monitoring Unit) counters to estimate the > utilization of each module. > > +config DEVFREQ_EVENT_ROCKCHIP_DFI > + tristate "ROCKCHIP DFI DEVFREQ event Driver" > + depends on ARCH_ROCKCHIP > + help > + This add the devfreq-event driver for Rockchip SoC. It provides DFI > + (DDR Monitor Module) driver to count ddr load. > + > endif # PM_DEVFREQ_EVENT > diff --git a/drivers/devfreq/event/Makefile b/drivers/devfreq/event/Makefile > index be146ea..e3f88fc 100644 > --- a/drivers/devfreq/event/Makefile > +++ b/drivers/devfreq/event/Makefile > @@ -1,2 +1,3 @@ > # Exynos DEVFREQ Event Drivers > obj-$(CONFIG_DEVFREQ_EVENT_EXYNOS_PPMU) += exynos-ppmu.o > +obj-$(CONFIG_DEVFREQ_EVENT_ROCKCHIP_DFI) += rockchip-dfi.o > diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c > new file mode 100644 > index 0000000..96a0307 > --- /dev/null > +++ b/drivers/devfreq/event/rockchip-dfi.c > @@ -0,0 +1,253 @@ > +/* > + * Copyright (c) 2016, Fuzhou Rockchip Electronics Co., Ltd > + * Author: Lin Huang > + * > + * This program is free software; you can redistribute it and/or modify it > + * under the terms and conditions of the GNU General Public License, > + * version 2, as published by the Free Software Foundation. > + * > + * This program is distributed in the hope it will be useful, but WITHOUT > + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or > + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for > + * more details. > + */ > + > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > +#include > + > +#define RK3399_DMC_NUM_CH 2 > + > +/* DDRMON_CTRL */ > +#define DDRMON_CTRL 0x04 > +#define CLR_DDRMON_CTRL (0x1f0000 << 0) > +#define LPDDR4_EN (0x10001 << 4) > +#define HARDWARE_EN (0x10001 << 3) > +#define LPDDR3_EN (0x10001 << 2) > +#define SOFTWARE_EN (0x10001 << 1) > +#define TIME_CNT_EN (0x10001 << 0) > + > +#define DDRMON_CH0_COUNT_NUM 0x28 > +#define DDRMON_CH0_DFI_ACCESS_NUM 0x2c > +#define DDRMON_CH1_COUNT_NUM 0x3c > +#define DDRMON_CH1_DFI_ACCESS_NUM 0x40 > + > +/* pmu grf */ > +#define PMUGRF_OS_REG2 0x308 > +#define DDRTYPE_SHIFT 13 > +#define DDRTYPE_MASK 7 > + > +enum { > + DDR3 = 3, > + LPDDR3 = 6, > + LPDDR4 = 7, > + UNUSED = 0xFF > +}; > + > +struct dmc_usage { > + u32 access; > + u32 total; > +}; > + > +struct rockchip_dfi { > + struct devfreq_event_dev *edev; > + struct devfreq_event_desc *desc; > + struct dmc_usage ch_usage[RK3399_DMC_NUM_CH]; > + struct device *dev; > + void __iomem *regs; > + struct regmap *regmap_pmu; > + struct clk *clk; > +}; > + > +static void rockchip_dfi_start_hardware_counter(struct devfreq_event_dev *edev) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + void __iomem *dfi_regs = info->regs; > + u32 val; > + u32 ddr_type; > + > + /* get ddr type */ > + regmap_read(info->regmap_pmu, PMUGRF_OS_REG2, &val); > + ddr_type = (val >> DDRTYPE_SHIFT) & DDRTYPE_MASK; > + > + /* clear DDRMON_CTRL setting */ > + writel_relaxed(CLR_DDRMON_CTRL, dfi_regs + DDRMON_CTRL); > + > + /* set ddr type to dfi */ > + if (ddr_type == LPDDR3) > + writel_relaxed(LPDDR3_EN, dfi_regs + DDRMON_CTRL); > + else if (ddr_type == LPDDR4) > + writel_relaxed(LPDDR4_EN, dfi_regs + DDRMON_CTRL); > + > + /* enable count, use software mode */ > + writel_relaxed(SOFTWARE_EN, dfi_regs + DDRMON_CTRL); > +} > + > +static void rockchip_dfi_stop_hardware_counter(struct devfreq_event_dev *edev) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + void __iomem *dfi_regs = info->regs; > + u32 val; > + > + val = readl_relaxed(dfi_regs + DDRMON_CTRL); > + val &= ~SOFTWARE_EN; > + writel_relaxed(val, dfi_regs + DDRMON_CTRL); > +} > + > +static int rockchip_dfi_get_busier_ch(struct devfreq_event_dev *edev) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + u32 tmp, max = 0; > + u32 i, busier_ch = 0; > + void __iomem *dfi_regs = info->regs; > + > + rockchip_dfi_stop_hardware_counter(edev); > + > + /* Find out which channel is busier */ > + for (i = 0; i < RK3399_DMC_NUM_CH; i++) { > + info->ch_usage[i].access = readl_relaxed(dfi_regs + > + DDRMON_CH0_DFI_ACCESS_NUM + i * 20); > + info->ch_usage[i].total = readl_relaxed(dfi_regs + > + DDRMON_CH0_COUNT_NUM + i * 20); > + tmp = info->ch_usage[i].access; > + if (tmp > max) { > + busier_ch = i; > + max = tmp; > + } > + } > + rockchip_dfi_start_hardware_counter(edev); > + > + return busier_ch; > +} > + > +static int rockchip_dfi_disable(struct devfreq_event_dev *edev) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + > + rockchip_dfi_stop_hardware_counter(edev); > + clk_disable_unprepare(info->clk); > + > + return 0; > +} > + > +static int rockchip_dfi_enable(struct devfreq_event_dev *edev) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + int ret; > + > + ret = clk_prepare_enable(info->clk); > + if (ret) { > + dev_err(&edev->dev, "failed to enable dfi clk: %d\n", ret); > + return ret; > + } > + > + rockchip_dfi_start_hardware_counter(edev); > + return 0; > +} > + > +static int rockchip_dfi_set_event(struct devfreq_event_dev *edev) > +{ > + return 0; > +} > + > +static int rockchip_dfi_get_event(struct devfreq_event_dev *edev, > + struct devfreq_event_data *edata) > +{ > + struct rockchip_dfi *info = devfreq_event_get_drvdata(edev); > + int busier_ch; > + > + busier_ch = rockchip_dfi_get_busier_ch(edev); > + > + edata->load_count = info->ch_usage[busier_ch].access; > + edata->total_count = info->ch_usage[busier_ch].total; > + > + return 0; > +} > + > +static const struct devfreq_event_ops rockchip_dfi_ops = { > + .disable = rockchip_dfi_disable, > + .enable = rockchip_dfi_enable, > + .get_event = rockchip_dfi_get_event, > + .set_event = rockchip_dfi_set_event, > +}; > + > +static const struct of_device_id rockchip_dfi_id_match[] = { > + { .compatible = "rockchip,rk3399-dfi" }, > + { }, > +}; > + > +static int rockchip_dfi_probe(struct platform_device *pdev) > +{ > + struct device *dev = &pdev->dev; > + struct rockchip_dfi *data; > + struct resource *res; > + struct devfreq_event_desc *desc; > + struct device_node *np = pdev->dev.of_node, *node; > + > + data = devm_kzalloc(dev, sizeof(struct rockchip_dfi), GFP_KERNEL); > + if (!data) > + return -ENOMEM; > + > + res = platform_get_resource(pdev, IORESOURCE_MEM, 0); > + data->regs = devm_ioremap_resource(&pdev->dev, res); > + if (IS_ERR(data->regs)) > + return PTR_ERR(data->regs); > + > + data->clk = devm_clk_get(dev, "pclk_ddr_mon"); > + if (IS_ERR(data->clk)) { > + dev_err(dev, "Cannot get the clk dmc_clk\n"); > + return PTR_ERR(data->clk); > + }; > + > + /* try to find the optional reference to the pmu syscon */ > + node = of_parse_phandle(np, "rockchip,pmu", 0); > + if (node) { > + data->regmap_pmu = syscon_node_to_regmap(node); > + if (IS_ERR(data->regmap_pmu)) > + return PTR_ERR(data->regmap_pmu); > + } > + data->dev = dev; > + > + desc = devm_kzalloc(dev, sizeof(*desc), GFP_KERNEL); > + if (!desc) > + return -ENOMEM; > + > + desc->ops = &rockchip_dfi_ops; > + desc->driver_data = data; > + desc->name = np->name; > + data->desc = desc; > + > + data->edev = devm_devfreq_event_add_edev(&pdev->dev, desc); > + if (IS_ERR(data->edev)) { > + dev_err(&pdev->dev, > + "failed to add devfreq-event device\n"); > + return PTR_ERR(data->edev); > + } > + > + platform_set_drvdata(pdev, data); > + > + return 0; > +} > + > +static struct platform_driver rockchip_dfi_driver = { > + .probe = rockchip_dfi_probe, > + .driver = { > + .name = "rockchip-dfi", > + .of_match_table = rockchip_dfi_id_match, > + }, > +}; > +module_platform_driver(rockchip_dfi_driver); > + > +MODULE_LICENSE("GPL v2"); > +MODULE_AUTHOR("Lin Huang "); > +MODULE_DESCRIPTION("Rockchip dfi driver"); >