From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 7/7] x86emul: introduce SrcImm16 Date: Thu, 11 Aug 2016 06:07:23 -0600 Message-ID: <57AC869B02000078001050DE@prv-mh.provo.novell.com> References: <57AC83530200007800105078@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part92A4646B.1__=" Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bXolj-0005c6-4p for xen-devel@lists.xenproject.org; Thu, 11 Aug 2016 12:07:27 +0000 In-Reply-To: <57AC83530200007800105078@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel Cc: Andrew Cooper List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part92A4646B.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline ... and use it for RET, LRET, and ENTER processing to limit the amount of "manual" insn bytes fetching. Signed-off-by: Jan Beulich --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -39,6 +39,7 @@ #define SrcMem16 (4<<3) /* Memory operand (16-bit). */ #define SrcImm (5<<3) /* Immediate operand. */ #define SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */ +#define SrcImm16 (7<<3) /* 16-bit zero-extended immediate operand. */ #define SrcMask (7<<3) /* Generic ModRM decode. */ #define ModRM (1<<6) @@ -143,11 +144,11 @@ static uint8_t opcode_table[256] =3D { DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm= |Mov, /* 0xC0 - 0xC7 */ ByteOp|DstMem|SrcImm|ModRM, DstMem|SrcImmByte|ModRM, - ImplicitOps, ImplicitOps, + DstImplicit|SrcImm16, ImplicitOps, DstReg|SrcMem|ModRM|Mov, DstReg|SrcMem|ModRM|Mov, ByteOp|DstMem|SrcImm|ModRM|Mov, DstMem|SrcImm|ModRM|Mov, /* 0xC8 - 0xCF */ - ImplicitOps, ImplicitOps, ImplicitOps, ImplicitOps, + DstImplicit|SrcImm16, ImplicitOps, DstImplicit|SrcImm16, ImplicitOps, ImplicitOps, DstImplicit|SrcImmByte, ImplicitOps, ImplicitOps, /* 0xD0 - 0xD7 */ ByteOp|DstMem|SrcImplicit|ModRM, DstMem|SrcImplicit|ModRM, @@ -1994,6 +1995,11 @@ x86_emulate( case 4: src.val =3D insn_fetch_type(int32_t); break; } break; + case SrcImm16: + src.type =3D OP_IMM; + src.bytes =3D 2; + src.val =3D insn_fetch_type(uint16_t); + break; } =20 /* Decode and fetch the destination operand: register or memory. */ @@ -2786,16 +2792,14 @@ x86_emulate( break; =20 case 0xc2: /* ret imm16 (near) */ - case 0xc3: /* ret (near) */ { - int offset =3D (b =3D=3D 0xc2) ? insn_fetch_type(uint16_t) : 0; + case 0xc3: /* ret (near) */ op_bytes =3D ((op_bytes =3D=3D 4) && mode_64bit()) ? 8 : = op_bytes; - if ( (rc =3D read_ulong(x86_seg_ss, sp_post_inc(op_bytes + = offset), + if ( (rc =3D read_ulong(x86_seg_ss, sp_post_inc(op_bytes + = src.val), &dst.val, op_bytes, ctxt, ops)) !=3D 0 || (rc =3D ops->insn_fetch(x86_seg_cs, dst.val, NULL, 0, ctxt)) = ) goto done; _regs.eip =3D dst.val; break; - } =20 case 0xc4: /* les */ { unsigned long sel; @@ -2817,7 +2821,6 @@ x86_emulate( goto les; =20 case 0xc8: /* enter imm16,imm8 */ { - uint16_t size =3D insn_fetch_type(uint16_t); uint8_t depth =3D insn_fetch_type(uint8_t) & 31; int i; =20 @@ -2846,7 +2849,7 @@ x86_emulate( goto done; } =20 - sp_pre_dec(size); + sp_pre_dec(src.val); break; } =20 @@ -2874,17 +2877,15 @@ x86_emulate( break; =20 case 0xca: /* ret imm16 (far) */ - case 0xcb: /* ret (far) */ { - int offset =3D (b =3D=3D 0xca) ? insn_fetch_type(uint16_t) : 0; + case 0xcb: /* ret (far) */ if ( (rc =3D read_ulong(x86_seg_ss, sp_post_inc(op_bytes), &dst.val, op_bytes, ctxt, ops)) || - (rc =3D read_ulong(x86_seg_ss, sp_post_inc(op_bytes + = offset), + (rc =3D read_ulong(x86_seg_ss, sp_post_inc(op_bytes + = src.val), &src.val, op_bytes, ctxt, ops)) || (rc =3D load_seg(x86_seg_cs, src.val, 1, &cs, ctxt, ops)) || (rc =3D commit_far_branch(&cs, dst.val)) ) goto done; break; - } =20 case 0xcc: /* int3 */ src.val =3D EXC_BP; --=__Part92A4646B.1__= Content-Type: text/plain; name="x86emul-SrcImm16.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86emul-SrcImm16.patch" x86emul: introduce SrcImm16=0A=0A... and use it for RET, LRET, and ENTER = processing to limit the amount=0Aof "manual" insn bytes fetching.=0A=0ASign= ed-off-by: Jan Beulich =0A=0A--- a/xen/arch/x86/x86_emul= ate/x86_emulate.c=0A+++ b/xen/arch/x86/x86_emulate/x86_emulate.c=0A@@ = -39,6 +39,7 @@=0A #define SrcMem16 (4<<3) /* Memory operand (16-bit). = */=0A #define SrcImm (5<<3) /* Immediate operand. */=0A #define = SrcImmByte (6<<3) /* 8-bit sign-extended immediate operand. */=0A+#define = SrcImm16 (7<<3) /* 16-bit zero-extended immediate operand. */=0A = #define SrcMask (7<<3)=0A /* Generic ModRM decode. */=0A #define ModRM = (1<<6)=0A@@ -143,11 +144,11 @@ static uint8_t opcode_table[256] =3D = {=0A DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, DstReg|SrcImm|Mov, = DstReg|SrcImm|Mov,=0A /* 0xC0 - 0xC7 */=0A ByteOp|DstMem|SrcImm|Mod= RM, DstMem|SrcImmByte|ModRM,=0A- ImplicitOps, ImplicitOps,=0A+ = DstImplicit|SrcImm16, ImplicitOps,=0A DstReg|SrcMem|ModRM|Mov, = DstReg|SrcMem|ModRM|Mov,=0A ByteOp|DstMem|SrcImm|ModRM|Mov, DstMem|SrcI= mm|ModRM|Mov,=0A /* 0xC8 - 0xCF */=0A- ImplicitOps, ImplicitOps, = ImplicitOps, ImplicitOps,=0A+ DstImplicit|SrcImm16, ImplicitOps, = DstImplicit|SrcImm16, ImplicitOps,=0A ImplicitOps, DstImplicit|SrcImmBy= te, ImplicitOps, ImplicitOps,=0A /* 0xD0 - 0xD7 */=0A ByteOp|DstMem= |SrcImplicit|ModRM, DstMem|SrcImplicit|ModRM,=0A@@ -1994,6 +1995,11 @@ = x86_emulate(=0A case 4: src.val =3D insn_fetch_type(int32_t); = break;=0A }=0A break;=0A+ case SrcImm16:=0A+ = src.type =3D OP_IMM;=0A+ src.bytes =3D 2;=0A+ src.val =3D = insn_fetch_type(uint16_t);=0A+ break;=0A }=0A =0A /* Decode = and fetch the destination operand: register or memory. */=0A@@ -2786,16 = +2792,14 @@ x86_emulate(=0A break;=0A =0A case 0xc2: /* ret = imm16 (near) */=0A- case 0xc3: /* ret (near) */ {=0A- int offset = =3D (b =3D=3D 0xc2) ? insn_fetch_type(uint16_t) : 0;=0A+ case 0xc3: /* = ret (near) */=0A op_bytes =3D ((op_bytes =3D=3D 4) && mode_64bit())= ? 8 : op_bytes;=0A- if ( (rc =3D read_ulong(x86_seg_ss, sp_post_inc= (op_bytes + offset),=0A+ if ( (rc =3D read_ulong(x86_seg_ss, = sp_post_inc(op_bytes + src.val),=0A = &dst.val, op_bytes, ctxt, ops)) !=3D 0 ||=0A (rc =3D = ops->insn_fetch(x86_seg_cs, dst.val, NULL, 0, ctxt)) )=0A goto = done;=0A _regs.eip =3D dst.val;=0A break;=0A- }=0A =0A = case 0xc4: /* les */ {=0A unsigned long sel;=0A@@ -2817,7 = +2821,6 @@ x86_emulate(=0A goto les;=0A =0A case 0xc8: /* = enter imm16,imm8 */ {=0A- uint16_t size =3D insn_fetch_type(uint16_t= );=0A uint8_t depth =3D insn_fetch_type(uint8_t) & 31;=0A = int i;=0A =0A@@ -2846,7 +2849,7 @@ x86_emulate(=0A goto = done;=0A }=0A =0A- sp_pre_dec(size);=0A+ sp_pre_dec(s= rc.val);=0A break;=0A }=0A =0A@@ -2874,17 +2877,15 @@ = x86_emulate(=0A break;=0A =0A case 0xca: /* ret imm16 (far) = */=0A- case 0xcb: /* ret (far) */ {=0A- int offset =3D (b =3D=3D = 0xca) ? insn_fetch_type(uint16_t) : 0;=0A+ case 0xcb: /* ret (far) = */=0A if ( (rc =3D read_ulong(x86_seg_ss, sp_post_inc(op_bytes),=0A= &dst.val, op_bytes, ctxt, ops)) ||=0A- = (rc =3D read_ulong(x86_seg_ss, sp_post_inc(op_bytes + offset),=0A+ = (rc =3D read_ulong(x86_seg_ss, sp_post_inc(op_bytes + = src.val),=0A &src.val, op_bytes, ctxt, ops)) = ||=0A (rc =3D load_seg(x86_seg_cs, src.val, 1, &cs, ctxt, = ops)) ||=0A (rc =3D commit_far_branch(&cs, dst.val)) )=0A = goto done;=0A break;=0A- }=0A =0A case 0xcc: /* = int3 */=0A src.val =3D EXC_BP;=0A --=__Part92A4646B.1__= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwczovL2xpc3RzLnhlbi5v cmcveGVuLWRldmVsCg== --=__Part92A4646B.1__=--