From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 07/17] x86emul: move x86_execute() common epilogue code Date: Thu, 08 Sep 2016 07:13:24 -0600 Message-ID: <57D18014020000780010D187@prv-mh.provo.novell.com> References: <57D17C78020000780010D127@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part695FE2E4.1__=" Return-path: Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1bhz92-0000s8-7T for xen-devel@lists.xenproject.org; Thu, 08 Sep 2016 13:13:32 +0000 In-Reply-To: <57D17C78020000780010D127@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel Cc: Andrew Cooper List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part695FE2E4.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Only code movement, no functional change. Signed-off-by: Jan Beulich --- This is just to ease review of a later patch. --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -4111,56 +4111,7 @@ x86_emulate( default: goto cannot_emulate; } - - writeback: - switch ( dst.type ) - { - case OP_REG: - /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. = */ - switch ( dst.bytes ) - { - case 1: *(uint8_t *)dst.reg =3D (uint8_t)dst.val; break; - case 2: *(uint16_t *)dst.reg =3D (uint16_t)dst.val; break; - case 4: *dst.reg =3D (uint32_t)dst.val; break; /* 64b: zero-ext = */ - case 8: *dst.reg =3D dst.val; break; - } - break; - case OP_MEM: - if ( !(d & Mov) && (dst.orig_val =3D=3D dst.val) && - !ctxt->force_writeback ) - /* nothing to do */; - else if ( lock_prefix ) - rc =3D ops->cmpxchg( - dst.mem.seg, dst.mem.off, &dst.orig_val, - &dst.val, dst.bytes, ctxt); - else - rc =3D ops->write( - dst.mem.seg, dst.mem.off, &dst.val, dst.bytes, ctxt); - if ( rc !=3D 0 ) - goto done; - default: - break; - } - - no_writeback: - /* Inject #DB if single-step tracing was enabled at instruction = start. */ - if ( (ctxt->regs->eflags & EFLG_TF) && (rc =3D=3D X86EMUL_OKAY) && - (ops->inject_hw_exception !=3D NULL) ) - rc =3D ops->inject_hw_exception(EXC_DB, -1, ctxt) ? : X86EMUL_EXCE= PTION; - - /* Commit shadow register state. */ - _regs.eflags &=3D ~EFLG_RF; - - /* Zero the upper 32 bits of %rip if not in 64-bit mode. */ - if ( !mode_64bit() ) - _regs.eip =3D (uint32_t)_regs.eip; - - *ctxt->regs =3D _regs; - - done: - _put_fpu(); - put_stub(stub); - return rc; + goto writeback; =20 ext_0f_insn: switch ( b ) @@ -5134,7 +5085,56 @@ x86_emulate( default: goto cannot_emulate; } - goto writeback; + + writeback: + switch ( dst.type ) + { + case OP_REG: + /* The 4-byte case *is* correct: in 64-bit mode we zero-extend. = */ + switch ( dst.bytes ) + { + case 1: *(uint8_t *)dst.reg =3D (uint8_t)dst.val; break; + case 2: *(uint16_t *)dst.reg =3D (uint16_t)dst.val; break; + case 4: *dst.reg =3D (uint32_t)dst.val; break; /* 64b: zero-ext = */ + case 8: *dst.reg =3D dst.val; break; + } + break; + case OP_MEM: + if ( !(d & Mov) && (dst.orig_val =3D=3D dst.val) && + !ctxt->force_writeback ) + /* nothing to do */; + else if ( lock_prefix ) + rc =3D ops->cmpxchg( + dst.mem.seg, dst.mem.off, &dst.orig_val, + &dst.val, dst.bytes, ctxt); + else + rc =3D ops->write( + dst.mem.seg, dst.mem.off, &dst.val, dst.bytes, ctxt); + if ( rc !=3D 0 ) + goto done; + default: + break; + } + + no_writeback: + /* Inject #DB if single-step tracing was enabled at instruction = start. */ + if ( (ctxt->regs->eflags & EFLG_TF) && (rc =3D=3D X86EMUL_OKAY) && + (ops->inject_hw_exception !=3D NULL) ) + rc =3D ops->inject_hw_exception(EXC_DB, -1, ctxt) ? : X86EMUL_EXCE= PTION; + + /* Commit shadow register state. */ + _regs.eflags &=3D ~EFLG_RF; + + /* Zero the upper 32 bits of %rip if not in 64-bit mode. */ + if ( !mode_64bit() ) + _regs.eip =3D (uint32_t)_regs.eip; + + *ctxt->regs =3D _regs; + + done: + _put_fpu(); + put_stub(stub); + return rc; =20 cannot_emulate: _put_fpu(); --=__Part695FE2E4.1__= Content-Type: text/plain; name="x86emul-move-writeback.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86emul-move-writeback.patch" x86emul: move x86_execute() common epilogue code=0A=0AOnly code movement, = no functional change.=0A=0ASigned-off-by: Jan Beulich = =0A---=0AThis is just to ease review of a later patch.=0A=0A--- a/xen/arch/= x86/x86_emulate/x86_emulate.c=0A+++ b/xen/arch/x86/x86_emulate/x86_emulate.= c=0A@@ -4111,56 +4111,7 @@ x86_emulate(=0A default:=0A goto = cannot_emulate;=0A }=0A-=0A- writeback:=0A- switch ( dst.type )=0A- = {=0A- case OP_REG:=0A- /* The 4-byte case *is* correct: in = 64-bit mode we zero-extend. */=0A- switch ( dst.bytes )=0A- = {=0A- case 1: *(uint8_t *)dst.reg =3D (uint8_t)dst.val; break;=0A- = case 2: *(uint16_t *)dst.reg =3D (uint16_t)dst.val; break;=0A- = case 4: *dst.reg =3D (uint32_t)dst.val; break; /* 64b: zero-ext */=0A- = case 8: *dst.reg =3D dst.val; break;=0A- }=0A- = break;=0A- case OP_MEM:=0A- if ( !(d & Mov) && (dst.orig_val = =3D=3D dst.val) &&=0A- !ctxt->force_writeback )=0A- = /* nothing to do */;=0A- else if ( lock_prefix )=0A- rc = =3D ops->cmpxchg(=0A- dst.mem.seg, dst.mem.off, &dst.orig_va= l,=0A- &dst.val, dst.bytes, ctxt);=0A- else=0A- = rc =3D ops->write(=0A- dst.mem.seg, dst.mem.off, = &dst.val, dst.bytes, ctxt);=0A- if ( rc !=3D 0 )=0A- = goto done;=0A- default:=0A- break;=0A- }=0A-=0A- no_writeback:= =0A- /* Inject #DB if single-step tracing was enabled at instruction = start. */=0A- if ( (ctxt->regs->eflags & EFLG_TF) && (rc =3D=3D = X86EMUL_OKAY) &&=0A- (ops->inject_hw_exception !=3D NULL) )=0A- = rc =3D ops->inject_hw_exception(EXC_DB, -1, ctxt) ? : X86EMUL_EXCEPTION= ;=0A-=0A- /* Commit shadow register state. */=0A- _regs.eflags &=3D = ~EFLG_RF;=0A-=0A- /* Zero the upper 32 bits of %rip if not in 64-bit = mode. */=0A- if ( !mode_64bit() )=0A- _regs.eip =3D (uint32_t)_re= gs.eip;=0A-=0A- *ctxt->regs =3D _regs;=0A-=0A- done:=0A- _put_fpu();= =0A- put_stub(stub);=0A- return rc;=0A+ goto writeback;=0A =0A = ext_0f_insn:=0A switch ( b )=0A@@ -5134,7 +5085,56 @@ x86_emulate(=0A = default:=0A goto cannot_emulate;=0A }=0A- goto writeback;= =0A+=0A+ writeback:=0A+ switch ( dst.type )=0A+ {=0A+ case = OP_REG:=0A+ /* The 4-byte case *is* correct: in 64-bit mode we = zero-extend. */=0A+ switch ( dst.bytes )=0A+ {=0A+ = case 1: *(uint8_t *)dst.reg =3D (uint8_t)dst.val; break;=0A+ case = 2: *(uint16_t *)dst.reg =3D (uint16_t)dst.val; break;=0A+ case 4: = *dst.reg =3D (uint32_t)dst.val; break; /* 64b: zero-ext */=0A+ case = 8: *dst.reg =3D dst.val; break;=0A+ }=0A+ break;=0A+ case = OP_MEM:=0A+ if ( !(d & Mov) && (dst.orig_val =3D=3D dst.val) &&=0A+ = !ctxt->force_writeback )=0A+ /* nothing to do = */;=0A+ else if ( lock_prefix )=0A+ rc =3D ops->cmpxchg(= =0A+ dst.mem.seg, dst.mem.off, &dst.orig_val,=0A+ = &dst.val, dst.bytes, ctxt);=0A+ else=0A+ rc =3D = ops->write(=0A+ dst.mem.seg, dst.mem.off, &dst.val, = dst.bytes, ctxt);=0A+ if ( rc !=3D 0 )=0A+ goto = done;=0A+ default:=0A+ break;=0A+ }=0A+=0A+ no_writeback:=0A+ = /* Inject #DB if single-step tracing was enabled at instruction start. = */=0A+ if ( (ctxt->regs->eflags & EFLG_TF) && (rc =3D=3D X86EMUL_OKAY) = &&=0A+ (ops->inject_hw_exception !=3D NULL) )=0A+ rc =3D = ops->inject_hw_exception(EXC_DB, -1, ctxt) ? : X86EMUL_EXCEPTION;=0A+=0A+ = /* Commit shadow register state. */=0A+ _regs.eflags &=3D ~EFLG_RF;=0A= +=0A+ /* Zero the upper 32 bits of %rip if not in 64-bit mode. */=0A+ = if ( !mode_64bit() )=0A+ _regs.eip =3D (uint32_t)_regs.eip;=0A+=0A+= *ctxt->regs =3D _regs;=0A+=0A+ done:=0A+ _put_fpu();=0A+ = put_stub(stub);=0A+ return rc;=0A =0A cannot_emulate:=0A _put_fpu()= ;=0A --=__Part695FE2E4.1__= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwczovL2xpc3RzLnhlbi5v cmcveGVuLWRldmVsCg== --=__Part695FE2E4.1__=--