From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S936254AbcIWInX (ORCPT ); Fri, 23 Sep 2016 04:43:23 -0400 Received: from foss.arm.com ([217.140.101.70]:53870 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1754016AbcIWInV (ORCPT ); Fri, 23 Sep 2016 04:43:21 -0400 Subject: Re: linux-next: build failure after merge of the kvm-arm tree To: Christoffer Dall , Vladimir Murzin References: <20160923133116.707a8f07@canb.auug.org.au> Cc: Stephen Rothwell , linux-next@vger.kernel.org, linux-kernel@vger.kernel.org From: Marc Zyngier X-Enigmail-Draft-Status: N1110 Organization: ARM Ltd Message-ID: <57E4EB25.2020206@arm.com> Date: Fri, 23 Sep 2016 09:43:17 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Icedove/38.7.0 MIME-Version: 1.0 In-Reply-To: <20160923133116.707a8f07@canb.auug.org.au> Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 23/09/16 04:31, Stephen Rothwell wrote: > Hi all, > > After merging the kvm-arm tree, today's linux-next build (arm > multi_v7_defconfig) failed like this: > > tmp/cc9rCfjd.s: Assembler messages: > tmp/cc9rCfjd.s:310: Error: bad or missing co-processor number -- `mcr "mrc","mcr","p15, 0, r2, c12, c12, 3",u32' > scripts/Makefile.build:290: recipe for target 'drivers/irqchip/irq-gic-v3.o' failed > > Maybe caused by commit > > 4f2546384150 ("ARM: Move system register accessors to asm/cp15.h") > > I have used the kvm-arm tree from next-20160922 for today. Ouch. This comes from 91ef844 ("irqchip/gic-v3: Reset BPR during initialization") which has introduced a new accessor that doesn't get converted by Vladimir's patch. My own fault. This can be fixed-up by adding this to Vladimir's patch: diff --git a/arch/arm/include/asm/arch_gicv3.h b/arch/arm/include/asm/arch_gicv3.h index 996848e..809f3be 100644 --- a/arch/arm/include/asm/arch_gicv3.h +++ b/arch/arm/include/asm/arch_gicv3.h @@ -216,6 +216,15 @@ static inline void gic_write_sre(u32 val) isb(); } +static inline void gic_write_bpr1(u32 val) +{ +#ifndef __write_sysreg + asm volatile("mcr " __stringify(ICC_BPR1) : : "r" (val)); +#else + write_sysreg(val, ICC_BPR1); +#endif +} + /* * Even in 32bit systems that use LPAE, there is no guarantee that the I/O * interface provides true 64bit atomic accesses, so using strd/ldrd doesn't but that'll create a minor conflict. Another possibility is to put Vladimir's series on the backburner until tip/irq/core gets in, and bring it back at this time. I'd prefer the first solution, as it gives a bit more exposure to the code... Thanks, M. -- Jazz is not dead. It just smells funny...