* [PATCH v3 00/21] Add driver nodes for MT8195 SoC
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Add driver nodes for MT8195 SoC.
Patchset 17 "arm64: dts: mt8195: Add adsp node and adsp mailbox" depends on
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git/commit/?id=009b21f392759ca7be91bc4be9d9534f6cee2878
---
v2 -> v3:
- fix dsp node name
- add descriptions for iommu interrupts
- limit the levels of power domain nodes
- update maintainer list of power controller yaml
- support naming power controller node with unit address
- add SoC specific compatible string to scpsys yaml
v1 -> v2:
- add new dt-bindings: mfd/mediatek,scpsys.yaml
- update compatible string for mt81xx scpsys nodes
- apply comments for yaml files: iommu, smi-common, and power-controller
- apply comments for dts nodes: power domain, vdosys0.
- apply comments for commit message of watchdog, i2c, and smi-common.
- add review-by tags
---
Jason-JH.Lin (2):
arm64: dts: mt8195: Add gce node
arm64: dts: mt8195: Add display node for vdosys0
Tinghan Shen (15):
dt-bindings: iommu: mediatek: Increase max interrupt number
dt-bindings: memory: mediatek: Update condition for mt8195 smi node
dt-bindings: power: mediatek: Refine multiple level power domain nodes
dt-bindings: power: mediatek: Support naming power controller node
with unit address
dt-bindings: power: mediatek: Update maintainer list
dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
dt-bindings: power: mediatek: Update example in dt-bindings
arm64: dts: mediatek: Update mt81xx scpsys node to align with
dt-bindings
arm64: dts: mt8195: Disable watchdog external reset signal
arm64: dts: mt8195: Add vdosys and vppsys clock nodes
arm64: dts: mt8195: Add power domains controller
arm64: dts: mt8195: Add spmi node
arm64: dts: mt8195: Add scp node
arm64: dts: mt8195: Add audio related nodes
arm64: dts: mt8195: Add iommu and smi nodes
Trevor Wu (1):
arm64: dts: mt8195: Specify audio reset controller
Tzung-Bi Shih (1):
arm64: dts: mt8195: Disable I2C0 node
YC Hung (1):
arm64: dts: mt8195: Add adsp node and adsp mailbox nodes
YT Lee (1):
arm64: dts: mt8195: Add cpufreq node
.../bindings/iommu/mediatek,iommu.yaml | 18 +-
.../mediatek,smi-common.yaml | 11 +-
.../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 ++
.../power/mediatek,power-controller.yaml | 137 +--
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1056 ++++++++++++++++-
9 files changed, 1174 insertions(+), 128 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
--
2.18.0
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH v3 00/21] Add driver nodes for MT8195 SoC
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Add driver nodes for MT8195 SoC.
Patchset 17 "arm64: dts: mt8195: Add adsp node and adsp mailbox" depends on
https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git/commit/?id=009b21f392759ca7be91bc4be9d9534f6cee2878
---
v2 -> v3:
- fix dsp node name
- add descriptions for iommu interrupts
- limit the levels of power domain nodes
- update maintainer list of power controller yaml
- support naming power controller node with unit address
- add SoC specific compatible string to scpsys yaml
v1 -> v2:
- add new dt-bindings: mfd/mediatek,scpsys.yaml
- update compatible string for mt81xx scpsys nodes
- apply comments for yaml files: iommu, smi-common, and power-controller
- apply comments for dts nodes: power domain, vdosys0.
- apply comments for commit message of watchdog, i2c, and smi-common.
- add review-by tags
---
Jason-JH.Lin (2):
arm64: dts: mt8195: Add gce node
arm64: dts: mt8195: Add display node for vdosys0
Tinghan Shen (15):
dt-bindings: iommu: mediatek: Increase max interrupt number
dt-bindings: memory: mediatek: Update condition for mt8195 smi node
dt-bindings: power: mediatek: Refine multiple level power domain nodes
dt-bindings: power: mediatek: Support naming power controller node
with unit address
dt-bindings: power: mediatek: Update maintainer list
dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
dt-bindings: power: mediatek: Update example in dt-bindings
arm64: dts: mediatek: Update mt81xx scpsys node to align with
dt-bindings
arm64: dts: mt8195: Disable watchdog external reset signal
arm64: dts: mt8195: Add vdosys and vppsys clock nodes
arm64: dts: mt8195: Add power domains controller
arm64: dts: mt8195: Add spmi node
arm64: dts: mt8195: Add scp node
arm64: dts: mt8195: Add audio related nodes
arm64: dts: mt8195: Add iommu and smi nodes
Trevor Wu (1):
arm64: dts: mt8195: Specify audio reset controller
Tzung-Bi Shih (1):
arm64: dts: mt8195: Disable I2C0 node
YC Hung (1):
arm64: dts: mt8195: Add adsp node and adsp mailbox nodes
YT Lee (1):
arm64: dts: mt8195: Add cpufreq node
.../bindings/iommu/mediatek,iommu.yaml | 18 +-
.../mediatek,smi-common.yaml | 11 +-
.../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 ++
.../power/mediatek,power-controller.yaml | 137 +--
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +-
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1056 ++++++++++++++++-
9 files changed, 1174 insertions(+), 128 deletions(-)
create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* [PATCH v3 01/21] dt-bindings: iommu: mediatek: Increase max interrupt number
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
mt8195 infra iommu uses 5 interrupts.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../bindings/iommu/mediatek,iommu.yaml | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index fee0241b5098..5afe2a004533 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -91,7 +91,8 @@ properties:
maxItems: 1
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 5
clocks:
items:
@@ -191,9 +192,24 @@ allOf:
const: mediatek,mt8195-iommu-infra
then:
+ properties:
+ interrupts:
+ maxItems: 1
+
required:
- mediatek,larbs
+ else:
+ properties:
+ interrupts:
+ description: The IOMMU has 5 banks. Each bank has its own interrupt.
+ items:
+ - description: The interrupt for IOMMU bank0
+ - description: The interrupt for IOMMU bank1
+ - description: The interrupt for IOMMU bank2
+ - description: The interrupt for IOMMU bank3
+ - description: The interrupt for IOMMU bank4
+
additionalProperties: false
examples:
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 01/21] dt-bindings: iommu: mediatek: Increase max interrupt number
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
mt8195 infra iommu uses 5 interrupts.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../bindings/iommu/mediatek,iommu.yaml | 18 +++++++++++++++++-
1 file changed, 17 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
index fee0241b5098..5afe2a004533 100644
--- a/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
+++ b/Documentation/devicetree/bindings/iommu/mediatek,iommu.yaml
@@ -91,7 +91,8 @@ properties:
maxItems: 1
interrupts:
- maxItems: 1
+ minItems: 1
+ maxItems: 5
clocks:
items:
@@ -191,9 +192,24 @@ allOf:
const: mediatek,mt8195-iommu-infra
then:
+ properties:
+ interrupts:
+ maxItems: 1
+
required:
- mediatek,larbs
+ else:
+ properties:
+ interrupts:
+ description: The IOMMU has 5 banks. Each bank has its own interrupt.
+ items:
+ - description: The interrupt for IOMMU bank0
+ - description: The interrupt for IOMMU bank1
+ - description: The interrupt for IOMMU bank2
+ - description: The interrupt for IOMMU bank3
+ - description: The interrupt for IOMMU bank4
+
additionalProperties: false
examples:
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 02/21] dt-bindings: memory: mediatek: Update condition for mt8195 smi node
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
The max clock items for the dts node with compatible
'mediatek,mt8195-smi-sub-common' should be 3.
However, the dtbs_check of such node will get following message,
arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: smi@14010000: clock-names: ['apb', 'smi', 'gals0'] is too long
From schema: Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
It's because the 'mediatek,mt8195-smi-sub-common' compatible incorrectly
matches the 'else' conditions for gen2 HW without gals.
Rewrite the 'else' condition to specifically identify the compatibles
that utilizing gen2 HW without gals.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../memory-controllers/mediatek,smi-common.yaml | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
index 71bc5cefb49c..4f5dd0a20109 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -144,7 +144,16 @@ allOf:
- const: gals0
- const: gals1
- else: # for gen2 HW that don't have gals
+ - if: # for gen2 HW that don't have gals
+ properties:
+ compatible:
+ enum:
+ - mediatek,mt2712-smi-common
+ - mediatek,mt6795-smi-common
+ - mediatek,mt8167-smi-common
+ - mediatek,mt8173-smi-common
+
+ then:
properties:
clocks:
minItems: 2
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 02/21] dt-bindings: memory: mediatek: Update condition for mt8195 smi node
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
The max clock items for the dts node with compatible
'mediatek,mt8195-smi-sub-common' should be 3.
However, the dtbs_check of such node will get following message,
arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: smi@14010000: clock-names: ['apb', 'smi', 'gals0'] is too long
From schema: Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
It's because the 'mediatek,mt8195-smi-sub-common' compatible incorrectly
matches the 'else' conditions for gen2 HW without gals.
Rewrite the 'else' condition to specifically identify the compatibles
that utilizing gen2 HW without gals.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
.../memory-controllers/mediatek,smi-common.yaml | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
index 71bc5cefb49c..4f5dd0a20109 100644
--- a/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
+++ b/Documentation/devicetree/bindings/memory-controllers/mediatek,smi-common.yaml
@@ -144,7 +144,16 @@ allOf:
- const: gals0
- const: gals1
- else: # for gen2 HW that don't have gals
+ - if: # for gen2 HW that don't have gals
+ properties:
+ compatible:
+ enum:
+ - mediatek,mt2712-smi-common
+ - mediatek,mt6795-smi-common
+ - mediatek,mt8167-smi-common
+ - mediatek,mt8173-smi-common
+
+ then:
properties:
clocks:
minItems: 2
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 03/21] dt-bindings: power: mediatek: Refine multiple level power domain nodes
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Extract duplicated properties and support more levels of power
domain nodes.
This change fix following error when do dtbs_check,
arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: power-controller: power-domain@15:power-domain@16:power-domain@18: 'power-domain@19', 'power-domain@20', 'power-domain@21' do not match any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../power/mediatek,power-controller.yaml | 131 +++---------------
1 file changed, 17 insertions(+), 114 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index b448101fac43..321802c95308 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -42,6 +42,23 @@ properties:
patternProperties:
"^power-domain@[0-9a-f]+$":
+ $ref: "#/$defs/power-domain-node"
+ patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ $ref: "#/$defs/power-domain-node"
+ patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ $ref: "#/$defs/power-domain-node"
+ patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ $ref: "#/$defs/power-domain-node"
+ unevaluatedProperties: false
+ unevaluatedProperties: false
+ unevaluatedProperties: false
+ unevaluatedProperties: false
+
+$defs:
+ power-domain-node:
type: object
description: |
Represents the power domains within the power controller node as documented
@@ -100,123 +117,9 @@ patternProperties:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the SMI register range.
- patternProperties:
- "^power-domain@[0-9a-f]+$":
- type: object
- description: |
- Represents a power domain child within a power domain parent node.
-
- properties:
-
- '#power-domain-cells':
- description:
- Must be 0 for nodes representing a single PM domain and 1 for nodes
- providing multiple PM domains.
-
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
-
- reg:
- maxItems: 1
-
- clocks:
- description: |
- A number of phandles to clocks that need to be enabled during domain
- power-up sequencing.
-
- clock-names:
- description: |
- List of names of clocks, in order to match the power-up sequencing
- for each power domain we need to group the clocks by name. BASIC
- clocks need to be enabled before enabling the corresponding power
- domain, and should not have a '-' in their name (i.e mm, mfg, venc).
- SUSBYS clocks need to be enabled before releasing the bus protection,
- and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
-
- In order to follow properly the power-up sequencing, the clocks must
- be specified by order, adding first the BASIC clocks followed by the
- SUSBSYS clocks.
-
- domain-supply:
- description: domain regulator supply.
-
- mediatek,infracfg:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: phandle to the device containing the INFRACFG register range.
-
- mediatek,smi:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: phandle to the device containing the SMI register range.
-
- patternProperties:
- "^power-domain@[0-9a-f]+$":
- type: object
- description: |
- Represents a power domain child within a power domain parent node.
-
- properties:
-
- '#power-domain-cells':
- description:
- Must be 0 for nodes representing a single PM domain and 1 for nodes
- providing multiple PM domains.
-
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
-
- reg:
- maxItems: 1
-
- clocks:
- description: |
- A number of phandles to clocks that need to be enabled during domain
- power-up sequencing.
-
- clock-names:
- description: |
- List of names of clocks, in order to match the power-up sequencing
- for each power domain we need to group the clocks by name. BASIC
- clocks need to be enabled before enabling the corresponding power
- domain, and should not have a '-' in their name (i.e mm, mfg, venc).
- SUSBYS clocks need to be enabled before releasing the bus protection,
- and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
-
- In order to follow properly the power-up sequencing, the clocks must
- be specified by order, adding first the BASIC clocks followed by the
- SUSBSYS clocks.
-
- domain-supply:
- description: domain regulator supply.
-
- mediatek,infracfg:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: phandle to the device containing the INFRACFG register range.
-
- mediatek,smi:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: phandle to the device containing the SMI register range.
-
- required:
- - reg
-
- additionalProperties: false
-
- required:
- - reg
-
- additionalProperties: false
-
required:
- reg
- additionalProperties: false
-
required:
- compatible
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 03/21] dt-bindings: power: mediatek: Refine multiple level power domain nodes
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Extract duplicated properties and support more levels of power
domain nodes.
This change fix following error when do dtbs_check,
arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: power-controller: power-domain@15:power-domain@16:power-domain@18: 'power-domain@19', 'power-domain@20', 'power-domain@21' do not match any of the regexes: 'pinctrl-[0-9]+'
From schema: Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../power/mediatek,power-controller.yaml | 131 +++---------------
1 file changed, 17 insertions(+), 114 deletions(-)
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index b448101fac43..321802c95308 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -42,6 +42,23 @@ properties:
patternProperties:
"^power-domain@[0-9a-f]+$":
+ $ref: "#/$defs/power-domain-node"
+ patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ $ref: "#/$defs/power-domain-node"
+ patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ $ref: "#/$defs/power-domain-node"
+ patternProperties:
+ "^power-domain@[0-9a-f]+$":
+ $ref: "#/$defs/power-domain-node"
+ unevaluatedProperties: false
+ unevaluatedProperties: false
+ unevaluatedProperties: false
+ unevaluatedProperties: false
+
+$defs:
+ power-domain-node:
type: object
description: |
Represents the power domains within the power controller node as documented
@@ -100,123 +117,9 @@ patternProperties:
$ref: /schemas/types.yaml#/definitions/phandle
description: phandle to the device containing the SMI register range.
- patternProperties:
- "^power-domain@[0-9a-f]+$":
- type: object
- description: |
- Represents a power domain child within a power domain parent node.
-
- properties:
-
- '#power-domain-cells':
- description:
- Must be 0 for nodes representing a single PM domain and 1 for nodes
- providing multiple PM domains.
-
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
-
- reg:
- maxItems: 1
-
- clocks:
- description: |
- A number of phandles to clocks that need to be enabled during domain
- power-up sequencing.
-
- clock-names:
- description: |
- List of names of clocks, in order to match the power-up sequencing
- for each power domain we need to group the clocks by name. BASIC
- clocks need to be enabled before enabling the corresponding power
- domain, and should not have a '-' in their name (i.e mm, mfg, venc).
- SUSBYS clocks need to be enabled before releasing the bus protection,
- and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
-
- In order to follow properly the power-up sequencing, the clocks must
- be specified by order, adding first the BASIC clocks followed by the
- SUSBSYS clocks.
-
- domain-supply:
- description: domain regulator supply.
-
- mediatek,infracfg:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: phandle to the device containing the INFRACFG register range.
-
- mediatek,smi:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: phandle to the device containing the SMI register range.
-
- patternProperties:
- "^power-domain@[0-9a-f]+$":
- type: object
- description: |
- Represents a power domain child within a power domain parent node.
-
- properties:
-
- '#power-domain-cells':
- description:
- Must be 0 for nodes representing a single PM domain and 1 for nodes
- providing multiple PM domains.
-
- '#address-cells':
- const: 1
-
- '#size-cells':
- const: 0
-
- reg:
- maxItems: 1
-
- clocks:
- description: |
- A number of phandles to clocks that need to be enabled during domain
- power-up sequencing.
-
- clock-names:
- description: |
- List of names of clocks, in order to match the power-up sequencing
- for each power domain we need to group the clocks by name. BASIC
- clocks need to be enabled before enabling the corresponding power
- domain, and should not have a '-' in their name (i.e mm, mfg, venc).
- SUSBYS clocks need to be enabled before releasing the bus protection,
- and should contain a '-' in their name (i.e mm-0, isp-0, cam-0).
-
- In order to follow properly the power-up sequencing, the clocks must
- be specified by order, adding first the BASIC clocks followed by the
- SUSBSYS clocks.
-
- domain-supply:
- description: domain regulator supply.
-
- mediatek,infracfg:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: phandle to the device containing the INFRACFG register range.
-
- mediatek,smi:
- $ref: /schemas/types.yaml#/definitions/phandle
- description: phandle to the device containing the SMI register range.
-
- required:
- - reg
-
- additionalProperties: false
-
- required:
- - reg
-
- additionalProperties: false
-
required:
- reg
- additionalProperties: false
-
required:
- compatible
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 04/21] dt-bindings: power: mediatek: Support naming power controller node with unit address
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Support naming power controller node with unit address, also compatible
with node names without unit address.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../devicetree/bindings/power/mediatek,power-controller.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 321802c95308..2d6afc090947 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -19,7 +19,7 @@ description: |
properties:
$nodename:
- const: power-controller
+ pattern: '^power-controller(@[0-9a-f]+)?$'
compatible:
enum:
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 04/21] dt-bindings: power: mediatek: Support naming power controller node with unit address
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Support naming power controller node with unit address, also compatible
with node names without unit address.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../devicetree/bindings/power/mediatek,power-controller.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 321802c95308..2d6afc090947 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -19,7 +19,7 @@ description: |
properties:
$nodename:
- const: power-controller
+ pattern: '^power-controller(@[0-9a-f]+)?$'
compatible:
enum:
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 05/21] dt-bindings: power: mediatek: Update maintainer list
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Update the maintainer list of power controller binding.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../devicetree/bindings/power/mediatek,power-controller.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 2d6afc090947..03b7f6aa591d 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Power Domains Controller
maintainers:
- - Weiyi Lu <weiyi.lu@mediatek.com>
+ - MandyJH Liu <mandyjh.liu@mediatek.com>
- Matthias Brugger <mbrugger@suse.com>
description: |
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 05/21] dt-bindings: power: mediatek: Update maintainer list
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Update the maintainer list of power controller binding.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../devicetree/bindings/power/mediatek,power-controller.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 2d6afc090947..03b7f6aa591d 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -7,7 +7,7 @@ $schema: http://devicetree.org/meta-schemas/core.yaml#
title: Mediatek Power Domains Controller
maintainers:
- - Weiyi Lu <weiyi.lu@mediatek.com>
+ - MandyJH Liu <mandyjh.liu@mediatek.com>
- Matthias Brugger <mbrugger@suse.com>
description: |
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. Add the bindings for it.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
new file mode 100644
index 000000000000..4117a6dbc19c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Control Processor System
+
+maintainers:
+ - MandyJH Liu <mandyjh.liu@mediatek.com>
+
+description:
+ MediaTek System Control Processor System (SCPSYS) has several
+ power management tasks. The tasks include MTCMOS power
+ domain control, thermal measurement, DVFS, etc.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8167-scpsys
+ - mediatek,mt8173-scpsys
+ - mediatek,mt8183-scpsys
+ - mediatek,mt8192-scpsys
+ - mediatek,mt8195-scpsys
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^power-controller(@[0-9a-f]+)?$":
+ $ref: /schemas/power/mediatek,power-controller.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/power/mt8195-power.h>
+
+ syscon@10006000 {
+ compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
+ reg = <0x10006000 0x100>;
+
+ spm: power-controller {
+ compatible = "mediatek,mt8195-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* sample of power domain nodes */
+ power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
The System Control Processor System (SCPSYS) has several power
management related tasks in the system. Add the bindings for it.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 +++++++++++++++++++
1 file changed, 68 insertions(+)
create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
new file mode 100644
index 000000000000..4117a6dbc19c
--- /dev/null
+++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
@@ -0,0 +1,68 @@
+# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek System Control Processor System
+
+maintainers:
+ - MandyJH Liu <mandyjh.liu@mediatek.com>
+
+description:
+ MediaTek System Control Processor System (SCPSYS) has several
+ power management tasks. The tasks include MTCMOS power
+ domain control, thermal measurement, DVFS, etc.
+
+properties:
+ compatible:
+ items:
+ - enum:
+ - mediatek,mt8167-scpsys
+ - mediatek,mt8173-scpsys
+ - mediatek,mt8183-scpsys
+ - mediatek,mt8192-scpsys
+ - mediatek,mt8195-scpsys
+ - const: syscon
+ - const: simple-mfd
+
+ reg:
+ maxItems: 1
+
+patternProperties:
+ "^power-controller(@[0-9a-f]+)?$":
+ $ref: /schemas/power/mediatek,power-controller.yaml#
+
+required:
+ - compatible
+ - reg
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8195-clk.h>
+ #include <dt-bindings/power/mt8195-power.h>
+
+ syscon@10006000 {
+ compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
+ reg = <0x10006000 0x100>;
+
+ spm: power-controller {
+ compatible = "mediatek,mt8195-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* sample of power domain nodes */
+ power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 07/21] dt-bindings: power: mediatek: Update example in dt-bindings
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Update the scpsys node compatible string to align with the
scpsys node bindings.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../devicetree/bindings/power/mediatek,power-controller.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 03b7f6aa591d..605ec7ab5f63 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -135,7 +135,7 @@ examples:
#size-cells = <2>;
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
spm: power-controller {
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 07/21] dt-bindings: power: mediatek: Update example in dt-bindings
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Update the scpsys node compatible string to align with the
scpsys node bindings.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
.../devicetree/bindings/power/mediatek,power-controller.yaml | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
index 03b7f6aa591d..605ec7ab5f63 100644
--- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
+++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
@@ -135,7 +135,7 @@ examples:
#size-cells = <2>;
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
spm: power-controller {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 08/21] arm64: dts: mediatek: Update mt81xx scpsys node to align with dt-bindings
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Update scpsys nodes using simple-mfd in mt81xx SoC devicetree
to align with the bindings.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 3 +--
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 3 +--
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +--
4 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 54655f2feb04..fbe1a1128cc6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -36,9 +36,8 @@
};
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
spm: power-controller {
compatible = "mediatek,mt8167-power-controller";
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 6d9513c1f5bf..b4d48f8b7eeb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -444,9 +444,8 @@
};
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 9d32871973a2..28d84f0054ee 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -761,9 +761,8 @@
};
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index cbae5a5ee4a0..8cd5906fe3a8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -306,9 +306,8 @@
};
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 08/21] arm64: dts: mediatek: Update mt81xx scpsys node to align with dt-bindings
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Update scpsys nodes using simple-mfd in mt81xx SoC devicetree
to align with the bindings.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
arch/arm64/boot/dts/mediatek/mt8167.dtsi | 3 +--
arch/arm64/boot/dts/mediatek/mt8173.dtsi | 3 +--
arch/arm64/boot/dts/mediatek/mt8183.dtsi | 3 +--
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 3 +--
4 files changed, 4 insertions(+), 8 deletions(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8167.dtsi b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
index 54655f2feb04..fbe1a1128cc6 100644
--- a/arch/arm64/boot/dts/mediatek/mt8167.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8167.dtsi
@@ -36,9 +36,8 @@
};
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8167-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
spm: power-controller {
compatible = "mediatek,mt8167-power-controller";
diff --git a/arch/arm64/boot/dts/mediatek/mt8173.dtsi b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
index 6d9513c1f5bf..b4d48f8b7eeb 100644
--- a/arch/arm64/boot/dts/mediatek/mt8173.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8173.dtsi
@@ -444,9 +444,8 @@
};
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8173-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
diff --git a/arch/arm64/boot/dts/mediatek/mt8183.dtsi b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
index 9d32871973a2..28d84f0054ee 100644
--- a/arch/arm64/boot/dts/mediatek/mt8183.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8183.dtsi
@@ -761,9 +761,8 @@
};
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8183-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index cbae5a5ee4a0..8cd5906fe3a8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -306,9 +306,8 @@
};
scpsys: syscon@10006000 {
- compatible = "syscon", "simple-mfd";
+ compatible = "mediatek,mt8192-scpsys", "syscon", "simple-mfd";
reg = <0 0x10006000 0 0x1000>;
- #power-domain-cells = <1>;
/* System Power Manager */
spm: power-controller {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 09/21] arm64: dts: mt8195: Disable watchdog external reset signal
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Fengquan Chen
Disable the external output reset signal of watchdog reset to avoid losing
the reset reason stored in the watchdog registers.
Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 066c14989708..436687ba826f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -327,6 +327,7 @@
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8195-wdt",
"mediatek,mt6589-wdt";
+ mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
};
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 09/21] arm64: dts: mt8195: Disable watchdog external reset signal
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Fengquan Chen
Disable the external output reset signal of watchdog reset to avoid losing
the reset reason stored in the watchdog registers.
Signed-off-by: Fengquan Chen <fengquan.chen@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1 +
1 file changed, 1 insertion(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 066c14989708..436687ba826f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -327,6 +327,7 @@
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8195-wdt",
"mediatek,mt6589-wdt";
+ mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 10/21] arm64: dts: mt8195: Disable I2C0 node
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Tzung-Bi Shih
From: Tzung-Bi Shih <tzungbi@chromium.org>
The I2C0 node should not be enabled globally, as usage is board
dependent; disable it in dtsi.
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 436687ba826f..8032b839dfe8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -829,7 +829,7 @@
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
- status = "okay";
+ status = "disabled";
};
i2c1: i2c@11e01000 {
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 10/21] arm64: dts: mt8195: Disable I2C0 node
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Tzung-Bi Shih
From: Tzung-Bi Shih <tzungbi@chromium.org>
The I2C0 node should not be enabled globally, as usage is board
dependent; disable it in dtsi.
Signed-off-by: Tzung-Bi Shih <tzungbi@chromium.org>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 436687ba826f..8032b839dfe8 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -829,7 +829,7 @@
clock-names = "main", "dma";
#address-cells = <1>;
#size-cells = <0>;
- status = "okay";
+ status = "disabled";
};
i2c1: i2c@11e01000 {
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 11/21] arm64: dts: mt8195: Add cpufreq node
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group, YT Lee
From: YT Lee <yt.lee@mediatek.corp-partner.google.com>
Add cpufreq node for mt8195.
Signed-off-by: YT Lee <yt.lee@mediatek.corp-partner.google.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8032b839dfe8..900aaa16f862 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -26,6 +26,7 @@
compatible = "arm,cortex-a55";
reg = <0x000>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -38,6 +39,7 @@
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -50,6 +52,7 @@
compatible = "arm,cortex-a55";
reg = <0x200>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -62,6 +65,7 @@
compatible = "arm,cortex-a55";
reg = <0x300>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -74,6 +78,7 @@
compatible = "arm,cortex-a78";
reg = <0x400>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -86,6 +91,7 @@
compatible = "arm,cortex-a78";
reg = <0x500>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -98,6 +104,7 @@
compatible = "arm,cortex-a78";
reg = <0x600>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -110,6 +117,7 @@
compatible = "arm,cortex-a78";
reg = <0x700>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -231,6 +239,12 @@
clock-output-names = "clk32k";
};
+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 11/21] arm64: dts: mt8195: Add cpufreq node
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group, YT Lee
From: YT Lee <yt.lee@mediatek.corp-partner.google.com>
Add cpufreq node for mt8195.
Signed-off-by: YT Lee <yt.lee@mediatek.corp-partner.google.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 14 ++++++++++++++
1 file changed, 14 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8032b839dfe8..900aaa16f862 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -26,6 +26,7 @@
compatible = "arm,cortex-a55";
reg = <0x000>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -38,6 +39,7 @@
compatible = "arm,cortex-a55";
reg = <0x100>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -50,6 +52,7 @@
compatible = "arm,cortex-a55";
reg = <0x200>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -62,6 +65,7 @@
compatible = "arm,cortex-a55";
reg = <0x300>;
enable-method = "psci";
+ performance-domains = <&performance 0>;
clock-frequency = <1701000000>;
capacity-dmips-mhz = <578>;
cpu-idle-states = <&cpu_off_l &cluster_off_l>;
@@ -74,6 +78,7 @@
compatible = "arm,cortex-a78";
reg = <0x400>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -86,6 +91,7 @@
compatible = "arm,cortex-a78";
reg = <0x500>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -98,6 +104,7 @@
compatible = "arm,cortex-a78";
reg = <0x600>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -110,6 +117,7 @@
compatible = "arm,cortex-a78";
reg = <0x700>;
enable-method = "psci";
+ performance-domains = <&performance 1>;
clock-frequency = <2171000000>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_off_b &cluster_off_b>;
@@ -231,6 +239,12 @@
clock-output-names = "clk32k";
};
+ performance: performance-controller@11bc10 {
+ compatible = "mediatek,cpufreq-hw";
+ reg = <0 0x0011bc10 0 0x120>, <0 0x0011bd30 0 0x120>;
+ #performance-domain-cells = <1>;
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupt-parent = <&gic>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 12/21] arm64: dts: mt8195: Add vdosys and vppsys clock nodes
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Add display clock nodes.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 900aaa16f862..8d59a7da3271 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -983,6 +983,12 @@
#clock-cells = <1>;
};
+ vppsys0: clock-controller@14000000 {
+ compatible = "mediatek,mt8195-vppsys0";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0 0x14e00000 0 0x1000>;
@@ -1001,6 +1007,12 @@
#clock-cells = <1>;
};
+ vppsys1: clock-controller@14f00000 {
+ compatible = "mediatek,mt8195-vppsys1";
+ reg = <0 0x14f00000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x15000000 0 0x1000>;
@@ -1108,5 +1120,17 @@
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ vdosys0: syscon@1c01a000 {
+ compatible = "mediatek,mt8195-mmsys", "syscon";
+ reg = <0 0x1c01a000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdosys1: syscon@1c100000 {
+ compatible = "mediatek,mt8195-mmsys", "syscon";
+ reg = <0 0x1c100000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 12/21] arm64: dts: mt8195: Add vdosys and vppsys clock nodes
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Add display clock nodes.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 24 ++++++++++++++++++++++++
1 file changed, 24 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 900aaa16f862..8d59a7da3271 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -983,6 +983,12 @@
#clock-cells = <1>;
};
+ vppsys0: clock-controller@14000000 {
+ compatible = "mediatek,mt8195-vppsys0";
+ reg = <0 0x14000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0 0x14e00000 0 0x1000>;
@@ -1001,6 +1007,12 @@
#clock-cells = <1>;
};
+ vppsys1: clock-controller@14f00000 {
+ compatible = "mediatek,mt8195-vppsys1";
+ reg = <0 0x14f00000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x15000000 0 0x1000>;
@@ -1108,5 +1120,17 @@
reg = <0 0x1b000000 0 0x1000>;
#clock-cells = <1>;
};
+
+ vdosys0: syscon@1c01a000 {
+ compatible = "mediatek,mt8195-mmsys", "syscon";
+ reg = <0 0x1c01a000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdosys1: syscon@1c100000 {
+ compatible = "mediatek,mt8195-mmsys", "syscon";
+ reg = <0 0x1c100000 0 0x1000>;
+ #clock-cells = <1>;
+ };
};
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 13/21] arm64: dts: mt8195: Add power domains controller
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group, Weiyi Lu
Add power domains controller node for mt8195.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 326 +++++++++++++++++++++++
1 file changed, 326 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8d59a7da3271..7e77aecb1296 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/power/mt8195-power.h>
/ {
compatible = "mediatek,mt8195";
@@ -338,6 +339,331 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8195-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
+ reg = <MT8195_POWER_DOMAIN_MFG0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_MFG1 {
+ reg = <MT8195_POWER_DOMAIN_MFG1>;
+ clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
+ clock-names = "mfg";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_MFG2 {
+ reg = <MT8195_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG3 {
+ reg = <MT8195_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG4 {
+ reg = <MT8195_POWER_DOMAIN_MFG4>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG5 {
+ reg = <MT8195_POWER_DOMAIN_MFG5>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG6 {
+ reg = <MT8195_POWER_DOMAIN_MFG6>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
+ reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
+ clocks = <&topckgen CLK_TOP_VPP>,
+ <&topckgen CLK_TOP_CAM>,
+ <&topckgen CLK_TOP_CCU>,
+ <&topckgen CLK_TOP_IMG>,
+ <&topckgen CLK_TOP_VENC>,
+ <&topckgen CLK_TOP_VDEC>,
+ <&topckgen CLK_TOP_WPE_VPP>,
+ <&topckgen CLK_TOP_CFG_VPP0>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
+ <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
+ <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_INFRA>,
+ <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
+ <&vppsys0 CLK_VPP0_SMI_REORDER>,
+ <&vppsys0 CLK_VPP0_SMI_IOMMU>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
+ <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
+ <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
+ "vppsys4", "vppsys5", "vppsys6", "vppsys7",
+ "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
+ "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
+ "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
+ "vppsys0-12", "vppsys0-13", "vppsys0-14",
+ "vppsys0-15", "vppsys0-16", "vppsys0-17",
+ "vppsys0-18";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_VDEC1 {
+ reg = <MT8195_POWER_DOMAIN_VDEC1>;
+ clocks = <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "vdec1-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
+ reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
+ reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&topckgen CLK_TOP_CFG_VDO0>,
+ <&vdosys0 CLK_VDO0_SMI_GALS>,
+ <&vdosys0 CLK_VDO0_SMI_COMMON>,
+ <&vdosys0 CLK_VDO0_SMI_EMI>,
+ <&vdosys0 CLK_VDO0_SMI_IOMMU>,
+ <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vdosys0 CLK_VDO0_SMI_RSI>;
+ clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
+ "vdosys0-2", "vdosys0-3",
+ "vdosys0-4", "vdosys0-5";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
+ reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
+ clocks = <&topckgen CLK_TOP_CFG_VPP1>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
+ clock-names = "vppsys1", "vppsys1-0",
+ "vppsys1-1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_WPESYS {
+ reg = <MT8195_POWER_DOMAIN_WPESYS>;
+ clocks = <&wpesys CLK_WPE_SMI_LARB7>,
+ <&wpesys CLK_WPE_SMI_LARB8>,
+ <&wpesys CLK_WPE_SMI_LARB7_P>,
+ <&wpesys CLK_WPE_SMI_LARB8_P>;
+ clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
+ "wepsys-3";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDEC0 {
+ reg = <MT8195_POWER_DOMAIN_VDEC0>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "vdec0-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDEC2 {
+ reg = <MT8195_POWER_DOMAIN_VDEC2>;
+ clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
+ clock-names = "vdec2-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VENC {
+ reg = <MT8195_POWER_DOMAIN_VENC>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
+ reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&topckgen CLK_TOP_CFG_VDO1>,
+ <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_SMI_LARB3>,
+ <&vdosys1 CLK_VDO1_GALS>;
+ clock-names = "vdosys1", "vdosys1-0",
+ "vdosys1-1", "vdosys1-2";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_DP_TX {
+ reg = <MT8195_POWER_DOMAIN_DP_TX>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_EPD_TX {
+ reg = <MT8195_POWER_DOMAIN_EPD_TX>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
+ reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
+ clocks = <&topckgen CLK_TOP_HDMI_APB>;
+ clock-names = "hdmi_tx";
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_IMG {
+ reg = <MT8195_POWER_DOMAIN_IMG>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "img-0", "img-1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_DIP {
+ reg = <MT8195_POWER_DOMAIN_DIP>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_IPE {
+ reg = <MT8195_POWER_DOMAIN_IPE>;
+ clocks = <&topckgen CLK_TOP_IPE>,
+ <&imgsys CLK_IMG_IPE>,
+ <&ipesys CLK_IPE_SMI_LARB12>;
+ clock-names = "ipe", "ipe-0", "ipe-1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CAM {
+ reg = <MT8195_POWER_DOMAIN_CAM>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>,
+ <&camsys CLK_CAM_CAM2MM1_GALS>,
+ <&camsys CLK_CAM_CAM2SYS_GALS>;
+ clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
+ "cam-4";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
+ reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
+ reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
+ reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
+ reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
+ reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
+ reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
+ clocks = <&topckgen CLK_TOP_SENINF>,
+ <&topckgen CLK_TOP_SENINF2>;
+ clock-names = "csi_rx_top", "csi_rx_top1";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_ETHER {
+ reg = <MT8195_POWER_DOMAIN_ETHER>;
+ clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
+ clock-names = "ether";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_ADSP {
+ reg = <MT8195_POWER_DOMAIN_ADSP>;
+ clocks = <&topckgen CLK_TOP_ADSP>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
+ clock-names = "adsp", "adsp1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_AUDIO {
+ reg = <MT8195_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_A1SYS_HP>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
+ clock-names = "audio", "audio1", "audio2",
+ "audio3";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8195-wdt",
"mediatek,mt6589-wdt";
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 13/21] arm64: dts: mt8195: Add power domains controller
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group, Weiyi Lu
Add power domains controller node for mt8195.
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 326 +++++++++++++++++++++++
1 file changed, 326 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 8d59a7da3271..7e77aecb1296 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -10,6 +10,7 @@
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/power/mt8195-power.h>
/ {
compatible = "mediatek,mt8195";
@@ -338,6 +339,331 @@
#interrupt-cells = <2>;
};
+ scpsys: syscon@10006000 {
+ compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
+ reg = <0 0x10006000 0 0x1000>;
+
+ /* System Power Manager */
+ spm: power-controller {
+ compatible = "mediatek,mt8195-power-controller";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ /* power domain of the SoC */
+ mfg0: power-domain@MT8195_POWER_DOMAIN_MFG0 {
+ reg = <MT8195_POWER_DOMAIN_MFG0>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_MFG1 {
+ reg = <MT8195_POWER_DOMAIN_MFG1>;
+ clocks = <&apmixedsys CLK_APMIXED_MFGPLL>;
+ clock-names = "mfg";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_MFG2 {
+ reg = <MT8195_POWER_DOMAIN_MFG2>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG3 {
+ reg = <MT8195_POWER_DOMAIN_MFG3>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG4 {
+ reg = <MT8195_POWER_DOMAIN_MFG4>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG5 {
+ reg = <MT8195_POWER_DOMAIN_MFG5>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_MFG6 {
+ reg = <MT8195_POWER_DOMAIN_MFG6>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VPPSYS0 {
+ reg = <MT8195_POWER_DOMAIN_VPPSYS0>;
+ clocks = <&topckgen CLK_TOP_VPP>,
+ <&topckgen CLK_TOP_CAM>,
+ <&topckgen CLK_TOP_CCU>,
+ <&topckgen CLK_TOP_IMG>,
+ <&topckgen CLK_TOP_VENC>,
+ <&topckgen CLK_TOP_VDEC>,
+ <&topckgen CLK_TOP_WPE_VPP>,
+ <&topckgen CLK_TOP_CFG_VPP0>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>,
+ <&vppsys0 CLK_VPP0_GALS_VENCSYS>,
+ <&vppsys0 CLK_VPP0_GALS_VENCSYS_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_INFRA>,
+ <&vppsys0 CLK_VPP0_GALS_CAMSYS>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>,
+ <&vppsys0 CLK_VPP0_SMI_REORDER>,
+ <&vppsys0 CLK_VPP0_SMI_IOMMU>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>,
+ <&vppsys0 CLK_VPP0_GALS_EMI0_EMI1>,
+ <&vppsys0 CLK_VPP0_SMI_SUB_COMMON_REORDER>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "vppsys", "vppsys1", "vppsys2", "vppsys3",
+ "vppsys4", "vppsys5", "vppsys6", "vppsys7",
+ "vppsys0-0", "vppsys0-1", "vppsys0-2", "vppsys0-3",
+ "vppsys0-4", "vppsys0-5", "vppsys0-6", "vppsys0-7",
+ "vppsys0-8", "vppsys0-9", "vppsys0-10", "vppsys0-11",
+ "vppsys0-12", "vppsys0-13", "vppsys0-14",
+ "vppsys0-15", "vppsys0-16", "vppsys0-17",
+ "vppsys0-18";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_VDEC1 {
+ reg = <MT8195_POWER_DOMAIN_VDEC1>;
+ clocks = <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "vdec1-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VENC_CORE1 {
+ reg = <MT8195_POWER_DOMAIN_VENC_CORE1>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDOSYS0 {
+ reg = <MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&topckgen CLK_TOP_CFG_VDO0>,
+ <&vdosys0 CLK_VDO0_SMI_GALS>,
+ <&vdosys0 CLK_VDO0_SMI_COMMON>,
+ <&vdosys0 CLK_VDO0_SMI_EMI>,
+ <&vdosys0 CLK_VDO0_SMI_IOMMU>,
+ <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vdosys0 CLK_VDO0_SMI_RSI>;
+ clock-names = "vdosys0", "vdosys0-0", "vdosys0-1",
+ "vdosys0-2", "vdosys0-3",
+ "vdosys0-4", "vdosys0-5";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_VPPSYS1 {
+ reg = <MT8195_POWER_DOMAIN_VPPSYS1>;
+ clocks = <&topckgen CLK_TOP_CFG_VPP1>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_LARB>;
+ clock-names = "vppsys1", "vppsys1-0",
+ "vppsys1-1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_WPESYS {
+ reg = <MT8195_POWER_DOMAIN_WPESYS>;
+ clocks = <&wpesys CLK_WPE_SMI_LARB7>,
+ <&wpesys CLK_WPE_SMI_LARB8>,
+ <&wpesys CLK_WPE_SMI_LARB7_P>,
+ <&wpesys CLK_WPE_SMI_LARB8_P>;
+ clock-names = "wepsys-0", "wepsys-1", "wepsys-2",
+ "wepsys-3";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDEC0 {
+ reg = <MT8195_POWER_DOMAIN_VDEC0>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "vdec0-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDEC2 {
+ reg = <MT8195_POWER_DOMAIN_VDEC2>;
+ clocks = <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
+ clock-names = "vdec2-0";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VENC {
+ reg = <MT8195_POWER_DOMAIN_VENC>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_VDOSYS1 {
+ reg = <MT8195_POWER_DOMAIN_VDOSYS1>;
+ clocks = <&topckgen CLK_TOP_CFG_VDO1>,
+ <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_SMI_LARB3>,
+ <&vdosys1 CLK_VDO1_GALS>;
+ clock-names = "vdosys1", "vdosys1-0",
+ "vdosys1-1", "vdosys1-2";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_DP_TX {
+ reg = <MT8195_POWER_DOMAIN_DP_TX>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_EPD_TX {
+ reg = <MT8195_POWER_DOMAIN_EPD_TX>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_HDMI_TX {
+ reg = <MT8195_POWER_DOMAIN_HDMI_TX>;
+ clocks = <&topckgen CLK_TOP_HDMI_APB>;
+ clock-names = "hdmi_tx";
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_IMG {
+ reg = <MT8195_POWER_DOMAIN_IMG>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "img-0", "img-1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_DIP {
+ reg = <MT8195_POWER_DOMAIN_DIP>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_IPE {
+ reg = <MT8195_POWER_DOMAIN_IPE>;
+ clocks = <&topckgen CLK_TOP_IPE>,
+ <&imgsys CLK_IMG_IPE>,
+ <&ipesys CLK_IPE_SMI_LARB12>;
+ clock-names = "ipe", "ipe-0", "ipe-1";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CAM {
+ reg = <MT8195_POWER_DOMAIN_CAM>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>,
+ <&camsys CLK_CAM_CAM2MM1_GALS>,
+ <&camsys CLK_CAM_CAM2SYS_GALS>;
+ clock-names = "cam-0", "cam-1", "cam-2", "cam-3",
+ "cam-4";
+ mediatek,infracfg = <&infracfg_ao>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_CAM_RAWA {
+ reg = <MT8195_POWER_DOMAIN_CAM_RAWA>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CAM_RAWB {
+ reg = <MT8195_POWER_DOMAIN_CAM_RAWB>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CAM_MRAW {
+ reg = <MT8195_POWER_DOMAIN_CAM_MRAW>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P0 {
+ reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P0>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_PCIE_MAC_P1 {
+ reg = <MT8195_POWER_DOMAIN_PCIE_MAC_P1>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
+ reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_CSI_RX_TOP {
+ reg = <MT8195_POWER_DOMAIN_CSI_RX_TOP>;
+ clocks = <&topckgen CLK_TOP_SENINF>,
+ <&topckgen CLK_TOP_SENINF2>;
+ clock-names = "csi_rx_top", "csi_rx_top1";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_ETHER {
+ reg = <MT8195_POWER_DOMAIN_ETHER>;
+ clocks = <&pericfg_ao CLK_PERI_AO_ETHERNET_MAC>;
+ clock-names = "ether";
+ #power-domain-cells = <0>;
+ };
+
+ power-domain@MT8195_POWER_DOMAIN_ADSP {
+ reg = <MT8195_POWER_DOMAIN_ADSP>;
+ clocks = <&topckgen CLK_TOP_ADSP>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>;
+ clock-names = "adsp", "adsp1";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <1>;
+
+ power-domain@MT8195_POWER_DOMAIN_AUDIO {
+ reg = <MT8195_POWER_DOMAIN_AUDIO>;
+ clocks = <&topckgen CLK_TOP_A1SYS_HP>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>;
+ clock-names = "audio", "audio1", "audio2",
+ "audio3";
+ mediatek,infracfg = <&infracfg_ao>;
+ #power-domain-cells = <0>;
+ };
+ };
+ };
+ };
+
watchdog: watchdog@10007000 {
compatible = "mediatek,mt8195-wdt",
"mediatek,mt6589-wdt";
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 14/21] arm64: dts: mt8195: Add spmi node
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Henry Chen
Add spmi node to mt8195.
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 07affd663768..16a854031431 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -697,6 +697,21 @@
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
};
+ spmi: spmi@10027000 {
+ compatible = "mediatek,mt8195-spmi";
+ reg = <0 0x10027000 0 0x000e00>,
+ <0 0x10029000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_M_MST>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 14/21] arm64: dts: mt8195: Add spmi node
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Henry Chen
Add spmi node to mt8195.
Signed-off-by: Henry Chen <henryc.chen@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 15 +++++++++++++++
1 file changed, 15 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 07affd663768..16a854031431 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -697,6 +697,21 @@
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
};
+ spmi: spmi@10027000 {
+ compatible = "mediatek,mt8195-spmi";
+ reg = <0 0x10027000 0 0x000e00>,
+ <0 0x10029000 0 0x000100>;
+ reg-names = "pmif", "spmimst";
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>,
+ <&topckgen CLK_TOP_SPMI_M_MST>;
+ clock-names = "pmif_sys_ck",
+ "pmif_tmr_ck",
+ "spmimst_clk_mux";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 15/21] arm64: dts: mt8195: Add scp node
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Add scp node for mt8195.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 16a854031431..f35540637197 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -712,6 +712,16 @@
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
};
+ scp: scp@10500000 {
+ compatible = "mediatek,mt8195-scp";
+ reg = <0 0x10500000 0 0x100000>,
+ <0 0x10720000 0 0xe0000>,
+ <0 0x10700000 0 0x8000>;
+ reg-names = "sram", "cfg", "l1tcm";
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 15/21] arm64: dts: mt8195: Add scp node
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Add scp node for mt8195.
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 16a854031431..f35540637197 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -712,6 +712,16 @@
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
};
+ scp: scp@10500000 {
+ compatible = "mediatek,mt8195-scp";
+ reg = <0 0x10500000 0 0x100000>,
+ <0 0x10720000 0 0xe0000>,
+ <0 0x10700000 0 0x8000>;
+ reg-names = "sram", "cfg", "l1tcm";
+ interrupts = <GIC_SPI 462 IRQ_TYPE_LEVEL_HIGH 0>;
+ status = "disabled";
+ };
+
scp_adsp: clock-controller@10720000 {
compatible = "mediatek,mt8195-scp_adsp";
reg = <0 0x10720000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 16/21] arm64: dts: mt8195: Add audio related nodes
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Trevor Wu
Add audio related nodes for mt8195.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index f35540637197..635d8cf9fe19 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -226,6 +226,17 @@
<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
+ dmic_codec: dmic-codec {
+ compatible = "dmic-codec";
+ num-channels = <2>;
+ wakeup-delay-ms = <50>;
+ };
+
+ sound: mt8195-sound {
+ mediatek,platform = <&afe>;
+ status = "disabled";
+ };
+
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -728,6 +739,53 @@
#clock-cells = <1>;
};
+ afe: mt8195-afe-pcm@10890000 {
+ compatible = "mediatek,mt8195-audio";
+ reg = <0 0x10890000 0 0x10000>;
+ mediatek,topckgen = <&topckgen>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>,
+ <&apmixedsys CLK_APMIXED_APLL1>,
+ <&apmixedsys CLK_APMIXED_APLL2>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_A1SYS_HP>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&topckgen CLK_TOP_AUDIO_H>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&topckgen CLK_TOP_DPTX_MCK>,
+ <&topckgen CLK_TOP_I2SO1_MCK>,
+ <&topckgen CLK_TOP_I2SO2_MCK>,
+ <&topckgen CLK_TOP_I2SI1_MCK>,
+ <&topckgen CLK_TOP_I2SI2_MCK>,
+ <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
+ <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
+ clock-names = "clk26m",
+ "apll1_ck",
+ "apll2_ck",
+ "apll12_div0",
+ "apll12_div1",
+ "apll12_div2",
+ "apll12_div3",
+ "apll12_div9",
+ "a1sys_hp_sel",
+ "aud_intbus_sel",
+ "audio_h_sel",
+ "audio_local_bus_sel",
+ "dptx_m_sel",
+ "i2so1_m_sel",
+ "i2so2_m_sel",
+ "i2si1_m_sel",
+ "i2si2_m_sel",
+ "infra_ao_audio_26m_b",
+ "scp_adsp_audiodsp";
+ status = "disabled";
+ };
+
uart0: serial@11001100 {
compatible = "mediatek,mt8195-uart",
"mediatek,mt6577-uart";
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 16/21] arm64: dts: mt8195: Add audio related nodes
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Trevor Wu
Add audio related nodes for mt8195.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 58 ++++++++++++++++++++++++
1 file changed, 58 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index f35540637197..635d8cf9fe19 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -226,6 +226,17 @@
<&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
};
+ dmic_codec: dmic-codec {
+ compatible = "dmic-codec";
+ num-channels = <2>;
+ wakeup-delay-ms = <50>;
+ };
+
+ sound: mt8195-sound {
+ mediatek,platform = <&afe>;
+ status = "disabled";
+ };
+
clk26m: oscillator-26m {
compatible = "fixed-clock";
#clock-cells = <0>;
@@ -728,6 +739,53 @@
#clock-cells = <1>;
};
+ afe: mt8195-afe-pcm@10890000 {
+ compatible = "mediatek,mt8195-audio";
+ reg = <0 0x10890000 0 0x10000>;
+ mediatek,topckgen = <&topckgen>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
+ interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>,
+ <&apmixedsys CLK_APMIXED_APLL1>,
+ <&apmixedsys CLK_APMIXED_APLL2>,
+ <&topckgen CLK_TOP_APLL12_DIV0>,
+ <&topckgen CLK_TOP_APLL12_DIV1>,
+ <&topckgen CLK_TOP_APLL12_DIV2>,
+ <&topckgen CLK_TOP_APLL12_DIV3>,
+ <&topckgen CLK_TOP_APLL12_DIV9>,
+ <&topckgen CLK_TOP_A1SYS_HP>,
+ <&topckgen CLK_TOP_AUD_INTBUS>,
+ <&topckgen CLK_TOP_AUDIO_H>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&topckgen CLK_TOP_DPTX_MCK>,
+ <&topckgen CLK_TOP_I2SO1_MCK>,
+ <&topckgen CLK_TOP_I2SO2_MCK>,
+ <&topckgen CLK_TOP_I2SI1_MCK>,
+ <&topckgen CLK_TOP_I2SI2_MCK>,
+ <&infracfg_ao CLK_INFRA_AO_AUDIO_26M_B>,
+ <&scp_adsp CLK_SCP_ADSP_AUDIODSP>;
+ clock-names = "clk26m",
+ "apll1_ck",
+ "apll2_ck",
+ "apll12_div0",
+ "apll12_div1",
+ "apll12_div2",
+ "apll12_div3",
+ "apll12_div9",
+ "a1sys_hp_sel",
+ "aud_intbus_sel",
+ "audio_h_sel",
+ "audio_local_bus_sel",
+ "dptx_m_sel",
+ "i2so1_m_sel",
+ "i2so2_m_sel",
+ "i2si1_m_sel",
+ "i2si2_m_sel",
+ "infra_ao_audio_26m_b",
+ "scp_adsp_audiodsp";
+ status = "disabled";
+ };
+
uart0: serial@11001100 {
compatible = "mediatek,mt8195-uart",
"mediatek,mt6577-uart";
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 17/21] arm64: dts: mt8195: Add adsp node and adsp mailbox nodes
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group, YC Hung,
Allen-KH Cheng
From: YC Hung <yc.hung@mediatek.corp-partner.google.com>
Add adsp node and adsp mailbox nodes for mt8195.
Signed-off-by: YC Hung <yc.hung@mediatek.corp-partner.google.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 37 ++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 635d8cf9fe19..54d8d26dd2e4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -739,6 +739,43 @@
#clock-cells = <1>;
};
+ adsp: dsp@10803000 {
+ compatible = "mediatek,mt8195-dsp";
+ reg = <0 0x10803000 0 0x1000>,
+ <0 0x10840000 0 0x40000>;
+ reg-names = "cfg", "sram";
+ clocks = <&topckgen CLK_TOP_ADSP>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&topckgen CLK_TOP_MAINPLL_D7_D2>,
+ <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
+ <&topckgen CLK_TOP_AUDIO_H>;
+ clock-names = "adsp_sel",
+ "clk26m_ck",
+ "audio_local_bus",
+ "mainpll_d7_d2",
+ "scp_adsp_audiodsp",
+ "audio_h";
+ power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
+ mbox-names = "rx", "tx";
+ mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+ status = "disabled";
+ };
+
+ adsp_mailbox0: mailbox@10816000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10816000 0 0x1000>;
+ interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ adsp_mailbox1: mailbox@10817000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10817000 0 0x1000>;
+ interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
afe: mt8195-afe-pcm@10890000 {
compatible = "mediatek,mt8195-audio";
reg = <0 0x10890000 0 0x10000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 17/21] arm64: dts: mt8195: Add adsp node and adsp mailbox nodes
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group, YC Hung,
Allen-KH Cheng
From: YC Hung <yc.hung@mediatek.corp-partner.google.com>
Add adsp node and adsp mailbox nodes for mt8195.
Signed-off-by: YC Hung <yc.hung@mediatek.corp-partner.google.com>
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.corp-partner.google.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 37 ++++++++++++++++++++++++
1 file changed, 37 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 635d8cf9fe19..54d8d26dd2e4 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -739,6 +739,43 @@
#clock-cells = <1>;
};
+ adsp: dsp@10803000 {
+ compatible = "mediatek,mt8195-dsp";
+ reg = <0 0x10803000 0 0x1000>,
+ <0 0x10840000 0 0x40000>;
+ reg-names = "cfg", "sram";
+ clocks = <&topckgen CLK_TOP_ADSP>,
+ <&clk26m>,
+ <&topckgen CLK_TOP_AUDIO_LOCAL_BUS>,
+ <&topckgen CLK_TOP_MAINPLL_D7_D2>,
+ <&scp_adsp CLK_SCP_ADSP_AUDIODSP>,
+ <&topckgen CLK_TOP_AUDIO_H>;
+ clock-names = "adsp_sel",
+ "clk26m_ck",
+ "audio_local_bus",
+ "mainpll_d7_d2",
+ "scp_adsp_audiodsp",
+ "audio_h";
+ power-domains = <&spm MT8195_POWER_DOMAIN_ADSP>;
+ mbox-names = "rx", "tx";
+ mboxes = <&adsp_mailbox0>, <&adsp_mailbox1>;
+ status = "disabled";
+ };
+
+ adsp_mailbox0: mailbox@10816000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10816000 0 0x1000>;
+ interrupts = <GIC_SPI 702 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ adsp_mailbox1: mailbox@10817000 {
+ compatible = "mediatek,mt8195-adsp-mbox";
+ #mbox-cells = <0>;
+ reg = <0 0x10817000 0 0x1000>;
+ interrupts = <GIC_SPI 703 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
afe: mt8195-afe-pcm@10890000 {
compatible = "mediatek,mt8195-audio";
reg = <0 0x10890000 0 0x10000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 18/21] arm64: dts: mt8195: Specify audio reset controller
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Trevor Wu
From: Trevor Wu <trevor.wu@mediatek.com>
Specify audio reset controller for audio hardware resetting.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 54d8d26dd2e4..08e6ae5ce40f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -680,6 +680,7 @@
"mediatek,mt6589-wdt";
mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
};
apmixedsys: syscon@1000c000 {
@@ -782,6 +783,8 @@
mediatek,topckgen = <&topckgen>;
power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 14>;
+ reset-names = "audiosys";
clocks = <&clk26m>,
<&apmixedsys CLK_APMIXED_APLL1>,
<&apmixedsys CLK_APMIXED_APLL2>,
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 18/21] arm64: dts: mt8195: Specify audio reset controller
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Trevor Wu
From: Trevor Wu <trevor.wu@mediatek.com>
Specify audio reset controller for audio hardware resetting.
Signed-off-by: Trevor Wu <trevor.wu@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 54d8d26dd2e4..08e6ae5ce40f 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -680,6 +680,7 @@
"mediatek,mt6589-wdt";
mediatek,disable-extrst;
reg = <0 0x10007000 0 0x100>;
+ #reset-cells = <1>;
};
apmixedsys: syscon@1000c000 {
@@ -782,6 +783,8 @@
mediatek,topckgen = <&topckgen>;
power-domains = <&spm MT8195_POWER_DOMAIN_AUDIO>;
interrupts = <GIC_SPI 822 IRQ_TYPE_LEVEL_HIGH 0>;
+ resets = <&watchdog 14>;
+ reset-names = "audiosys";
clocks = <&clk26m>,
<&apmixedsys CLK_APMIXED_APLL1>,
<&apmixedsys CLK_APMIXED_APLL2>,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 19/21] arm64: dts: mt8195: Add iommu and smi nodes
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Add iommu nodes and smi nodes for mt8195.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 451 +++++++++++++++++++++++
1 file changed, 451 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 08e6ae5ce40f..7de162ba4d08 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
@@ -724,6 +725,19 @@
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
};
+ iommu_infra: infra-iommu@10315000 {
+ compatible = "mediatek,mt8195-iommu-infra";
+ reg = <0 0x10315000 0 0x5000>;
+ interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>;
+ clock-names = "bclk";
+ #iommu-cells = <1>;
+ };
+
scp: scp@10500000 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x10500000 0 0x100000>,
@@ -1438,6 +1452,64 @@
#clock-cells = <1>;
};
+ smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x14010000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x14011000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ smi_common_vpp: smi@14012000 {
+ compatible = "mediatek,mt8195-smi-common-vpp";
+ reg = <0 0x14012000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ larb4: larb@14013000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14013000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ iommu_vpp: iommu@14018000 {
+ compatible = "mediatek,mt8195-iommu-vpp";
+ reg = <0 0x14018000 0 0x1000>;
+ mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
+ &larb12 &larb14 &larb16 &larb18
+ &larb20 &larb22 &larb23 &larb26
+ &larb27>;
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
+ clock-names = "bclk";
+ #iommu-cells = <1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0 0x14e00000 0 0x1000>;
@@ -1456,24 +1528,116 @@
#clock-cells = <1>;
};
+ larb7: larb@14e04000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14e04000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&wpesys CLK_WPE_SMI_LARB7>,
+ <&wpesys CLK_WPE_SMI_LARB7>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
+ };
+
+ larb8: larb@14e05000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14e05000 0 0x1000>;
+ mediatek,larb-id = <8>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&wpesys CLK_WPE_SMI_LARB8>,
+ <&wpesys CLK_WPE_SMI_LARB8>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
+ };
+
vppsys1: clock-controller@14f00000 {
compatible = "mediatek,mt8195-vppsys1";
reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>;
};
+ larb5: larb@14f02000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14f02000 0 0x1000>;
+ mediatek,larb-id = <5>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ larb6: larb@14f03000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14f03000 0 0x1000>;
+ mediatek,larb-id = <6>;
+ mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
+ clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb9: larb@15001000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,larb-id = <9>;
+ mediatek,smi = <&smi_sub_common_img1_3x1>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
+ };
+
+ smi_sub_common_img0_3x1: smi@15002000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x15002000 0 0x1000>;
+ clocks = <&imgsys CLK_IMG_IPE>,
+ <&imgsys CLK_IMG_IPE>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
+ };
+
+ smi_sub_common_img1_3x1: smi@15003000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x15003000 0 0x1000>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vdo>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
+ };
+
imgsys1_dip_top: clock-controller@15110000 {
compatible = "mediatek,mt8195-imgsys1_dip_top";
reg = <0 0x15110000 0 0x1000>;
#clock-cells = <1>;
};
+ larb10: larb@15120000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15120000 0 0x1000>;
+ mediatek,larb-id = <10>;
+ mediatek,smi = <&smi_sub_common_img1_3x1>;
+ clocks = <&imgsys CLK_IMG_DIP0>,
+ <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
+ };
+
imgsys1_dip_nr: clock-controller@15130000 {
compatible = "mediatek,mt8195-imgsys1_dip_nr";
reg = <0 0x15130000 0 0x1000>;
@@ -1486,18 +1650,129 @@
#clock-cells = <1>;
};
+ larb11: larb@15230000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15230000 0 0x1000>;
+ mediatek,larb-id = <11>;
+ mediatek,smi = <&smi_sub_common_img1_3x1>;
+ clocks = <&imgsys CLK_IMG_WPE0>,
+ <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
+ };
+
ipesys: clock-controller@15330000 {
compatible = "mediatek,mt8195-ipesys";
reg = <0 0x15330000 0 0x1000>;
#clock-cells = <1>;
};
+ larb12: larb@15340000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15340000 0 0x1000>;
+ mediatek,larb-id = <12>;
+ mediatek,smi = <&smi_sub_common_img0_3x1>;
+ clocks = <&ipesys CLK_IPE_SMI_LARB12>,
+ <&ipesys CLK_IPE_SMI_LARB12>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
+ };
+
camsys: clock-controller@16000000 {
compatible = "mediatek,mt8195-camsys";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb13: larb@16001000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16001000 0 0x1000>;
+ mediatek,larb-id = <13>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ larb14: larb@16002000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16002000 0 0x1000>;
+ mediatek,larb-id = <14>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_LARB14>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ smi_sub_common_cam_4x1: smi@16004000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x16004000 0 0x1000>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vdo>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ smi_sub_common_cam_7x1: smi@16005000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x16005000 0 0x1000>;
+ clocks = <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CAM2MM1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ larb16: larb@16012000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16012000 0 0x1000>;
+ mediatek,larb-id = <16>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb17: larb@16013000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16013000 0 0x1000>;
+ mediatek,larb-id = <17>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
+ <&camsys_yuva CLK_CAM_YUVA_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb27: larb@16014000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16014000 0 0x1000>;
+ mediatek,larb-id = <27>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
+ };
+
+ larb28: larb@16015000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16015000 0 0x1000>;
+ mediatek,larb-id = <28>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
+ <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
+ };
+
camsys_rawa: clock-controller@1604f000 {
compatible = "mediatek,mt8195-camsys_rawa";
reg = <0 0x1604f000 0 0x1000>;
@@ -1528,24 +1803,103 @@
#clock-cells = <1>;
};
+ larb25: larb@16141000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16141000 0 0x1000>;
+ mediatek,larb-id = <25>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys_mraw CLK_CAM_MRAW_LARBX>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
+ };
+
+ larb26: larb@16142000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16142000 0 0x1000>;
+ mediatek,larb-id = <26>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
+ <&camsys_mraw CLK_CAM_MRAW_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
+
+ };
+
ccusys: clock-controller@17200000 {
compatible = "mediatek,mt8195-ccusys";
reg = <0 0x17200000 0 0x1000>;
#clock-cells = <1>;
};
+ larb18: larb@17201000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x17201000 0 0x1000>;
+ mediatek,larb-id = <18>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&ccusys CLK_CCU_LARB18>,
+ <&ccusys CLK_CCU_LARB18>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ larb24: larb@1800d000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1800d000 0 0x1000>;
+ mediatek,larb-id = <24>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+ };
+
+ larb23: larb@1800e000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1800e000 0 0x1000>;
+ mediatek,larb-id = <23>;
+ mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+ };
+
vdecsys_soc: clock-controller@1800f000 {
compatible = "mediatek,mt8195-vdecsys_soc";
reg = <0 0x1800f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb21: larb@1802e000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1802e000 0 0x1000>;
+ mediatek,larb-id = <21>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdecsys CLK_VDEC_LARB1>,
+ <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+ };
+
vdecsys: clock-controller@1802f000 {
compatible = "mediatek,mt8195-vdecsys";
reg = <0 0x1802f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb22: larb@1803e000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1803e000 0 0x1000>;
+ mediatek,larb-id = <22>;
+ mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
+ };
+
vdecsys_core1: clock-controller@1803f000 {
compatible = "mediatek,mt8195-vdecsys_core1";
reg = <0 0x1803f000 0 0x1000>;
@@ -1564,6 +1918,17 @@
#clock-cells = <1>;
};
+ larb19: larb@1a010000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1a010000 0 0x1000>;
+ mediatek,larb-id = <19>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vencsys CLK_VENC_VENC>,
+ <&vencsys CLK_VENC_GALS>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
+ };
+
vencsys_core1: clock-controller@1b000000 {
compatible = "mediatek,mt8195-vencsys_core1";
reg = <0 0x1b000000 0 0x1000>;
@@ -1576,10 +1941,96 @@
#clock-cells = <1>;
};
+ larb20: larb@1b010000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1b010000 0 0x1000>;
+ mediatek,larb-id = <20>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
+ <&vencsys_core1 CLK_VENC_CORE1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
+ };
+
+ larb0: larb@1c018000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c018000 0 0x1000>;
+ mediatek,larb-id = <0>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ };
+
+ larb1: larb@1c019000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c019000 0 0x1000>;
+ mediatek,larb-id = <1>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ };
+
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-mmsys", "syscon";
reg = <0 0x1c100000 0 0x1000>;
#clock-cells = <1>;
};
+
+ smi_common_vdo: smi@1c01b000 {
+ compatible = "mediatek,mt8195-smi-common-vdo";
+ reg = <0 0x1c01b000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
+ <&vdosys0 CLK_VDO0_SMI_EMI>,
+ <&vdosys0 CLK_VDO0_SMI_RSI>,
+ <&vdosys0 CLK_VDO0_SMI_GALS>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+
+ };
+
+ iommu_vdo: iommu@1c01f000 {
+ compatible = "mediatek,mt8195-iommu-vdo";
+ reg = <0 0x1c01f000 0 0x1000>;
+ mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
+ &larb10 &larb11 &larb13 &larb17
+ &larb19 &larb21 &larb24 &larb25
+ &larb28>;
+ interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
+ #iommu-cells = <1>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
+ clock-names = "bclk";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ };
+
+ larb2: larb@1c102000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c102000 0 0x1000>;
+ mediatek,larb-id = <2>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ };
+
+ larb3: larb@1c103000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c103000 0 0x1000>;
+ mediatek,larb-id = <3>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
+ <&vdosys1 CLK_VDO1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ };
};
};
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 19/21] arm64: dts: mt8195: Add iommu and smi nodes
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
Add iommu nodes and smi nodes for mt8195.
Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 451 +++++++++++++++++++++++
1 file changed, 451 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 08e6ae5ce40f..7de162ba4d08 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -8,6 +8,7 @@
#include <dt-bindings/clock/mt8195-clk.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/memory/mt8195-memory-port.h>
#include <dt-bindings/phy/phy.h>
#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
#include <dt-bindings/power/mt8195-power.h>
@@ -724,6 +725,19 @@
assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
};
+ iommu_infra: infra-iommu@10315000 {
+ compatible = "mediatek,mt8195-iommu-infra";
+ reg = <0 0x10315000 0 0x5000>;
+ interrupts = <GIC_SPI 795 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 796 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 797 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 798 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 799 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>;
+ clock-names = "bclk";
+ #iommu-cells = <1>;
+ };
+
scp: scp@10500000 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x10500000 0 0x100000>,
@@ -1438,6 +1452,64 @@
#clock-cells = <1>;
};
+ smi_sub_common_vpp0_vpp1_2x1: smi@14010000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x14010000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ smi_sub_common_vdec_vpp0_2x1: smi@14011000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x14011000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ smi_common_vpp: smi@14012000 {
+ compatible = "mediatek,mt8195-smi-common-vpp";
+ reg = <0 0x14012000 0 0x1000>;
+ clocks = <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>,
+ <&vppsys0 CLK_VPP0_SMI_RSI>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ larb4: larb@14013000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14013000 0 0x1000>;
+ mediatek,larb-id = <4>;
+ mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>,
+ <&vppsys0 CLK_VPP0_SMI_COMMON_LARB4>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
+ iommu_vpp: iommu@14018000 {
+ compatible = "mediatek,mt8195-iommu-vpp";
+ reg = <0 0x14018000 0 0x1000>;
+ mediatek,larbs = <&larb1 &larb3 &larb4 &larb6 &larb8
+ &larb12 &larb14 &larb16 &larb18
+ &larb20 &larb22 &larb23 &larb26
+ &larb27>;
+ interrupts = <GIC_SPI 594 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&vppsys0 CLK_VPP0_SMI_IOMMU>;
+ clock-names = "bclk";
+ #iommu-cells = <1>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS0>;
+ };
+
wpesys: clock-controller@14e00000 {
compatible = "mediatek,mt8195-wpesys";
reg = <0 0x14e00000 0 0x1000>;
@@ -1456,24 +1528,116 @@
#clock-cells = <1>;
};
+ larb7: larb@14e04000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14e04000 0 0x1000>;
+ mediatek,larb-id = <7>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&wpesys CLK_WPE_SMI_LARB7>,
+ <&wpesys CLK_WPE_SMI_LARB7>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
+ };
+
+ larb8: larb@14e05000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14e05000 0 0x1000>;
+ mediatek,larb-id = <8>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&wpesys CLK_WPE_SMI_LARB8>,
+ <&wpesys CLK_WPE_SMI_LARB8>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_WPE>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_WPESYS>;
+ };
+
vppsys1: clock-controller@14f00000 {
compatible = "mediatek,mt8195-vppsys1";
reg = <0 0x14f00000 0 0x1000>;
#clock-cells = <1>;
};
+ larb5: larb@14f02000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14f02000 0 0x1000>;
+ mediatek,larb-id = <5>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB5>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
+ larb6: larb@14f03000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x14f03000 0 0x1000>;
+ mediatek,larb-id = <6>;
+ mediatek,smi = <&smi_sub_common_vpp0_vpp1_2x1>;
+ clocks = <&vppsys1 CLK_VPP1_VPPSYS1_LARB>,
+ <&vppsys1 CLK_VPP1_VPPSYS1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VPP1_LARB6>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VPPSYS1>;
+ };
+
imgsys: clock-controller@15000000 {
compatible = "mediatek,mt8195-imgsys";
reg = <0 0x15000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb9: larb@15001000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15001000 0 0x1000>;
+ mediatek,larb-id = <9>;
+ mediatek,smi = <&smi_sub_common_img1_3x1>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
+ };
+
+ smi_sub_common_img0_3x1: smi@15002000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x15002000 0 0x1000>;
+ clocks = <&imgsys CLK_IMG_IPE>,
+ <&imgsys CLK_IMG_IPE>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
+ };
+
+ smi_sub_common_img1_3x1: smi@15003000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x15003000 0 0x1000>;
+ clocks = <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_LARB9>,
+ <&imgsys CLK_IMG_GALS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vdo>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_IMG>;
+ };
+
imgsys1_dip_top: clock-controller@15110000 {
compatible = "mediatek,mt8195-imgsys1_dip_top";
reg = <0 0x15110000 0 0x1000>;
#clock-cells = <1>;
};
+ larb10: larb@15120000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15120000 0 0x1000>;
+ mediatek,larb-id = <10>;
+ mediatek,smi = <&smi_sub_common_img1_3x1>;
+ clocks = <&imgsys CLK_IMG_DIP0>,
+ <&imgsys1_dip_top CLK_IMG1_DIP_TOP_LARB10>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
+ };
+
imgsys1_dip_nr: clock-controller@15130000 {
compatible = "mediatek,mt8195-imgsys1_dip_nr";
reg = <0 0x15130000 0 0x1000>;
@@ -1486,18 +1650,129 @@
#clock-cells = <1>;
};
+ larb11: larb@15230000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15230000 0 0x1000>;
+ mediatek,larb-id = <11>;
+ mediatek,smi = <&smi_sub_common_img1_3x1>;
+ clocks = <&imgsys CLK_IMG_WPE0>,
+ <&imgsys1_wpe CLK_IMG1_WPE_LARB11>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_DIP>;
+ };
+
ipesys: clock-controller@15330000 {
compatible = "mediatek,mt8195-ipesys";
reg = <0 0x15330000 0 0x1000>;
#clock-cells = <1>;
};
+ larb12: larb@15340000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x15340000 0 0x1000>;
+ mediatek,larb-id = <12>;
+ mediatek,smi = <&smi_sub_common_img0_3x1>;
+ clocks = <&ipesys CLK_IPE_SMI_LARB12>,
+ <&ipesys CLK_IPE_SMI_LARB12>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_IPE>;
+ };
+
camsys: clock-controller@16000000 {
compatible = "mediatek,mt8195-camsys";
reg = <0 0x16000000 0 0x1000>;
#clock-cells = <1>;
};
+ larb13: larb@16001000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16001000 0 0x1000>;
+ mediatek,larb-id = <13>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ larb14: larb@16002000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16002000 0 0x1000>;
+ mediatek,larb-id = <14>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_LARB14>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ smi_sub_common_cam_4x1: smi@16004000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x16004000 0 0x1000>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_LARB13>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vdo>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ smi_sub_common_cam_7x1: smi@16005000 {
+ compatible = "mediatek,mt8195-smi-sub-common";
+ reg = <0 0x16005000 0 0x1000>;
+ clocks = <&camsys CLK_CAM_LARB14>,
+ <&camsys CLK_CAM_CAM2MM1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_IMGSYS_CAMSYS>;
+ clock-names = "apb", "smi", "gals0";
+ mediatek,smi = <&smi_common_vpp>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ larb16: larb@16012000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16012000 0 0x1000>;
+ mediatek,larb-id = <16>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys_rawa CLK_CAM_RAWA_LARBX>,
+ <&camsys_rawa CLK_CAM_RAWA_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb17: larb@16013000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16013000 0 0x1000>;
+ mediatek,larb-id = <17>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys_yuva CLK_CAM_YUVA_LARBX>,
+ <&camsys_yuva CLK_CAM_YUVA_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWA>;
+ };
+
+ larb27: larb@16014000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16014000 0 0x1000>;
+ mediatek,larb-id = <27>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys_rawb CLK_CAM_RAWB_LARBX>,
+ <&camsys_rawb CLK_CAM_RAWB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
+ };
+
+ larb28: larb@16015000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16015000 0 0x1000>;
+ mediatek,larb-id = <28>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys_yuvb CLK_CAM_YUVB_LARBX>,
+ <&camsys_yuvb CLK_CAM_YUVB_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_RAWB>;
+ };
+
camsys_rawa: clock-controller@1604f000 {
compatible = "mediatek,mt8195-camsys_rawa";
reg = <0 0x1604f000 0 0x1000>;
@@ -1528,24 +1803,103 @@
#clock-cells = <1>;
};
+ larb25: larb@16141000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16141000 0 0x1000>;
+ mediatek,larb-id = <25>;
+ mediatek,smi = <&smi_sub_common_cam_4x1>;
+ clocks = <&camsys CLK_CAM_LARB13>,
+ <&camsys_mraw CLK_CAM_MRAW_LARBX>,
+ <&camsys CLK_CAM_CAM2MM0_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
+ };
+
+ larb26: larb@16142000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x16142000 0 0x1000>;
+ mediatek,larb-id = <26>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&camsys_mraw CLK_CAM_MRAW_LARBX>,
+ <&camsys_mraw CLK_CAM_MRAW_LARBX>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM_MRAW>;
+
+ };
+
ccusys: clock-controller@17200000 {
compatible = "mediatek,mt8195-ccusys";
reg = <0 0x17200000 0 0x1000>;
#clock-cells = <1>;
};
+ larb18: larb@17201000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x17201000 0 0x1000>;
+ mediatek,larb-id = <18>;
+ mediatek,smi = <&smi_sub_common_cam_7x1>;
+ clocks = <&ccusys CLK_CCU_LARB18>,
+ <&ccusys CLK_CCU_LARB18>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_CAM>;
+ };
+
+ larb24: larb@1800d000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1800d000 0 0x1000>;
+ mediatek,larb-id = <24>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+ };
+
+ larb23: larb@1800e000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1800e000 0 0x1000>;
+ mediatek,larb-id = <23>;
+ mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC0>;
+ };
+
vdecsys_soc: clock-controller@1800f000 {
compatible = "mediatek,mt8195-vdecsys_soc";
reg = <0 0x1800f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb21: larb@1802e000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1802e000 0 0x1000>;
+ mediatek,larb-id = <21>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdecsys CLK_VDEC_LARB1>,
+ <&vdecsys CLK_VDEC_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC1>;
+ };
+
vdecsys: clock-controller@1802f000 {
compatible = "mediatek,mt8195-vdecsys";
reg = <0 0x1802f000 0 0x1000>;
#clock-cells = <1>;
};
+ larb22: larb@1803e000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1803e000 0 0x1000>;
+ mediatek,larb-id = <22>;
+ mediatek,smi = <&smi_sub_common_vdec_vpp0_2x1>;
+ clocks = <&vppsys0 CLK_VPP0_GALS_VDEC_VDEC_CORE1>,
+ <&vdecsys_core1 CLK_VDEC_CORE1_LARB1>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDEC2>;
+ };
+
vdecsys_core1: clock-controller@1803f000 {
compatible = "mediatek,mt8195-vdecsys_core1";
reg = <0 0x1803f000 0 0x1000>;
@@ -1564,6 +1918,17 @@
#clock-cells = <1>;
};
+ larb19: larb@1a010000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1a010000 0 0x1000>;
+ mediatek,larb-id = <19>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vencsys CLK_VENC_VENC>,
+ <&vencsys CLK_VENC_GALS>;
+ clock-names = "apb", "smi";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VENC>;
+ };
+
vencsys_core1: clock-controller@1b000000 {
compatible = "mediatek,mt8195-vencsys_core1";
reg = <0 0x1b000000 0 0x1000>;
@@ -1576,10 +1941,96 @@
#clock-cells = <1>;
};
+ larb20: larb@1b010000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1b010000 0 0x1000>;
+ mediatek,larb-id = <20>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&vencsys_core1 CLK_VENC_CORE1_LARB>,
+ <&vencsys_core1 CLK_VENC_CORE1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
+ };
+
+ larb0: larb@1c018000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c018000 0 0x1000>;
+ mediatek,larb-id = <0>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB0>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ };
+
+ larb1: larb@1c019000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c019000 0 0x1000>;
+ mediatek,larb-id = <1>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_LARB>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_LARB1>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ };
+
vdosys1: syscon@1c100000 {
compatible = "mediatek,mt8195-mmsys", "syscon";
reg = <0 0x1c100000 0 0x1000>;
#clock-cells = <1>;
};
+
+ smi_common_vdo: smi@1c01b000 {
+ compatible = "mediatek,mt8195-smi-common-vdo";
+ reg = <0 0x1c01b000 0 0x1000>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_COMMON>,
+ <&vdosys0 CLK_VDO0_SMI_EMI>,
+ <&vdosys0 CLK_VDO0_SMI_RSI>,
+ <&vdosys0 CLK_VDO0_SMI_GALS>;
+ clock-names = "apb", "smi", "gals0", "gals1";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+
+ };
+
+ iommu_vdo: iommu@1c01f000 {
+ compatible = "mediatek,mt8195-iommu-vdo";
+ reg = <0 0x1c01f000 0 0x1000>;
+ mediatek,larbs = <&larb0 &larb2 &larb5 &larb7 &larb9
+ &larb10 &larb11 &larb13 &larb17
+ &larb19 &larb21 &larb24 &larb25
+ &larb28>;
+ interrupts = <GIC_SPI 669 IRQ_TYPE_LEVEL_HIGH 0>;
+ #iommu-cells = <1>;
+ clocks = <&vdosys0 CLK_VDO0_SMI_IOMMU>;
+ clock-names = "bclk";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ };
+
+ larb2: larb@1c102000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c102000 0 0x1000>;
+ mediatek,larb-id = <2>;
+ mediatek,smi = <&smi_common_vdo>;
+ clocks = <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_SMI_LARB2>,
+ <&vdosys1 CLK_VDO1_GALS>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ };
+
+ larb3: larb@1c103000 {
+ compatible = "mediatek,mt8195-smi-larb";
+ reg = <0 0x1c103000 0 0x1000>;
+ mediatek,larb-id = <3>;
+ mediatek,smi = <&smi_common_vpp>;
+ clocks = <&vdosys1 CLK_VDO1_SMI_LARB3>,
+ <&vdosys1 CLK_VDO1_GALS>,
+ <&vppsys0 CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1>;
+ clock-names = "apb", "smi", "gals";
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS1>;
+ };
};
};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 20/21] arm64: dts: mt8195: Add gce node
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Jason-JH.Lin
From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
Add gce node and gce alias to mt8195 device tree.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 7de162ba4d08..06fd03906f21 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
@@ -19,6 +20,11 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ gce0 = &gce0;
+ gce1 = &gce1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -738,6 +744,22 @@
#iommu-cells = <1>;
};
+ gce0: mailbox@10320000 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x10320000 0 0x4000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+ };
+
+ gce1: mailbox@10330000 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x10330000 0 0x4000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
+ };
+
scp: scp@10500000 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x10500000 0 0x100000>,
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 20/21] arm64: dts: mt8195: Add gce node
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Jason-JH.Lin
From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
Add gce node and gce alias to mt8195 device tree.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 22 ++++++++++++++++++++++
1 file changed, 22 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 7de162ba4d08..06fd03906f21 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -6,6 +6,7 @@
/dts-v1/;
#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/gce/mt8195-gce.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/interrupt-controller/irq.h>
#include <dt-bindings/memory/mt8195-memory-port.h>
@@ -19,6 +20,11 @@
#address-cells = <2>;
#size-cells = <2>;
+ aliases {
+ gce0 = &gce0;
+ gce1 = &gce1;
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -738,6 +744,22 @@
#iommu-cells = <1>;
};
+ gce0: mailbox@10320000 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x10320000 0 0x4000>;
+ interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE>;
+ };
+
+ gce1: mailbox@10330000 {
+ compatible = "mediatek,mt8195-gce";
+ reg = <0 0x10330000 0 0x4000>;
+ interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <2>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_GCE2>;
+ };
+
scp: scp@10500000 {
compatible = "mediatek,mt8195-scp";
reg = <0 0x10500000 0 0x100000>,
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 21/21] arm64: dts: mt8195: Add display node for vdosys0
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 12:30 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Jason-JH.Lin
From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
Add display node for vdosys0 of mt8195.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 93 ++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 06fd03906f21..cb98ab5bf9ca 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1960,6 +1960,7 @@
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-mmsys", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
@@ -1975,6 +1976,98 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
};
+ ovl0: ovl@1c000000 {
+ compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
+ reg = <0 0x1c000000 0 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
+ };
+
+ rdma0: rdma@1c002000 {
+ compatible = "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
+ };
+
+ color0: color@1c003000 {
+ compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
+ };
+
+ ccorr0: ccorr@1c004000 {
+ compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
+ };
+
+ aal0: aal@1c005000 {
+ compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
+ };
+
+ gamma0: gamma@1c006000 {
+ compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
+ };
+
+ dither0: dither@1c007000 {
+ compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
+ };
+
+ dsc0: dsc@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+ merge0: merge@1c014000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c014000 0 0x1000>;
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
+ };
+
+ mutex: mutex@1c016000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c016000 0 0x1000>;
+ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+ };
+
larb0: larb@1c018000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1c018000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 70+ messages in thread
* [PATCH v3 21/21] arm64: dts: mt8195: Add display node for vdosys0
@ 2022-07-20 12:30 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-20 12:30 UTC (permalink / raw)
To: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Lee Jones, Matthias Brugger, Tinghan Shen,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group,
Jason-JH.Lin
From: "Jason-JH.Lin" <jason-jh.lin@mediatek.com>
Add display node for vdosys0 of mt8195.
Signed-off-by: Jason-JH.Lin <jason-jh.lin@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 93 ++++++++++++++++++++++++
1 file changed, 93 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
index 06fd03906f21..cb98ab5bf9ca 100644
--- a/arch/arm64/boot/dts/mediatek/mt8195.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -1960,6 +1960,7 @@
vdosys0: syscon@1c01a000 {
compatible = "mediatek,mt8195-mmsys", "syscon";
reg = <0 0x1c01a000 0 0x1000>;
+ mboxes = <&gce0 0 CMDQ_THR_PRIO_4>;
#clock-cells = <1>;
};
@@ -1975,6 +1976,98 @@
power-domains = <&spm MT8195_POWER_DOMAIN_VENC_CORE1>;
};
+ ovl0: ovl@1c000000 {
+ compatible = "mediatek,mt8195-disp-ovl", "mediatek,mt8183-disp-ovl";
+ reg = <0 0x1c000000 0 0x1000>;
+ interrupts = <GIC_SPI 636 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_OVL0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_OVL0_RDMA0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x0000 0x1000>;
+ };
+
+ rdma0: rdma@1c002000 {
+ compatible = "mediatek,mt8195-disp-rdma";
+ reg = <0 0x1c002000 0 0x1000>;
+ interrupts = <GIC_SPI 638 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_RDMA0>;
+ iommus = <&iommu_vdo M4U_PORT_L0_DISP_RDMA0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x2000 0x1000>;
+ };
+
+ color0: color@1c003000 {
+ compatible = "mediatek,mt8195-disp-color", "mediatek,mt8173-disp-color";
+ reg = <0 0x1c003000 0 0x1000>;
+ interrupts = <GIC_SPI 639 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_COLOR0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x3000 0x1000>;
+ };
+
+ ccorr0: ccorr@1c004000 {
+ compatible = "mediatek,mt8195-disp-ccorr", "mediatek,mt8192-disp-ccorr";
+ reg = <0 0x1c004000 0 0x1000>;
+ interrupts = <GIC_SPI 640 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_CCORR0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x4000 0x1000>;
+ };
+
+ aal0: aal@1c005000 {
+ compatible = "mediatek,mt8195-disp-aal", "mediatek,mt8183-disp-aal";
+ reg = <0 0x1c005000 0 0x1000>;
+ interrupts = <GIC_SPI 641 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_AAL0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x5000 0x1000>;
+ };
+
+ gamma0: gamma@1c006000 {
+ compatible = "mediatek,mt8195-disp-gamma", "mediatek,mt8183-disp-gamma";
+ reg = <0 0x1c006000 0 0x1000>;
+ interrupts = <GIC_SPI 642 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_GAMMA0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x6000 0x1000>;
+ };
+
+ dither0: dither@1c007000 {
+ compatible = "mediatek,mt8195-disp-dither", "mediatek,mt8183-disp-dither";
+ reg = <0 0x1c007000 0 0x1000>;
+ interrupts = <GIC_SPI 643 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_DITHER0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x7000 0x1000>;
+ };
+
+ dsc0: dsc@1c009000 {
+ compatible = "mediatek,mt8195-disp-dsc";
+ reg = <0 0x1c009000 0 0x1000>;
+ interrupts = <GIC_SPI 645 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DSC_WRAP0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c00XXXX 0x9000 0x1000>;
+ };
+
+ merge0: merge@1c014000 {
+ compatible = "mediatek,mt8195-disp-merge";
+ reg = <0 0x1c014000 0 0x1000>;
+ interrupts = <GIC_SPI 656 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_VPP_MERGE0>;
+ mediatek,gce-client-reg = <&gce0 SUBSYS_1c01XXXX 0x4000 0x1000>;
+ };
+
+ mutex: mutex@1c016000 {
+ compatible = "mediatek,mt8195-disp-mutex";
+ reg = <0 0x1c016000 0 0x1000>;
+ interrupts = <GIC_SPI 658 IRQ_TYPE_LEVEL_HIGH 0>;
+ power-domains = <&spm MT8195_POWER_DOMAIN_VDOSYS0>;
+ clocks = <&vdosys0 CLK_VDO0_DISP_MUTEX0>;
+ mediatek,gce-events = <CMDQ_EVENT_VDO0_DISP_STREAM_DONE_0>;
+ };
+
larb0: larb@1c018000 {
compatible = "mediatek,mt8195-smi-larb";
reg = <0 0x1c018000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 13:31 ` Lee Jones
-1 siblings, 0 replies; 70+ messages in thread
From: Lee Jones @ 2022-07-20 13:31 UTC (permalink / raw)
To: Tinghan Shen
Cc: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu, iommu, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On Wed, 20 Jul 2022, Tinghan Shen wrote:
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. Add the bindings for it.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Why have you ignored my review comments from v2?
> ---
> .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> new file mode 100644
> index 000000000000..4117a6dbc19c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek System Control Processor System
> +
> +maintainers:
> + - MandyJH Liu <mandyjh.liu@mediatek.com>
> +
> +description:
> + MediaTek System Control Processor System (SCPSYS) has several
> + power management tasks. The tasks include MTCMOS power
> + domain control, thermal measurement, DVFS, etc.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8167-scpsys
> + - mediatek,mt8173-scpsys
> + - mediatek,mt8183-scpsys
> + - mediatek,mt8192-scpsys
> + - mediatek,mt8195-scpsys
> + - const: syscon
> + - const: simple-mfd
> +
> + reg:
> + maxItems: 1
> +
> +patternProperties:
> + "^power-controller(@[0-9a-f]+)?$":
> + $ref: /schemas/power/mediatek,power-controller.yaml#
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8195-clk.h>
> + #include <dt-bindings/power/mt8195-power.h>
> +
> + syscon@10006000 {
> + compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
> + reg = <0x10006000 0x100>;
> +
> + spm: power-controller {
> + compatible = "mediatek,mt8195-power-controller";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + /* sample of power domain nodes */
> + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
> + reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
> + reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };
--
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
@ 2022-07-20 13:31 ` Lee Jones
0 siblings, 0 replies; 70+ messages in thread
From: Lee Jones @ 2022-07-20 13:31 UTC (permalink / raw)
To: Tinghan Shen
Cc: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu, iommu, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On Wed, 20 Jul 2022, Tinghan Shen wrote:
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. Add the bindings for it.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Why have you ignored my review comments from v2?
> ---
> .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> new file mode 100644
> index 000000000000..4117a6dbc19c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek System Control Processor System
> +
> +maintainers:
> + - MandyJH Liu <mandyjh.liu@mediatek.com>
> +
> +description:
> + MediaTek System Control Processor System (SCPSYS) has several
> + power management tasks. The tasks include MTCMOS power
> + domain control, thermal measurement, DVFS, etc.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8167-scpsys
> + - mediatek,mt8173-scpsys
> + - mediatek,mt8183-scpsys
> + - mediatek,mt8192-scpsys
> + - mediatek,mt8195-scpsys
> + - const: syscon
> + - const: simple-mfd
> +
> + reg:
> + maxItems: 1
> +
> +patternProperties:
> + "^power-controller(@[0-9a-f]+)?$":
> + $ref: /schemas/power/mediatek,power-controller.yaml#
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8195-clk.h>
> + #include <dt-bindings/power/mt8195-power.h>
> +
> + syscon@10006000 {
> + compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
> + reg = <0x10006000 0x100>;
> +
> + spm: power-controller {
> + compatible = "mediatek,mt8195-power-controller";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + /* sample of power domain nodes */
> + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
> + reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
> + #power-domain-cells = <0>;
> + };
> +
> + power-domain@MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY {
> + reg = <MT8195_POWER_DOMAIN_SSUSB_PCIE_PHY>;
> + #power-domain-cells = <0>;
> + };
> + };
> + };
--
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 01/21] dt-bindings: iommu: mediatek: Increase max interrupt number
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 17:30 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:30 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> mt8195 infra iommu uses 5 interrupts.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 01/21] dt-bindings: iommu: mediatek: Increase max interrupt number
@ 2022-07-20 17:30 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:30 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> mt8195 infra iommu uses 5 interrupts.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 03/21] dt-bindings: power: mediatek: Refine multiple level power domain nodes
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 17:32 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:32 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> Extract duplicated properties and support more levels of power
> domain nodes.
>
> This change fix following error when do dtbs_check,
> arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: power-controller: power-domain@15:power-domain@16:power-domain@18: 'power-domain@19', 'power-domain@20', 'power-domain@21' do not match any of the regexes: 'pinctrl-[0-9]+'
> From schema: Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> .../power/mediatek,power-controller.yaml | 131 +++---------------
> 1 file changed, 17 insertions(+), 114 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> index b448101fac43..321802c95308 100644
> --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> @@ -42,6 +42,23 @@ properties:
>
> patternProperties:
> "^power-domain@[0-9a-f]+$":
> + $ref: "#/$defs/power-domain-node"
> + patternProperties:
> + "^power-domain@[0-9a-f]+$":
> + $ref: "#/$defs/power-domain-node"
> + patternProperties:
> + "^power-domain@[0-9a-f]+$":
> + $ref: "#/$defs/power-domain-node"
> + patternProperties:
> + "^power-domain@[0-9a-f]+$":
> + $ref: "#/$defs/power-domain-node"
> + unevaluatedProperties: false
> + unevaluatedProperties: false
> + unevaluatedProperties: false
> + unevaluatedProperties: false
I see some beauty in previous endless recurrence, but at least we are
specific...
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 03/21] dt-bindings: power: mediatek: Refine multiple level power domain nodes
@ 2022-07-20 17:32 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:32 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> Extract duplicated properties and support more levels of power
> domain nodes.
>
> This change fix following error when do dtbs_check,
> arch/arm64/boot/dts/mediatek/mt8195-evb.dtb: power-controller: power-domain@15:power-domain@16:power-domain@18: 'power-domain@19', 'power-domain@20', 'power-domain@21' do not match any of the regexes: 'pinctrl-[0-9]+'
> From schema: Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> .../power/mediatek,power-controller.yaml | 131 +++---------------
> 1 file changed, 17 insertions(+), 114 deletions(-)
>
> diff --git a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> index b448101fac43..321802c95308 100644
> --- a/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> +++ b/Documentation/devicetree/bindings/power/mediatek,power-controller.yaml
> @@ -42,6 +42,23 @@ properties:
>
> patternProperties:
> "^power-domain@[0-9a-f]+$":
> + $ref: "#/$defs/power-domain-node"
> + patternProperties:
> + "^power-domain@[0-9a-f]+$":
> + $ref: "#/$defs/power-domain-node"
> + patternProperties:
> + "^power-domain@[0-9a-f]+$":
> + $ref: "#/$defs/power-domain-node"
> + patternProperties:
> + "^power-domain@[0-9a-f]+$":
> + $ref: "#/$defs/power-domain-node"
> + unevaluatedProperties: false
> + unevaluatedProperties: false
> + unevaluatedProperties: false
> + unevaluatedProperties: false
I see some beauty in previous endless recurrence, but at least we are
specific...
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 04/21] dt-bindings: power: mediatek: Support naming power controller node with unit address
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 17:32 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:32 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> Support naming power controller node with unit address, also compatible
> with node names without unit address.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 04/21] dt-bindings: power: mediatek: Support naming power controller node with unit address
@ 2022-07-20 17:32 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:32 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> Support naming power controller node with unit address, also compatible
> with node names without unit address.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 17:35 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:35 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. Add the bindings for it.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> new file mode 100644
> index 000000000000..4117a6dbc19c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek System Control Processor System
> +
> +maintainers:
> + - MandyJH Liu <mandyjh.liu@mediatek.com>
> +
> +description:
> + MediaTek System Control Processor System (SCPSYS) has several
> + power management tasks. The tasks include MTCMOS power
> + domain control, thermal measurement, DVFS, etc.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8167-scpsys
> + - mediatek,mt8173-scpsys
> + - mediatek,mt8183-scpsys
> + - mediatek,mt8192-scpsys
> + - mediatek,mt8195-scpsys
> + - const: syscon
> + - const: simple-mfd
> +
> + reg:
> + maxItems: 1
> +
> +patternProperties:
> + "^power-controller(@[0-9a-f]+)?$":
> + $ref: /schemas/power/mediatek,power-controller.yaml#
We talked that unit address might be useful but it was with an
assumption that you will actually use it. I think you don't use it, so
it is kind of meaningless now... unless you plan to use it?
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8195-clk.h>
> + #include <dt-bindings/power/mt8195-power.h>
> +
> + syscon@10006000 {
> + compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
> + reg = <0x10006000 0x100>;
> +
> + spm: power-controller {
> + compatible = "mediatek,mt8195-power-controller";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + /* sample of power domain nodes */
> + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
> + reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
Wrong indentation.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
@ 2022-07-20 17:35 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:35 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> The System Control Processor System (SCPSYS) has several power
> management related tasks in the system. Add the bindings for it.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 +++++++++++++++++++
> 1 file changed, 68 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>
> diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> new file mode 100644
> index 000000000000..4117a6dbc19c
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> @@ -0,0 +1,68 @@
> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek System Control Processor System
> +
> +maintainers:
> + - MandyJH Liu <mandyjh.liu@mediatek.com>
> +
> +description:
> + MediaTek System Control Processor System (SCPSYS) has several
> + power management tasks. The tasks include MTCMOS power
> + domain control, thermal measurement, DVFS, etc.
> +
> +properties:
> + compatible:
> + items:
> + - enum:
> + - mediatek,mt8167-scpsys
> + - mediatek,mt8173-scpsys
> + - mediatek,mt8183-scpsys
> + - mediatek,mt8192-scpsys
> + - mediatek,mt8195-scpsys
> + - const: syscon
> + - const: simple-mfd
> +
> + reg:
> + maxItems: 1
> +
> +patternProperties:
> + "^power-controller(@[0-9a-f]+)?$":
> + $ref: /schemas/power/mediatek,power-controller.yaml#
We talked that unit address might be useful but it was with an
assumption that you will actually use it. I think you don't use it, so
it is kind of meaningless now... unless you plan to use it?
> +
> +required:
> + - compatible
> + - reg
> +
> +additionalProperties: false
> +
> +examples:
> + - |
> + #include <dt-bindings/clock/mt8195-clk.h>
> + #include <dt-bindings/power/mt8195-power.h>
> +
> + syscon@10006000 {
> + compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
> + reg = <0x10006000 0x100>;
> +
> + spm: power-controller {
> + compatible = "mediatek,mt8195-power-controller";
> + #address-cells = <1>;
> + #size-cells = <0>;
> + #power-domain-cells = <1>;
> +
> + /* sample of power domain nodes */
> + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
> + reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
Wrong indentation.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
2022-07-20 13:31 ` Lee Jones
@ 2022-07-20 17:37 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:37 UTC (permalink / raw)
To: Lee Jones, Tinghan Shen
Cc: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu, iommu, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 20/07/2022 15:31, Lee Jones wrote:
> On Wed, 20 Jul 2022, Tinghan Shen wrote:
>
>> The System Control Processor System (SCPSYS) has several power
>> management related tasks in the system. Add the bindings for it.
>>
>> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
>
> Why have you ignored my review comments from v2?
If you refer whether the binding is needed at all, then the answer is
yes, because this is not simple syscons but a device with children,
which we want to parse/match.
Anyway Tinghan should respond to you about way how he proceeds...
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
@ 2022-07-20 17:37 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:37 UTC (permalink / raw)
To: Lee Jones, Tinghan Shen
Cc: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu, iommu, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On 20/07/2022 15:31, Lee Jones wrote:
> On Wed, 20 Jul 2022, Tinghan Shen wrote:
>
>> The System Control Processor System (SCPSYS) has several power
>> management related tasks in the system. Add the bindings for it.
>>
>> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
>
> Why have you ignored my review comments from v2?
If you refer whether the binding is needed at all, then the answer is
yes, because this is not simple syscons but a device with children,
which we want to parse/match.
Anyway Tinghan should respond to you about way how he proceeds...
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 07/21] dt-bindings: power: mediatek: Update example in dt-bindings
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 17:38 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:38 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> Update the scpsys node compatible string to align with the
> scpsys node bindings.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Squash it with previous because logically it's the same change.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 07/21] dt-bindings: power: mediatek: Update example in dt-bindings
@ 2022-07-20 17:38 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:38 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> Update the scpsys node compatible string to align with the
> scpsys node bindings.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Squash it with previous because logically it's the same change.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 08/21] arm64: dts: mediatek: Update mt81xx scpsys node to align with dt-bindings
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-20 17:39 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:39 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> Update scpsys nodes using simple-mfd in mt81xx SoC devicetree
> to align with the bindings.
"Update" is not accurate enough description. The same in commit title.
It answers "why" you are doing it, but does not answer what exactly you
are changing here and what is the effect. IOW, you need to explain the
true logic behind it - 10006000 is not power domain provider etc.
>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 08/21] arm64: dts: mediatek: Update mt81xx scpsys node to align with dt-bindings
@ 2022-07-20 17:39 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-20 17:39 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 20/07/2022 14:30, Tinghan Shen wrote:
> Update scpsys nodes using simple-mfd in mt81xx SoC devicetree
> to align with the bindings.
"Update" is not accurate enough description. The same in commit title.
It answers "why" you are doing it, but does not answer what exactly you
are changing here and what is the effect. IOW, you need to explain the
true logic behind it - 10006000 is not power domain provider etc.
>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
2022-07-20 17:37 ` Krzysztof Kozlowski
@ 2022-07-21 2:35 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-21 2:35 UTC (permalink / raw)
To: Krzysztof Kozlowski, Lee Jones
Cc: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu, iommu, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On Wed, 2022-07-20 at 19:37 +0200, Krzysztof Kozlowski wrote:
> On 20/07/2022 15:31, Lee Jones wrote:
> > On Wed, 20 Jul 2022, Tinghan Shen wrote:
> >
> > > The System Control Processor System (SCPSYS) has several power
> > > management related tasks in the system. Add the bindings for it.
> > >
> > > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> >
> > Why have you ignored my review comments from v2?
>
> If you refer whether the binding is needed at all, then the answer is
> yes, because this is not simple syscons but a device with children,
> which we want to parse/match.
>
> Anyway Tinghan should respond to you about way how he proceeds...
>
> Best regards,
> Krzysztof
Hi Lee,
I'm so sorry for not answering your feedback. I misunderstood it
that you're waiting the review result of DT maintainers.
This binding is added because of the discussion of the scpsys node[1].
I first looked at mfd/syscon.yaml to see if I could use it.
I found that it doesn't have the 'simple-mfd' compatible, so I decide to add a new one.
It's because I need the 'simple-mfd' compatible to parse child nodes.
[1] https://lore.kernel.org/all/f7eee4e8-05fa-4c83-9168-64e5ea4c510f@linaro.org/
Best regards,
TingHan
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
@ 2022-07-21 2:35 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-21 2:35 UTC (permalink / raw)
To: Krzysztof Kozlowski, Lee Jones
Cc: Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu, iommu, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On Wed, 2022-07-20 at 19:37 +0200, Krzysztof Kozlowski wrote:
> On 20/07/2022 15:31, Lee Jones wrote:
> > On Wed, 20 Jul 2022, Tinghan Shen wrote:
> >
> > > The System Control Processor System (SCPSYS) has several power
> > > management related tasks in the system. Add the bindings for it.
> > >
> > > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> >
> > Why have you ignored my review comments from v2?
>
> If you refer whether the binding is needed at all, then the answer is
> yes, because this is not simple syscons but a device with children,
> which we want to parse/match.
>
> Anyway Tinghan should respond to you about way how he proceeds...
>
> Best regards,
> Krzysztof
Hi Lee,
I'm so sorry for not answering your feedback. I misunderstood it
that you're waiting the review result of DT maintainers.
This binding is added because of the discussion of the scpsys node[1].
I first looked at mfd/syscon.yaml to see if I could use it.
I found that it doesn't have the 'simple-mfd' compatible, so I decide to add a new one.
It's because I need the 'simple-mfd' compatible to parse child nodes.
[1] https://lore.kernel.org/all/f7eee4e8-05fa-4c83-9168-64e5ea4c510f@linaro.org/
Best regards,
TingHan
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
2022-07-20 17:35 ` Krzysztof Kozlowski
@ 2022-07-21 3:05 ` Tinghan Shen
-1 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-21 3:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, Yong Wu, Joerg Roedel, Will Deacon,
Robin Murphy, Rob Herring, Krzysztof Kozlowski, Lee Jones,
Matthias Brugger, AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Wed, 2022-07-20 at 19:35 +0200, Krzysztof Kozlowski wrote:
> On 20/07/2022 14:30, Tinghan Shen wrote:
> > The System Control Processor System (SCPSYS) has several power
> > management related tasks in the system. Add the bindings for it.
> >
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 +++++++++++++++++++
> > 1 file changed, 68 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> > b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> > new file mode 100644
> > index 000000000000..4117a6dbc19c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> > @@ -0,0 +1,68 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml*__;Iw!!CTRNKA9wMg0ARbw!y63E-9qbCW_vyn8RrsCCs7YvZ7NxKqFT7l8C0ZZirEW95Ec0ce3lwegsSq51wrjtz8GjVSpkK-omCBP5CKx1l0WESQ$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y63E-9qbCW_vyn8RrsCCs7YvZ7NxKqFT7l8C0ZZirEW95Ec0ce3lwegsSq51wrjtz8GjVSpkK-omCBP5CKzzr9p82Q$
> >
> > +
> > +title: MediaTek System Control Processor System
> > +
> > +maintainers:
> > + - MandyJH Liu <mandyjh.liu@mediatek.com>
> > +
> > +description:
> > + MediaTek System Control Processor System (SCPSYS) has several
> > + power management tasks. The tasks include MTCMOS power
> > + domain control, thermal measurement, DVFS, etc.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8167-scpsys
> > + - mediatek,mt8173-scpsys
> > + - mediatek,mt8183-scpsys
> > + - mediatek,mt8192-scpsys
> > + - mediatek,mt8195-scpsys
> > + - const: syscon
> > + - const: simple-mfd
> > +
> > + reg:
> > + maxItems: 1
> > +
> > +patternProperties:
> > + "^power-controller(@[0-9a-f]+)?$":
> > + $ref: /schemas/power/mediatek,power-controller.yaml#
>
> We talked that unit address might be useful but it was with an
> assumption that you will actually use it. I think you don't use it, so
> it is kind of meaningless now... unless you plan to use it?
I tried to add the offset in the node name, but the binding check reports this message.
power-controller@0: node has a unit name, but no reg or ranges property
After considering the fact of mt8195 power controller HW resides in scpsys and the current power
domain driver doesn't support parsing the register address seperated from scpsys, I decide to
keep the power controller node as in v2 to pass the binding check and compatible with driver.
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8195-clk.h>
> > + #include <dt-bindings/power/mt8195-power.h>
> > +
> > + syscon@10006000 {
> > + compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
> > + reg = <0x10006000 0x100>;
> > +
> > + spm: power-controller {
> > + compatible = "mediatek,mt8195-power-controller";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #power-domain-cells = <1>;
> > +
> > + /* sample of power domain nodes */
> > + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
> > + reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
>
> Wrong indentation.
I missed checking this. I'll udpate in the next version.
Thanks,
TingHan
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
@ 2022-07-21 3:05 ` Tinghan Shen
0 siblings, 0 replies; 70+ messages in thread
From: Tinghan Shen @ 2022-07-21 3:05 UTC (permalink / raw)
To: Krzysztof Kozlowski, Yong Wu, Joerg Roedel, Will Deacon,
Robin Murphy, Rob Herring, Krzysztof Kozlowski, Lee Jones,
Matthias Brugger, AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On Wed, 2022-07-20 at 19:35 +0200, Krzysztof Kozlowski wrote:
> On 20/07/2022 14:30, Tinghan Shen wrote:
> > The System Control Processor System (SCPSYS) has several power
> > management related tasks in the system. Add the bindings for it.
> >
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 +++++++++++++++++++
> > 1 file changed, 68 insertions(+)
> > create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> >
> > diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> > b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> > new file mode 100644
> > index 000000000000..4117a6dbc19c
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
> > @@ -0,0 +1,68 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml*__;Iw!!CTRNKA9wMg0ARbw!y63E-9qbCW_vyn8RrsCCs7YvZ7NxKqFT7l8C0ZZirEW95Ec0ce3lwegsSq51wrjtz8GjVSpkK-omCBP5CKx1l0WESQ$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y63E-9qbCW_vyn8RrsCCs7YvZ7NxKqFT7l8C0ZZirEW95Ec0ce3lwegsSq51wrjtz8GjVSpkK-omCBP5CKzzr9p82Q$
> >
> > +
> > +title: MediaTek System Control Processor System
> > +
> > +maintainers:
> > + - MandyJH Liu <mandyjh.liu@mediatek.com>
> > +
> > +description:
> > + MediaTek System Control Processor System (SCPSYS) has several
> > + power management tasks. The tasks include MTCMOS power
> > + domain control, thermal measurement, DVFS, etc.
> > +
> > +properties:
> > + compatible:
> > + items:
> > + - enum:
> > + - mediatek,mt8167-scpsys
> > + - mediatek,mt8173-scpsys
> > + - mediatek,mt8183-scpsys
> > + - mediatek,mt8192-scpsys
> > + - mediatek,mt8195-scpsys
> > + - const: syscon
> > + - const: simple-mfd
> > +
> > + reg:
> > + maxItems: 1
> > +
> > +patternProperties:
> > + "^power-controller(@[0-9a-f]+)?$":
> > + $ref: /schemas/power/mediatek,power-controller.yaml#
>
> We talked that unit address might be useful but it was with an
> assumption that you will actually use it. I think you don't use it, so
> it is kind of meaningless now... unless you plan to use it?
I tried to add the offset in the node name, but the binding check reports this message.
power-controller@0: node has a unit name, but no reg or ranges property
After considering the fact of mt8195 power controller HW resides in scpsys and the current power
domain driver doesn't support parsing the register address seperated from scpsys, I decide to
keep the power controller node as in v2 to pass the binding check and compatible with driver.
>
> > +
> > +required:
> > + - compatible
> > + - reg
> > +
> > +additionalProperties: false
> > +
> > +examples:
> > + - |
> > + #include <dt-bindings/clock/mt8195-clk.h>
> > + #include <dt-bindings/power/mt8195-power.h>
> > +
> > + syscon@10006000 {
> > + compatible = "mediatek,mt8195-scpsys", "syscon", "simple-mfd";
> > + reg = <0x10006000 0x100>;
> > +
> > + spm: power-controller {
> > + compatible = "mediatek,mt8195-power-controller";
> > + #address-cells = <1>;
> > + #size-cells = <0>;
> > + #power-domain-cells = <1>;
> > +
> > + /* sample of power domain nodes */
> > + power-domain@MT8195_POWER_DOMAIN_PCIE_PHY {
> > + reg = <MT8195_POWER_DOMAIN_PCIE_PHY>;
>
> Wrong indentation.
I missed checking this. I'll udpate in the next version.
Thanks,
TingHan
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
2022-07-21 3:05 ` Tinghan Shen
@ 2022-07-21 6:34 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-21 6:34 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 21/07/2022 05:05, Tinghan Shen wrote:
> On Wed, 2022-07-20 at 19:35 +0200, Krzysztof Kozlowski wrote:
>> On 20/07/2022 14:30, Tinghan Shen wrote:
>>> The System Control Processor System (SCPSYS) has several power
>>> management related tasks in the system. Add the bindings for it.
>>>
>>> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
>>> ---
>>> .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 +++++++++++++++++++
>>> 1 file changed, 68 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>>> b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>>> new file mode 100644
>>> index 000000000000..4117a6dbc19c
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>>> @@ -0,0 +1,68 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id:
>>> https://urldefense.com/v3/__http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml*__;Iw!!CTRNKA9wMg0ARbw!y63E-9qbCW_vyn8RrsCCs7YvZ7NxKqFT7l8C0ZZirEW95Ec0ce3lwegsSq51wrjtz8GjVSpkK-omCBP5CKx1l0WESQ$
>>>
>>> +$schema:
>>> https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y63E-9qbCW_vyn8RrsCCs7YvZ7NxKqFT7l8C0ZZirEW95Ec0ce3lwegsSq51wrjtz8GjVSpkK-omCBP5CKzzr9p82Q$
>>>
>>> +
>>> +title: MediaTek System Control Processor System
>>> +
>>> +maintainers:
>>> + - MandyJH Liu <mandyjh.liu@mediatek.com>
>>> +
>>> +description:
>>> + MediaTek System Control Processor System (SCPSYS) has several
>>> + power management tasks. The tasks include MTCMOS power
>>> + domain control, thermal measurement, DVFS, etc.
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - mediatek,mt8167-scpsys
>>> + - mediatek,mt8173-scpsys
>>> + - mediatek,mt8183-scpsys
>>> + - mediatek,mt8192-scpsys
>>> + - mediatek,mt8195-scpsys
>>> + - const: syscon
>>> + - const: simple-mfd
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> +patternProperties:
>>> + "^power-controller(@[0-9a-f]+)?$":
>>> + $ref: /schemas/power/mediatek,power-controller.yaml#
>>
>> We talked that unit address might be useful but it was with an
>> assumption that you will actually use it. I think you don't use it, so
>> it is kind of meaningless now... unless you plan to use it?
>
> I tried to add the offset in the node name, but the binding check reports this message.
>
> power-controller@0: node has a unit name, but no reg or ranges property
Why would you add unit address without reg? What point would it solve?
> After considering the fact of mt8195 power controller HW resides in scpsys and the current power
> domain driver doesn't support parsing the register address seperated from scpsys, I decide to
> keep the power controller node as in v2 to pass the binding check and compatible with driver.
Then adding unit addresses in bindings has no point.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
@ 2022-07-21 6:34 ` Krzysztof Kozlowski
0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-07-21 6:34 UTC (permalink / raw)
To: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Lee Jones, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu
Cc: iommu, linux-mediatek, devicetree, linux-kernel,
linux-arm-kernel, Project_Global_Chrome_Upstream_Group
On 21/07/2022 05:05, Tinghan Shen wrote:
> On Wed, 2022-07-20 at 19:35 +0200, Krzysztof Kozlowski wrote:
>> On 20/07/2022 14:30, Tinghan Shen wrote:
>>> The System Control Processor System (SCPSYS) has several power
>>> management related tasks in the system. Add the bindings for it.
>>>
>>> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
>>> ---
>>> .../bindings/mfd/mediatek,mt8195-scpsys.yaml | 68 +++++++++++++++++++
>>> 1 file changed, 68 insertions(+)
>>> create mode 100644 Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>>>
>>> diff --git a/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>>> b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>>> new file mode 100644
>>> index 000000000000..4117a6dbc19c
>>> --- /dev/null
>>> +++ b/Documentation/devicetree/bindings/mfd/mediatek,mt8195-scpsys.yaml
>>> @@ -0,0 +1,68 @@
>>> +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
>>> +%YAML 1.2
>>> +---
>>> +$id:
>>> https://urldefense.com/v3/__http://devicetree.org/schemas/mfd/mediatek,mt8195-scpsys.yaml*__;Iw!!CTRNKA9wMg0ARbw!y63E-9qbCW_vyn8RrsCCs7YvZ7NxKqFT7l8C0ZZirEW95Ec0ce3lwegsSq51wrjtz8GjVSpkK-omCBP5CKx1l0WESQ$
>>>
>>> +$schema:
>>> https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!y63E-9qbCW_vyn8RrsCCs7YvZ7NxKqFT7l8C0ZZirEW95Ec0ce3lwegsSq51wrjtz8GjVSpkK-omCBP5CKzzr9p82Q$
>>>
>>> +
>>> +title: MediaTek System Control Processor System
>>> +
>>> +maintainers:
>>> + - MandyJH Liu <mandyjh.liu@mediatek.com>
>>> +
>>> +description:
>>> + MediaTek System Control Processor System (SCPSYS) has several
>>> + power management tasks. The tasks include MTCMOS power
>>> + domain control, thermal measurement, DVFS, etc.
>>> +
>>> +properties:
>>> + compatible:
>>> + items:
>>> + - enum:
>>> + - mediatek,mt8167-scpsys
>>> + - mediatek,mt8173-scpsys
>>> + - mediatek,mt8183-scpsys
>>> + - mediatek,mt8192-scpsys
>>> + - mediatek,mt8195-scpsys
>>> + - const: syscon
>>> + - const: simple-mfd
>>> +
>>> + reg:
>>> + maxItems: 1
>>> +
>>> +patternProperties:
>>> + "^power-controller(@[0-9a-f]+)?$":
>>> + $ref: /schemas/power/mediatek,power-controller.yaml#
>>
>> We talked that unit address might be useful but it was with an
>> assumption that you will actually use it. I think you don't use it, so
>> it is kind of meaningless now... unless you plan to use it?
>
> I tried to add the offset in the node name, but the binding check reports this message.
>
> power-controller@0: node has a unit name, but no reg or ranges property
Why would you add unit address without reg? What point would it solve?
> After considering the fact of mt8195 power controller HW resides in scpsys and the current power
> domain driver doesn't support parsing the register address seperated from scpsys, I decide to
> keep the power controller node as in v2 to pass the binding check and compatible with driver.
Then adding unit addresses in bindings has no point.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
2022-07-20 17:37 ` Krzysztof Kozlowski
@ 2022-07-21 11:36 ` Lee Jones
-1 siblings, 0 replies; 70+ messages in thread
From: Lee Jones @ 2022-07-21 11:36 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu, iommu, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On Wed, 20 Jul 2022, Krzysztof Kozlowski wrote:
> On 20/07/2022 15:31, Lee Jones wrote:
> > On Wed, 20 Jul 2022, Tinghan Shen wrote:
> >
> >> The System Control Processor System (SCPSYS) has several power
> >> management related tasks in the system. Add the bindings for it.
> >>
> >> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> >
> > Why have you ignored my review comments from v2?
>
> If you refer whether the binding is needed at all, then the answer is
> yes, because this is not simple syscons but a device with children,
> which we want to parse/match.
This part is fine.
> Anyway Tinghan should respond to you about way how he proceeds...
This would be nice, yes.
I was referring to the submit line, which nearly made me miss it, again.
--
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS
@ 2022-07-21 11:36 ` Lee Jones
0 siblings, 0 replies; 70+ messages in thread
From: Lee Jones @ 2022-07-21 11:36 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Tinghan Shen, Yong Wu, Joerg Roedel, Will Deacon, Robin Murphy,
Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
AngeloGioacchino Del Regno, MandyJH Liu, iommu, linux-mediatek,
devicetree, linux-kernel, linux-arm-kernel,
Project_Global_Chrome_Upstream_Group
On Wed, 20 Jul 2022, Krzysztof Kozlowski wrote:
> On 20/07/2022 15:31, Lee Jones wrote:
> > On Wed, 20 Jul 2022, Tinghan Shen wrote:
> >
> >> The System Control Processor System (SCPSYS) has several power
> >> management related tasks in the system. Add the bindings for it.
> >>
> >> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> >
> > Why have you ignored my review comments from v2?
>
> If you refer whether the binding is needed at all, then the answer is
> yes, because this is not simple syscons but a device with children,
> which we want to parse/match.
This part is fine.
> Anyway Tinghan should respond to you about way how he proceeds...
This would be nice, yes.
I was referring to the submit line, which nearly made me miss it, again.
--
Lee Jones [李琼斯]
Principal Technical Lead - Developer Services
Linaro.org │ Open source software for Arm SoCs
Follow Linaro: Facebook | Twitter | Blog
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 05/21] dt-bindings: power: mediatek: Update maintainer list
2022-07-20 12:30 ` Tinghan Shen
@ 2022-07-25 22:24 ` Rob Herring
-1 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2022-07-25 22:24 UTC (permalink / raw)
To: Tinghan Shen
Cc: Will Deacon, Robin Murphy, Krzysztof Kozlowski, linux-kernel,
linux-arm-kernel, AngeloGioacchino Del Regno, devicetree,
Yong Wu, Matthias Brugger, Joerg Roedel, Lee Jones, MandyJH Liu,
Rob Herring, Project_Global_Chrome_Upstream_Group,
linux-mediatek, iommu
On Wed, 20 Jul 2022 20:30:07 +0800, Tinghan Shen wrote:
> Update the maintainer list of power controller binding.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> .../devicetree/bindings/power/mediatek,power-controller.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
^ permalink raw reply [flat|nested] 70+ messages in thread
* Re: [PATCH v3 05/21] dt-bindings: power: mediatek: Update maintainer list
@ 2022-07-25 22:24 ` Rob Herring
0 siblings, 0 replies; 70+ messages in thread
From: Rob Herring @ 2022-07-25 22:24 UTC (permalink / raw)
To: Tinghan Shen
Cc: Will Deacon, Robin Murphy, Krzysztof Kozlowski, linux-kernel,
linux-arm-kernel, AngeloGioacchino Del Regno, devicetree,
Yong Wu, Matthias Brugger, Joerg Roedel, Lee Jones, MandyJH Liu,
Rob Herring, Project_Global_Chrome_Upstream_Group,
linux-mediatek, iommu
On Wed, 20 Jul 2022 20:30:07 +0800, Tinghan Shen wrote:
> Update the maintainer list of power controller binding.
>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> .../devicetree/bindings/power/mediatek,power-controller.yaml | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
Acked-by: Rob Herring <robh@kernel.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 70+ messages in thread
end of thread, other threads:[~2022-07-25 22:25 UTC | newest]
Thread overview: 70+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-07-20 12:30 [PATCH v3 00/21] Add driver nodes for MT8195 SoC Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 01/21] dt-bindings: iommu: mediatek: Increase max interrupt number Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 17:30 ` Krzysztof Kozlowski
2022-07-20 17:30 ` Krzysztof Kozlowski
2022-07-20 12:30 ` [PATCH v3 02/21] dt-bindings: memory: mediatek: Update condition for mt8195 smi node Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 03/21] dt-bindings: power: mediatek: Refine multiple level power domain nodes Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 17:32 ` Krzysztof Kozlowski
2022-07-20 17:32 ` Krzysztof Kozlowski
2022-07-20 12:30 ` [PATCH v3 04/21] dt-bindings: power: mediatek: Support naming power controller node with unit address Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 17:32 ` Krzysztof Kozlowski
2022-07-20 17:32 ` Krzysztof Kozlowski
2022-07-20 12:30 ` [PATCH v3 05/21] dt-bindings: power: mediatek: Update maintainer list Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-25 22:24 ` Rob Herring
2022-07-25 22:24 ` Rob Herring
2022-07-20 12:30 ` [PATCH v3 06/21] dt-bindings: power: mediatek: Add bindings for MediaTek SCPSYS Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 13:31 ` Lee Jones
2022-07-20 13:31 ` Lee Jones
2022-07-20 17:37 ` Krzysztof Kozlowski
2022-07-20 17:37 ` Krzysztof Kozlowski
2022-07-21 2:35 ` Tinghan Shen
2022-07-21 2:35 ` Tinghan Shen
2022-07-21 11:36 ` Lee Jones
2022-07-21 11:36 ` Lee Jones
2022-07-20 17:35 ` Krzysztof Kozlowski
2022-07-20 17:35 ` Krzysztof Kozlowski
2022-07-21 3:05 ` Tinghan Shen
2022-07-21 3:05 ` Tinghan Shen
2022-07-21 6:34 ` Krzysztof Kozlowski
2022-07-21 6:34 ` Krzysztof Kozlowski
2022-07-20 12:30 ` [PATCH v3 07/21] dt-bindings: power: mediatek: Update example in dt-bindings Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 17:38 ` Krzysztof Kozlowski
2022-07-20 17:38 ` Krzysztof Kozlowski
2022-07-20 12:30 ` [PATCH v3 08/21] arm64: dts: mediatek: Update mt81xx scpsys node to align with dt-bindings Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 17:39 ` Krzysztof Kozlowski
2022-07-20 17:39 ` Krzysztof Kozlowski
2022-07-20 12:30 ` [PATCH v3 09/21] arm64: dts: mt8195: Disable watchdog external reset signal Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 10/21] arm64: dts: mt8195: Disable I2C0 node Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 11/21] arm64: dts: mt8195: Add cpufreq node Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 12/21] arm64: dts: mt8195: Add vdosys and vppsys clock nodes Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 13/21] arm64: dts: mt8195: Add power domains controller Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 14/21] arm64: dts: mt8195: Add spmi node Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 15/21] arm64: dts: mt8195: Add scp node Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 16/21] arm64: dts: mt8195: Add audio related nodes Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 17/21] arm64: dts: mt8195: Add adsp node and adsp mailbox nodes Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 18/21] arm64: dts: mt8195: Specify audio reset controller Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 19/21] arm64: dts: mt8195: Add iommu and smi nodes Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 20/21] arm64: dts: mt8195: Add gce node Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
2022-07-20 12:30 ` [PATCH v3 21/21] arm64: dts: mt8195: Add display node for vdosys0 Tinghan Shen
2022-07-20 12:30 ` Tinghan Shen
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