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[88.21.103.182]) by smtp.gmail.com with ESMTPSA id d186sm7123008wmf.7.2019.11.25.07.00.39 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 25 Nov 2019 07:00:39 -0800 (PST) Subject: Re: [PATCH] mos6522: update counters when timer interrupts are off To: Laurent Vivier , qemu-devel@nongnu.org References: <20191125141414.5015-1-laurent@vivier.eu> <3c49973f-ef70-27ec-342a-de722a05e257@vivier.eu> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: <57edef14-04b0-03bc-ff7b-aa64a705e029@redhat.com> Date: Mon, 25 Nov 2019 16:00:38 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.1.1 MIME-Version: 1.0 In-Reply-To: <3c49973f-ef70-27ec-342a-de722a05e257@vivier.eu> Content-Language: en-US X-MC-Unique: DrAD3WkjNIu2PS76syyBfA-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 205.139.110.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-ppc@nongnu.org, Mark Cave-Ayland , Andrew Randrianasulu , David Gibson Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/25/19 3:56 PM, Laurent Vivier wrote: > Le 25/11/2019 =C3=A0 15:37, Philippe Mathieu-Daud=C3=A9 a =C3=A9crit=C2= =A0: >> On 11/25/19 3:14 PM, Laurent Vivier wrote: >>> Even if the interrupts are off, counters must be updated because >>> they are running anyway and kernel can try to read them >>> (it's the case with g3beige kernel). >>> >>> Reported-by: Andrew Randrianasulu >>> Signed-off-by: Laurent Vivier >>> --- >>> =C2=A0 hw/misc/mos6522.c | 8 ++++++-- >>> =C2=A0 1 file changed, 6 insertions(+), 2 deletions(-) >>> >>> diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c >>> index aa3bfe1afd..cecf0be59e 100644 >>> --- a/hw/misc/mos6522.c >>> +++ b/hw/misc/mos6522.c >>> @@ -113,6 +113,10 @@ static int64_t get_next_irq_time(MOS6522State *s, >>> MOS6522Timer *ti, >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 int64_t d, next_time; >>> =C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 unsigned int counter; >>> =20 >> >> Can you add a comment here such "Clock disabled. This is the longest >> time before expiration" or better? >> >> Reviewed-by: Philippe Mathieu-Daud=C3=A9 >> >>> +=C2=A0=C2=A0=C2=A0 if (ti->frequency =3D=3D 0) { >>> +=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0=C2=A0 return INT64_MAX; >>> +=C2=A0=C2=A0=C2=A0 } >>> + >=20 >=20 > In fact this is here for a deeper problem: >=20 > frequency is not correctly initialized on reset. >=20 > ti->frequency are initialized by cuda/pmu/mac_via after the parent reset > (mos6522) but the parent reset calls set_counter() that uses > ti->frequency to set the counters. The mos6522 reset initialize the > ti->frequency from s->frequency but s->frequency is never initialized. Ah, I see. "How machines behave after a soft reset" is something I'd like to get=20 tested more thoroughly (with Avocado eventually). > It was hidden before because the timers were not updated if the > interrupts are disabled, and now they are always updated. >=20 > I didn't want to add a such complicated comment in the code and I will > try to fix the problem later. Good :)