diff for duplicates of <5802c420636559ffd37095d2886f6964d9b55b11.1506683482.git.horms+renesas@verge.net.au>
diff --git a/a/1.txt b/N1/1.txt
index c2378d8..c02db75 100644
--- a/a/1.txt
+++ b/N1/1.txt
@@ -610,10 +610,10 @@ index 16358bf8d1db..5a31dfc0c316 100644
};
- /* Special CPG clocks */
-- cpg_clocks: cpg_clocks@e6150000 {
+- cpg_clocks: cpg_clocks at e6150000 {
- compatible = "renesas,r8a7790-cpg-clocks",
- "renesas,rcar-gen2-cpg-clocks";
-+ cpg: clock-controller@e6150000 {
++ cpg: clock-controller at e6150000 {
+ compatible = "renesas,r8a7790-cpg-mssr";
reg = <0 0xe6150000 0 0x1000>;
- clocks = <&extal_clk &usb_extal_clk>;
@@ -628,37 +628,37 @@ index 16358bf8d1db..5a31dfc0c316 100644
};
-
- /* Variable factor clocks */
-- sd2_clk: sd2@e6150078 {
+- sd2_clk: sd2 at e6150078 {
- compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
- reg = <0 0xe6150078 0 4>;
- clocks = <&pll1_div2_clk>;
- #clock-cells = <0>;
- };
-- sd3_clk: sd3@e615026c {
+- sd3_clk: sd3 at e615026c {
- compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
- reg = <0 0xe615026c 0 4>;
- clocks = <&pll1_div2_clk>;
- #clock-cells = <0>;
- };
-- mmc0_clk: mmc0@e6150240 {
+- mmc0_clk: mmc0 at e6150240 {
- compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
- reg = <0 0xe6150240 0 4>;
- clocks = <&pll1_div2_clk>;
- #clock-cells = <0>;
- };
-- mmc1_clk: mmc1@e6150244 {
+- mmc1_clk: mmc1 at e6150244 {
- compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
- reg = <0 0xe6150244 0 4>;
- clocks = <&pll1_div2_clk>;
- #clock-cells = <0>;
- };
-- ssp_clk: ssp@e6150248 {
+- ssp_clk: ssp at e6150248 {
- compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
- reg = <0 0xe6150248 0 4>;
- clocks = <&pll1_div2_clk>;
- #clock-cells = <0>;
- };
-- ssprs_clk: ssprs@e615024c {
+- ssprs_clk: ssprs at e615024c {
- compatible = "renesas,r8a7790-div6-clock", "renesas,cpg-div6-clock";
- reg = <0 0xe615024c 0 4>;
- clocks = <&pll1_div2_clk>;
@@ -801,7 +801,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- };
-
- /* Gate clocks */
-- mstp0_clks: mstp0_clks@e6150130 {
+- mstp0_clks: mstp0_clks at e6150130 {
- compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
- reg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;
- clocks = <&mp_clk>;
@@ -809,7 +809,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- clock-indices = <R8A7790_CLK_MSIOF0>;
- clock-output-names = "msiof0";
- };
-- mstp1_clks: mstp1_clks@e6150134 {
+- mstp1_clks: mstp1_clks at e6150134 {
- compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
- reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
- clocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,
@@ -832,7 +832,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- "fdp1-0", "tmu3", "tmu2", "cmt0", "tmu0",
- "vsp1-du1", "vsp1-du0", "vsp1-rt", "vsp1-sy";
- };
-- mstp2_clks: mstp2_clks@e6150138 {
+- mstp2_clks: mstp2_clks at e6150138 {
- compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
- reg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;
- clocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,
@@ -850,7 +850,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- "scifb1", "msiof1", "msiof3", "scifb2",
- "sys-dmac1", "sys-dmac0";
- };
-- mstp3_clks: mstp3_clks@e615013c {
+- mstp3_clks: mstp3_clks at e615013c {
- compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
- reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
- clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
@@ -870,7 +870,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- "iic0", "pciec", "iic1", "ssusb", "cmt1",
- "usbdmac0", "usbdmac1";
- };
-- mstp4_clks: mstp4_clks@e6150140 {
+- mstp4_clks: mstp4_clks at e6150140 {
- compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
- reg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;
- clocks = <&cp_clk>, <&zs_clk>;
@@ -878,7 +878,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- clock-indices = <R8A7790_CLK_IRQC R8A7790_CLK_INTC_SYS>;
- clock-output-names = "irqc", "intc-sys";
- };
-- mstp5_clks: mstp5_clks@e6150144 {
+- mstp5_clks: mstp5_clks at e6150144 {
- compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
- reg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;
- clocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,
@@ -892,7 +892,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- clock-output-names = "audmac0", "audmac1", "adsp_mod",
- "thermal", "pwm";
- };
-- mstp7_clks: mstp7_clks@e615014c {
+- mstp7_clks: mstp7_clks at e615014c {
- compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
- reg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;
- clocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,
@@ -909,7 +909,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- "ehci", "hsusb", "hscif1", "hscif0", "scif1",
- "scif0", "du2", "du1", "du0", "lvds1", "lvds0";
- };
-- mstp8_clks: mstp8_clks@e6150990 {
+- mstp8_clks: mstp8_clks at e6150990 {
- compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
- reg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;
- clocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,
@@ -926,7 +926,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- "mlb", "vin3", "vin2", "vin1", "vin0",
- "etheravb", "ether", "sata1", "sata0";
- };
-- mstp9_clks: mstp9_clks@e6150994 {
+- mstp9_clks: mstp9_clks at e6150994 {
- compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
- reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
- clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,
@@ -945,7 +945,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- "rcan1", "rcan0", "qspi_mod", "iic3",
- "i2c3", "i2c2", "i2c1", "i2c0";
- };
-- mstp10_clks: mstp10_clks@e6150998 {
+- mstp10_clks: mstp10_clks at e6150998 {
- compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
- reg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;
- clocks = <&p_clk>,
@@ -986,7 +986,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
- };
};
- prr: chipid@ff000044 {
+ prr: chipid at ff000044 {
@@ -1518,7 +1154,7 @@
compatible = "renesas,qspi-r8a7790", "renesas,qspi";
reg = <0 0xe6b10000 0 0x2c>;
@@ -1060,7 +1060,7 @@ index 16358bf8d1db..5a31dfc0c316 100644
status = "disabled";
@@ -1657,7 +1293,7 @@
- pci2: pci@ee0d0000 {
+ pci2: pci at ee0d0000 {
compatible = "renesas,pci-r8a7790", "renesas,pci-rcar-gen2";
device_type = "pci";
- clocks = <&mstp7_clks R8A7790_CLK_EHCI>;
diff --git a/a/content_digest b/N1/content_digest
index db0fd15..8d64999 100644
--- a/a/content_digest
+++ b/N1/content_digest
@@ -2,7 +2,7 @@
"ref\0cover.1506683482.git.horms+renesas\@verge.net.au\0"
]
[
- "From\0Simon Horman <horms+renesas\@verge.net.au>\0"
+ "From\0horms+renesas\@verge.net.au (Simon Horman)\0"
]
[
"Subject\0[PATCH 01/48] ARM: dts: r8a7790: Convert to new CPG/MSSR bindings\0"
@@ -11,13 +11,7 @@
"Date\0Fri, 29 Sep 2017 13:52:53 +0200\0"
]
[
- "To\0linux-renesas-soc\@vger.kernel.org\0"
-]
-[
- "Cc\0linux-arm-kernel\@lists.infradead.org",
- " Magnus Damm <magnus.damm\@gmail.com>",
- " Geert Uytterhoeven <geert+renesas\@glider.be>",
- " Simon Horman <horms+renesas\@verge.net.au>\0"
+ "To\0linux-arm-kernel\@lists.infradead.org\0"
]
[
"\0000:1\0"
@@ -638,10 +632,10 @@
" \t\t};\n",
" \n",
"-\t\t/* Special CPG clocks */\n",
- "-\t\tcpg_clocks: cpg_clocks\@e6150000 {\n",
+ "-\t\tcpg_clocks: cpg_clocks at e6150000 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-cpg-clocks\",\n",
"-\t\t\t\t \"renesas,rcar-gen2-cpg-clocks\";\n",
- "+\t\tcpg: clock-controller\@e6150000 {\n",
+ "+\t\tcpg: clock-controller at e6150000 {\n",
"+\t\t\tcompatible = \"renesas,r8a7790-cpg-mssr\";\n",
" \t\t\treg = <0 0xe6150000 0 0x1000>;\n",
"-\t\t\tclocks = <&extal_clk &usb_extal_clk>;\n",
@@ -656,37 +650,37 @@
" \t\t};\n",
"-\n",
"-\t\t/* Variable factor clocks */\n",
- "-\t\tsd2_clk: sd2\@e6150078 {\n",
+ "-\t\tsd2_clk: sd2 at e6150078 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"-\t\t\treg = <0 0xe6150078 0 4>;\n",
"-\t\t\tclocks = <&pll1_div2_clk>;\n",
"-\t\t\t#clock-cells = <0>;\n",
"-\t\t};\n",
- "-\t\tsd3_clk: sd3\@e615026c {\n",
+ "-\t\tsd3_clk: sd3 at e615026c {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"-\t\t\treg = <0 0xe615026c 0 4>;\n",
"-\t\t\tclocks = <&pll1_div2_clk>;\n",
"-\t\t\t#clock-cells = <0>;\n",
"-\t\t};\n",
- "-\t\tmmc0_clk: mmc0\@e6150240 {\n",
+ "-\t\tmmc0_clk: mmc0 at e6150240 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"-\t\t\treg = <0 0xe6150240 0 4>;\n",
"-\t\t\tclocks = <&pll1_div2_clk>;\n",
"-\t\t\t#clock-cells = <0>;\n",
"-\t\t};\n",
- "-\t\tmmc1_clk: mmc1\@e6150244 {\n",
+ "-\t\tmmc1_clk: mmc1 at e6150244 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"-\t\t\treg = <0 0xe6150244 0 4>;\n",
"-\t\t\tclocks = <&pll1_div2_clk>;\n",
"-\t\t\t#clock-cells = <0>;\n",
"-\t\t};\n",
- "-\t\tssp_clk: ssp\@e6150248 {\n",
+ "-\t\tssp_clk: ssp at e6150248 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"-\t\t\treg = <0 0xe6150248 0 4>;\n",
"-\t\t\tclocks = <&pll1_div2_clk>;\n",
"-\t\t\t#clock-cells = <0>;\n",
"-\t\t};\n",
- "-\t\tssprs_clk: ssprs\@e615024c {\n",
+ "-\t\tssprs_clk: ssprs at e615024c {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-div6-clock\", \"renesas,cpg-div6-clock\";\n",
"-\t\t\treg = <0 0xe615024c 0 4>;\n",
"-\t\t\tclocks = <&pll1_div2_clk>;\n",
@@ -829,7 +823,7 @@
"-\t\t};\n",
"-\n",
"-\t\t/* Gate clocks */\n",
- "-\t\tmstp0_clks: mstp0_clks\@e6150130 {\n",
+ "-\t\tmstp0_clks: mstp0_clks at e6150130 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
"-\t\t\treg = <0 0xe6150130 0 4>, <0 0xe6150030 0 4>;\n",
"-\t\t\tclocks = <&mp_clk>;\n",
@@ -837,7 +831,7 @@
"-\t\t\tclock-indices = <R8A7790_CLK_MSIOF0>;\n",
"-\t\t\tclock-output-names = \"msiof0\";\n",
"-\t\t};\n",
- "-\t\tmstp1_clks: mstp1_clks\@e6150134 {\n",
+ "-\t\tmstp1_clks: mstp1_clks at e6150134 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
"-\t\t\treg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;\n",
"-\t\t\tclocks = <&zs_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>, <&m2_clk>,\n",
@@ -860,7 +854,7 @@
"-\t\t\t\t\"fdp1-0\", \"tmu3\", \"tmu2\", \"cmt0\", \"tmu0\",\n",
"-\t\t\t\t\"vsp1-du1\", \"vsp1-du0\", \"vsp1-rt\", \"vsp1-sy\";\n",
"-\t\t};\n",
- "-\t\tmstp2_clks: mstp2_clks\@e6150138 {\n",
+ "-\t\tmstp2_clks: mstp2_clks at e6150138 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
"-\t\t\treg = <0 0xe6150138 0 4>, <0 0xe6150040 0 4>;\n",
"-\t\t\tclocks = <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>, <&mp_clk>,\n",
@@ -878,7 +872,7 @@
"-\t\t\t\t\"scifb1\", \"msiof1\", \"msiof3\", \"scifb2\",\n",
"-\t\t\t\t\"sys-dmac1\", \"sys-dmac0\";\n",
"-\t\t};\n",
- "-\t\tmstp3_clks: mstp3_clks\@e615013c {\n",
+ "-\t\tmstp3_clks: mstp3_clks at e615013c {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
"-\t\t\treg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;\n",
"-\t\t\tclocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,\n",
@@ -898,7 +892,7 @@
"-\t\t\t\t\"iic0\", \"pciec\", \"iic1\", \"ssusb\", \"cmt1\",\n",
"-\t\t\t\t\"usbdmac0\", \"usbdmac1\";\n",
"-\t\t};\n",
- "-\t\tmstp4_clks: mstp4_clks\@e6150140 {\n",
+ "-\t\tmstp4_clks: mstp4_clks at e6150140 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
"-\t\t\treg = <0 0xe6150140 0 4>, <0 0xe615004c 0 4>;\n",
"-\t\t\tclocks = <&cp_clk>, <&zs_clk>;\n",
@@ -906,7 +900,7 @@
"-\t\t\tclock-indices = <R8A7790_CLK_IRQC R8A7790_CLK_INTC_SYS>;\n",
"-\t\t\tclock-output-names = \"irqc\", \"intc-sys\";\n",
"-\t\t};\n",
- "-\t\tmstp5_clks: mstp5_clks\@e6150144 {\n",
+ "-\t\tmstp5_clks: mstp5_clks at e6150144 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
"-\t\t\treg = <0 0xe6150144 0 4>, <0 0xe615003c 0 4>;\n",
"-\t\t\tclocks = <&hp_clk>, <&hp_clk>, <&cpg_clocks R8A7790_CLK_ADSP>,\n",
@@ -920,7 +914,7 @@
"-\t\t\tclock-output-names = \"audmac0\", \"audmac1\", \"adsp_mod\",\n",
"-\t\t\t\t\t \"thermal\", \"pwm\";\n",
"-\t\t};\n",
- "-\t\tmstp7_clks: mstp7_clks\@e615014c {\n",
+ "-\t\tmstp7_clks: mstp7_clks at e615014c {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
"-\t\t\treg = <0 0xe615014c 0 4>, <0 0xe61501c4 0 4>;\n",
"-\t\t\tclocks = <&mp_clk>, <&hp_clk>, <&zs_clk>, <&zs_clk>, <&p_clk>,\n",
@@ -937,7 +931,7 @@
"-\t\t\t\t\"ehci\", \"hsusb\", \"hscif1\", \"hscif0\", \"scif1\",\n",
"-\t\t\t\t\"scif0\", \"du2\", \"du1\", \"du0\", \"lvds1\", \"lvds0\";\n",
"-\t\t};\n",
- "-\t\tmstp8_clks: mstp8_clks\@e6150990 {\n",
+ "-\t\tmstp8_clks: mstp8_clks at e6150990 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
"-\t\t\treg = <0 0xe6150990 0 4>, <0 0xe61509a0 0 4>;\n",
"-\t\t\tclocks = <&hp_clk>, <&zg_clk>, <&zg_clk>, <&zg_clk>,\n",
@@ -954,7 +948,7 @@
"-\t\t\t\t\"mlb\", \"vin3\", \"vin2\", \"vin1\", \"vin0\",\n",
"-\t\t\t\t\"etheravb\", \"ether\", \"sata1\", \"sata0\";\n",
"-\t\t};\n",
- "-\t\tmstp9_clks: mstp9_clks\@e6150994 {\n",
+ "-\t\tmstp9_clks: mstp9_clks at e6150994 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
"-\t\t\treg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;\n",
"-\t\t\tclocks = <&cp_clk>, <&cp_clk>, <&cp_clk>,\n",
@@ -973,7 +967,7 @@
"-\t\t\t\t\"rcan1\", \"rcan0\", \"qspi_mod\", \"iic3\",\n",
"-\t\t\t\t\"i2c3\", \"i2c2\", \"i2c1\", \"i2c0\";\n",
"-\t\t};\n",
- "-\t\tmstp10_clks: mstp10_clks\@e6150998 {\n",
+ "-\t\tmstp10_clks: mstp10_clks at e6150998 {\n",
"-\t\t\tcompatible = \"renesas,r8a7790-mstp-clocks\", \"renesas,cpg-mstp-clocks\";\n",
"-\t\t\treg = <0 0xe6150998 0 4>, <0 0xe61509a8 0 4>;\n",
"-\t\t\tclocks = <&p_clk>,\n",
@@ -1014,7 +1008,7 @@
"-\t\t};\n",
" \t};\n",
" \n",
- " \tprr: chipid\@ff000044 {\n",
+ " \tprr: chipid at ff000044 {\n",
"\@\@ -1518,7 +1154,7 \@\@\n",
" \t\tcompatible = \"renesas,qspi-r8a7790\", \"renesas,qspi\";\n",
" \t\treg = <0 0xe6b10000 0 0x2c>;\n",
@@ -1088,7 +1082,7 @@
" \t\tstatus = \"disabled\";\n",
" \n",
"\@\@ -1657,7 +1293,7 \@\@\n",
- " \tpci2: pci\@ee0d0000 {\n",
+ " \tpci2: pci at ee0d0000 {\n",
" \t\tcompatible = \"renesas,pci-r8a7790\", \"renesas,pci-rcar-gen2\";\n",
" \t\tdevice_type = \"pci\";\n",
"-\t\tclocks = <&mstp7_clks R8A7790_CLK_EHCI>;\n",
@@ -1147,4 +1141,4 @@
"2.1.4"
]
-89a10585af6035d4741240bfc2dbad6fd34f2561e6fc8529281ec11dac7268c8
+ca4cf3ac70ebca01f71475184367b6fd0d9053a691db4e8f4f3a320e72b0e884
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