From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:40172) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bw9k5-0006SV-PB for qemu-devel@nongnu.org; Mon, 17 Oct 2016 11:22:22 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bw9k1-0001k9-DJ for qemu-devel@nongnu.org; Mon, 17 Oct 2016 11:22:21 -0400 Received: from lhrrgout.huawei.com ([194.213.3.17]:4166) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1bw9k1-0001jG-5W for qemu-devel@nongnu.org; Mon, 17 Oct 2016 11:22:17 -0400 References: <1476589070-5792-1-git-send-email-rth@twiddle.net> <1476589070-5792-4-git-send-email-rth@twiddle.net> From: Claudio Fontana Message-ID: <5804ECA2.909@huawei.com> Date: Mon, 17 Oct 2016 17:22:10 +0200 MIME-Version: 1.0 In-Reply-To: <1476589070-5792-4-git-send-email-rth@twiddle.net> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 8bit Subject: Re: [Qemu-devel] [PATCH 03/15] tcg/aarch64: Implement field extraction opcodes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson , qemu-devel@nongnu.org On 16.10.2016 05:37, Richard Henderson wrote: > Cc: Claudio Fontana > Signed-off-by: Richard Henderson > --- > tcg/aarch64/tcg-target.h | 8 ++++---- > tcg/aarch64/tcg-target.inc.c | 14 ++++++++++++++ > 2 files changed, 18 insertions(+), 4 deletions(-) Reviewed-by: Claudio Fontana > > diff --git a/tcg/aarch64/tcg-target.h b/tcg/aarch64/tcg-target.h > index 410c31b..4a74bd8 100644 > --- a/tcg/aarch64/tcg-target.h > +++ b/tcg/aarch64/tcg-target.h > @@ -63,8 +63,8 @@ typedef enum { > #define TCG_TARGET_HAS_nand_i32 0 > #define TCG_TARGET_HAS_nor_i32 0 > #define TCG_TARGET_HAS_deposit_i32 1 > -#define TCG_TARGET_HAS_extract_i32 0 > -#define TCG_TARGET_HAS_sextract_i32 0 > +#define TCG_TARGET_HAS_extract_i32 1 > +#define TCG_TARGET_HAS_sextract_i32 1 > #define TCG_TARGET_HAS_movcond_i32 1 > #define TCG_TARGET_HAS_add2_i32 1 > #define TCG_TARGET_HAS_sub2_i32 1 > @@ -95,8 +95,8 @@ typedef enum { > #define TCG_TARGET_HAS_nand_i64 0 > #define TCG_TARGET_HAS_nor_i64 0 > #define TCG_TARGET_HAS_deposit_i64 1 > -#define TCG_TARGET_HAS_extract_i64 0 > -#define TCG_TARGET_HAS_sextract_i64 0 > +#define TCG_TARGET_HAS_extract_i64 1 > +#define TCG_TARGET_HAS_sextract_i64 1 > #define TCG_TARGET_HAS_movcond_i64 1 > #define TCG_TARGET_HAS_add2_i64 1 > #define TCG_TARGET_HAS_sub2_i64 1 > diff --git a/tcg/aarch64/tcg-target.inc.c b/tcg/aarch64/tcg-target.inc.c > index 1939d35..a496b3b 100644 > --- a/tcg/aarch64/tcg-target.inc.c > +++ b/tcg/aarch64/tcg-target.inc.c > @@ -1640,6 +1640,16 @@ static void tcg_out_op(TCGContext *s, TCGOpcode opc, > tcg_out_dep(s, ext, a0, REG0(2), args[3], args[4]); > break; > > + case INDEX_op_extract_i64: > + case INDEX_op_extract_i32: > + tcg_out_ubfm(s, ext, a0, a1, a2, args[3]); > + break; > + > + case INDEX_op_sextract_i64: > + case INDEX_op_sextract_i32: > + tcg_out_sbfm(s, ext, a0, a1, a2, args[3]); > + break; > + > case INDEX_op_add2_i32: > tcg_out_addsub2(s, TCG_TYPE_I32, a0, a1, REG0(2), REG0(3), > (int32_t)args[4], args[5], const_args[4], > @@ -1785,6 +1795,10 @@ static const TCGTargetOpDef aarch64_op_defs[] = { > > { INDEX_op_deposit_i32, { "r", "0", "rZ" } }, > { INDEX_op_deposit_i64, { "r", "0", "rZ" } }, > + { INDEX_op_extract_i32, { "r", "r" } }, > + { INDEX_op_extract_i64, { "r", "r" } }, > + { INDEX_op_sextract_i32, { "r", "r" } }, > + { INDEX_op_sextract_i64, { "r", "r" } }, > > { INDEX_op_add2_i32, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, > { INDEX_op_add2_i64, { "r", "r", "rZ", "rZ", "rA", "rMZ" } }, > -- Claudio Fontana Server Virtualization Architect Huawei Technologies Duesseldorf GmbH Riesstraße 25 - 80992 München