From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 08/10] x86/vm-event: use unambiguous register names Date: Tue, 20 Dec 2016 03:42:19 -0700 Message-ID: <5859191B020000780012AE08@prv-mh.provo.novell.com> References: <58590E27020000780012AD5E@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__Part7940751B.3__=" Return-path: Received: from mail6.bemta6.messagelabs.com ([193.109.254.103]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cJHsP-0001lz-HB for xen-devel@lists.xenproject.org; Tue, 20 Dec 2016 10:42:33 +0000 In-Reply-To: <58590E27020000780012AD5E@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel Cc: George Dunlap , Andrew Cooper , tamas@tklengyel.com, Razvan Cojocaru List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__Part7940751B.3__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline This is in preparation of eliminating the mis-naming of 64-bit fields with 32-bit register names (eflags instead of rflags etc). Signed-off-by: Jan Beulich --- a/xen/arch/x86/vm_event.c +++ b/xen/arch/x86/vm_event.c @@ -112,14 +112,14 @@ void vm_event_set_registers(struct vcpu { ASSERT(atomic_read(&v->vm_event_pause_count)); =20 - v->arch.user_regs.eax =3D rsp->data.regs.x86.rax; - v->arch.user_regs.ebx =3D rsp->data.regs.x86.rbx; - v->arch.user_regs.ecx =3D rsp->data.regs.x86.rcx; - v->arch.user_regs.edx =3D rsp->data.regs.x86.rdx; - v->arch.user_regs.esp =3D rsp->data.regs.x86.rsp; - v->arch.user_regs.ebp =3D rsp->data.regs.x86.rbp; - v->arch.user_regs.esi =3D rsp->data.regs.x86.rsi; - v->arch.user_regs.edi =3D rsp->data.regs.x86.rdi; + v->arch.user_regs.rax =3D rsp->data.regs.x86.rax; + v->arch.user_regs.rbx =3D rsp->data.regs.x86.rbx; + v->arch.user_regs.rcx =3D rsp->data.regs.x86.rcx; + v->arch.user_regs.rdx =3D rsp->data.regs.x86.rdx; + v->arch.user_regs.rsp =3D rsp->data.regs.x86.rsp; + v->arch.user_regs.rbp =3D rsp->data.regs.x86.rbp; + v->arch.user_regs.rsi =3D rsp->data.regs.x86.rsi; + v->arch.user_regs.rdi =3D rsp->data.regs.x86.rdi; =20 v->arch.user_regs.r8 =3D rsp->data.regs.x86.r8; v->arch.user_regs.r9 =3D rsp->data.regs.x86.r9; @@ -130,8 +130,8 @@ void vm_event_set_registers(struct vcpu v->arch.user_regs.r14 =3D rsp->data.regs.x86.r14; v->arch.user_regs.r15 =3D rsp->data.regs.x86.r15; =20 - v->arch.user_regs.eflags =3D rsp->data.regs.x86.rflags; - v->arch.user_regs.eip =3D rsp->data.regs.x86.rip; + v->arch.user_regs.rflags =3D rsp->data.regs.x86.rflags; + v->arch.user_regs.rip =3D rsp->data.regs.x86.rip; } =20 void vm_event_monitor_next_interrupt(struct vcpu *v) @@ -151,14 +151,14 @@ void vm_event_fill_regs(vm_event_request /* Architecture-specific vmcs/vmcb bits */ hvm_funcs.save_cpu_ctxt(curr, &ctxt); =20 - req->data.regs.x86.rax =3D regs->eax; - req->data.regs.x86.rcx =3D regs->ecx; - req->data.regs.x86.rdx =3D regs->edx; - req->data.regs.x86.rbx =3D regs->ebx; - req->data.regs.x86.rsp =3D regs->esp; - req->data.regs.x86.rbp =3D regs->ebp; - req->data.regs.x86.rsi =3D regs->esi; - req->data.regs.x86.rdi =3D regs->edi; + req->data.regs.x86.rax =3D regs->rax; + req->data.regs.x86.rcx =3D regs->rcx; + req->data.regs.x86.rdx =3D regs->rdx; + req->data.regs.x86.rbx =3D regs->rbx; + req->data.regs.x86.rsp =3D regs->rsp; + req->data.regs.x86.rbp =3D regs->rbp; + req->data.regs.x86.rsi =3D regs->rsi; + req->data.regs.x86.rdi =3D regs->rdi; =20 req->data.regs.x86.r8 =3D regs->r8; req->data.regs.x86.r9 =3D regs->r9; @@ -169,8 +169,8 @@ void vm_event_fill_regs(vm_event_request req->data.regs.x86.r14 =3D regs->r14; req->data.regs.x86.r15 =3D regs->r15; =20 - req->data.regs.x86.rflags =3D regs->eflags; - req->data.regs.x86.rip =3D regs->eip; + req->data.regs.x86.rflags =3D regs->rflags; + req->data.regs.x86.rip =3D regs->rip; =20 req->data.regs.x86.dr7 =3D curr->arch.debugreg[7]; req->data.regs.x86.cr0 =3D ctxt.cr0; --=__Part7940751B.3__= Content-Type: text/plain; name="x86-regnames-vmevt.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86-regnames-vmevt.patch" x86/vm-event: use unambiguous register names=0A=0AThis is in preparation = of eliminating the mis-naming of 64-bit fields=0Awith 32-bit register = names (eflags instead of rflags etc).=0A=0ASigned-off-by: Jan Beulich = =0A=0A--- a/xen/arch/x86/vm_event.c=0A+++ b/xen/arch/x86= /vm_event.c=0A@@ -112,14 +112,14 @@ void vm_event_set_registers(struct = vcpu=0A {=0A ASSERT(atomic_read(&v->vm_event_pause_count));=0A =0A- = v->arch.user_regs.eax =3D rsp->data.regs.x86.rax;=0A- v->arch.user_regs.= ebx =3D rsp->data.regs.x86.rbx;=0A- v->arch.user_regs.ecx =3D rsp->data.= regs.x86.rcx;=0A- v->arch.user_regs.edx =3D rsp->data.regs.x86.rdx;=0A- = v->arch.user_regs.esp =3D rsp->data.regs.x86.rsp;=0A- v->arch.user_re= gs.ebp =3D rsp->data.regs.x86.rbp;=0A- v->arch.user_regs.esi =3D = rsp->data.regs.x86.rsi;=0A- v->arch.user_regs.edi =3D rsp->data.regs.x86= .rdi;=0A+ v->arch.user_regs.rax =3D rsp->data.regs.x86.rax;=0A+ = v->arch.user_regs.rbx =3D rsp->data.regs.x86.rbx;=0A+ v->arch.user_regs.= rcx =3D rsp->data.regs.x86.rcx;=0A+ v->arch.user_regs.rdx =3D rsp->data.= regs.x86.rdx;=0A+ v->arch.user_regs.rsp =3D rsp->data.regs.x86.rsp;=0A+ = v->arch.user_regs.rbp =3D rsp->data.regs.x86.rbp;=0A+ v->arch.user_re= gs.rsi =3D rsp->data.regs.x86.rsi;=0A+ v->arch.user_regs.rdi =3D = rsp->data.regs.x86.rdi;=0A =0A v->arch.user_regs.r8 =3D rsp->data.regs.= x86.r8;=0A v->arch.user_regs.r9 =3D rsp->data.regs.x86.r9;=0A@@ -130,8 = +130,8 @@ void vm_event_set_registers(struct vcpu=0A v->arch.user_regs.= r14 =3D rsp->data.regs.x86.r14;=0A v->arch.user_regs.r15 =3D rsp->data.= regs.x86.r15;=0A =0A- v->arch.user_regs.eflags =3D rsp->data.regs.x86.rf= lags;=0A- v->arch.user_regs.eip =3D rsp->data.regs.x86.rip;=0A+ = v->arch.user_regs.rflags =3D rsp->data.regs.x86.rflags;=0A+ v->arch.user= _regs.rip =3D rsp->data.regs.x86.rip;=0A }=0A =0A void vm_event_monitor_nex= t_interrupt(struct vcpu *v)=0A@@ -151,14 +151,14 @@ void vm_event_fill_regs= (vm_event_request=0A /* Architecture-specific vmcs/vmcb bits */=0A = hvm_funcs.save_cpu_ctxt(curr, &ctxt);=0A =0A- req->data.regs.x86.rax = =3D regs->eax;=0A- req->data.regs.x86.rcx =3D regs->ecx;=0A- = req->data.regs.x86.rdx =3D regs->edx;=0A- req->data.regs.x86.rbx =3D = regs->ebx;=0A- req->data.regs.x86.rsp =3D regs->esp;=0A- req->data.re= gs.x86.rbp =3D regs->ebp;=0A- req->data.regs.x86.rsi =3D regs->esi;=0A- = req->data.regs.x86.rdi =3D regs->edi;=0A+ req->data.regs.x86.rax =3D = regs->rax;=0A+ req->data.regs.x86.rcx =3D regs->rcx;=0A+ req->data.re= gs.x86.rdx =3D regs->rdx;=0A+ req->data.regs.x86.rbx =3D regs->rbx;=0A+ = req->data.regs.x86.rsp =3D regs->rsp;=0A+ req->data.regs.x86.rbp =3D = regs->rbp;=0A+ req->data.regs.x86.rsi =3D regs->rsi;=0A+ req->data.re= gs.x86.rdi =3D regs->rdi;=0A =0A req->data.regs.x86.r8 =3D = regs->r8;=0A req->data.regs.x86.r9 =3D regs->r9;=0A@@ -169,8 +169,8 = @@ void vm_event_fill_regs(vm_event_request=0A req->data.regs.x86.r14 = =3D regs->r14;=0A req->data.regs.x86.r15 =3D regs->r15;=0A =0A- = req->data.regs.x86.rflags =3D regs->eflags;=0A- req->data.regs.x86.rip = =3D regs->eip;=0A+ req->data.regs.x86.rflags =3D regs->rflags;=0A+ = req->data.regs.x86.rip =3D regs->rip;=0A =0A req->data.regs.x86.dr7 = =3D curr->arch.debugreg[7];=0A req->data.regs.x86.cr0 =3D ctxt.cr0;=0A --=__Part7940751B.3__= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwczovL2xpc3RzLnhlbi5v cmcveGVuLWRldmVsCg== --=__Part7940751B.3__=--