From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751188AbdAVDG6 (ORCPT ); Sat, 21 Jan 2017 22:06:58 -0500 Received: from regular1.263xmail.com ([211.150.99.138]:60852 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750907AbdAVDGu (ORCPT ); Sat, 21 Jan 2017 22:06:50 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 103.29.142.67 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: <286e2b398c91fac9315d15c068f1dc40> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v2 18/26] drm/rockchip: dw-mipi-dsi: properly configure PHY timing To: John Keeping , Mark Yao References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-19-john@metanate.com> Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org From: Chris Zhong Message-ID: <588421B7.4000900@rock-chips.com> Date: Sun, 22 Jan 2017 11:06:31 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20170121163128.22240-19-john@metanate.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On 01/22/2017 12:31 AM, John Keeping wrote: > These values are specified as constant time periods but the PHY > configuration is in terms of the current lane byte clock so using > constant values guarantees that the timings will be outside the > specification with some display configurations. > > Derive the necessary configuration from the byte clock in order to > ensure that the PHY configuration is correct. > > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 36 ++++++++++++++++++++++++++++++---- > 1 file changed, 32 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index cfe7e4ba305c..12432e41971b 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -383,6 +383,26 @@ static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code, > dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); > } > > +/** > + * ns2bc - Nanoseconds to byte clock cycles > + */ > +static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns) > +{ > + unsigned long byte_clk_khz = dsi->lane_mbps * MSEC_PER_SEC / 8; > + > + return (ns * (byte_clk_khz / 1000) + 999) / 1000; > +} > + > +/** > + * ns2ui - Nanoseconds to UI time periods > + */ > +static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns) > +{ > + unsigned long byte_clk_khz = dsi->lane_mbps * MSEC_PER_SEC; > + > + return (ns * (byte_clk_khz / 1000) + 999) / 1000; > +} > + > static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > { > int ret, testdin, vco, val; > @@ -434,10 +454,18 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > SETRD_MAX | POWER_MANAGE | > TER_RESISTORS_ON); > > - > - dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); > - dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55); > - dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa); > + dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500)); > + dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); > + dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); > + dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); > + dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100)); > + dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7)); > + > + dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500)); > + dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5)); WARNING: line over 80 characters > + dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); WARNING: line over 80 characters > + dw_mipi_dsi_phy_write(dsi, 0x73, THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); WARNING: line over 80 characters > + dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100)); > > dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | > PHY_UNRSTZ | PHY_UNSHUTDOWNZ); From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Zhong Subject: Re: [PATCH v2 18/26] drm/rockchip: dw-mipi-dsi: properly configure PHY timing Date: Sun, 22 Jan 2017 11:06:31 +0800 Message-ID: <588421B7.4000900@rock-chips.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-19-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170121163128.22240-19-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: John Keeping , Mark Yao Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org List-Id: linux-rockchip.vger.kernel.org CgpPbiAwMS8yMi8yMDE3IDEyOjMxIEFNLCBKb2huIEtlZXBpbmcgd3JvdGU6Cj4gVGhlc2UgdmFs dWVzIGFyZSBzcGVjaWZpZWQgYXMgY29uc3RhbnQgdGltZSBwZXJpb2RzIGJ1dCB0aGUgUEhZCj4g Y29uZmlndXJhdGlvbiBpcyBpbiB0ZXJtcyBvZiB0aGUgY3VycmVudCBsYW5lIGJ5dGUgY2xvY2sg c28gdXNpbmcKPiBjb25zdGFudCB2YWx1ZXMgZ3VhcmFudGVlcyB0aGF0IHRoZSB0aW1pbmdzIHdp bGwgYmUgb3V0c2lkZSB0aGUKPiBzcGVjaWZpY2F0aW9uIHdpdGggc29tZSBkaXNwbGF5IGNvbmZp Z3VyYXRpb25zLgo+Cj4gRGVyaXZlIHRoZSBuZWNlc3NhcnkgY29uZmlndXJhdGlvbiBmcm9tIHRo ZSBieXRlIGNsb2NrIGluIG9yZGVyIHRvCj4gZW5zdXJlIHRoYXQgdGhlIFBIWSBjb25maWd1cmF0 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timing In-Reply-To: <20170121163128.22240-19-john@metanate.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-19-john@metanate.com> Message-ID: <588421B7.4000900@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On 01/22/2017 12:31 AM, John Keeping wrote: > These values are specified as constant time periods but the PHY > configuration is in terms of the current lane byte clock so using > constant values guarantees that the timings will be outside the > specification with some display configurations. > > Derive the necessary configuration from the byte clock in order to > ensure that the PHY configuration is correct. > > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 36 ++++++++++++++++++++++++++++++---- > 1 file changed, 32 insertions(+), 4 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index cfe7e4ba305c..12432e41971b 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -383,6 +383,26 @@ static void dw_mipi_dsi_phy_write(struct dw_mipi_dsi *dsi, u8 test_code, > dsi_write(dsi, DSI_PHY_TST_CTRL0, PHY_TESTCLK | PHY_UNTESTCLR); > } > > +/** > + * ns2bc - Nanoseconds to byte clock cycles > + */ > +static inline unsigned int ns2bc(struct dw_mipi_dsi *dsi, int ns) > +{ > + unsigned long byte_clk_khz = dsi->lane_mbps * MSEC_PER_SEC / 8; > + > + return (ns * (byte_clk_khz / 1000) + 999) / 1000; > +} > + > +/** > + * ns2ui - Nanoseconds to UI time periods > + */ > +static inline unsigned int ns2ui(struct dw_mipi_dsi *dsi, int ns) > +{ > + unsigned long byte_clk_khz = dsi->lane_mbps * MSEC_PER_SEC; > + > + return (ns * (byte_clk_khz / 1000) + 999) / 1000; > +} > + > static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > { > int ret, testdin, vco, val; > @@ -434,10 +454,18 @@ static int dw_mipi_dsi_phy_init(struct dw_mipi_dsi *dsi) > SETRD_MAX | POWER_MANAGE | > TER_RESISTORS_ON); > > - > - dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | 0xf); > - dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | 0x55); > - dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | 0xa); > + dw_mipi_dsi_phy_write(dsi, 0x60, TLP_PROGRAM_EN | ns2bc(dsi, 500)); > + dw_mipi_dsi_phy_write(dsi, 0x61, THS_PRE_PROGRAM_EN | ns2ui(dsi, 40)); > + dw_mipi_dsi_phy_write(dsi, 0x62, THS_ZERO_PROGRAM_EN | ns2bc(dsi, 300)); > + dw_mipi_dsi_phy_write(dsi, 0x63, THS_PRE_PROGRAM_EN | ns2ui(dsi, 100)); > + dw_mipi_dsi_phy_write(dsi, 0x64, BIT(5) | ns2bc(dsi, 100)); > + dw_mipi_dsi_phy_write(dsi, 0x65, BIT(5) | (ns2bc(dsi, 60) + 7)); > + > + dw_mipi_dsi_phy_write(dsi, 0x70, TLP_PROGRAM_EN | ns2bc(dsi, 500)); > + dw_mipi_dsi_phy_write(dsi, 0x71, THS_PRE_PROGRAM_EN | (ns2ui(dsi, 50) + 5)); WARNING: line over 80 characters > + dw_mipi_dsi_phy_write(dsi, 0x72, THS_ZERO_PROGRAM_EN | (ns2bc(dsi, 140) + 2)); WARNING: line over 80 characters > + dw_mipi_dsi_phy_write(dsi, 0x73, THS_PRE_PROGRAM_EN | (ns2ui(dsi, 60) + 8)); WARNING: line over 80 characters > + dw_mipi_dsi_phy_write(dsi, 0x74, BIT(5) | ns2bc(dsi, 100)); > > dsi_write(dsi, DSI_PHY_RSTZ, PHY_ENFORCEPLL | PHY_ENABLECLK | > PHY_UNRSTZ | PHY_UNSHUTDOWNZ);