From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751292AbdAVGY3 (ORCPT ); Sun, 22 Jan 2017 01:24:29 -0500 Received: from regular1.263xmail.com ([211.150.99.130]:44246 "EHLO regular1.263xmail.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750886AbdAVGYW (ORCPT ); Sun, 22 Jan 2017 01:24:22 -0500 X-263anti-spam: KSV:0; X-MAIL-GRAY: 0 X-MAIL-DELIVERY: 1 X-KSVirus-check: 0 X-ABS-CHECKED: 4 X-RL-SENDER: zyw@rock-chips.com X-FST-TO: linux-kernel@vger.kernel.org X-SENDER-IP: 58.22.7.114 X-LOGIN-NAME: zyw@rock-chips.com X-UNIQUE-TAG: <767d7f06d3edea22f0c316f645271a5a> X-ATTACHMENT-NUM: 0 X-DNS-TYPE: 0 Subject: Re: [PATCH v2 06/26] drm/rockchip: dw-mipi-dsi: fix generic packet status check To: John Keeping , Mark Yao References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-7-john@metanate.com> Cc: dri-devel@lists.freedesktop.org, linux-arm-kernel@lists.infradead.org, linux-rockchip@lists.infradead.org, linux-kernel@vger.kernel.org From: Chris Zhong Message-ID: <5884500D.7070706@rock-chips.com> Date: Sun, 22 Jan 2017 14:24:13 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.4.0 MIME-Version: 1.0 In-Reply-To: <20170121163128.22240-7-john@metanate.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi John Reviewed-by: Chris Zhong On 01/22/2017 12:31 AM, John Keeping wrote: > We want to check that both the GEN_CMD_EMPTY and GEN_PLD_W_EMPTY bits > are set so we can't just check "val & mask" because that will be true if > either bit is set. According to DW mipi dsi controller databook, you are right. we should check both the 2 BIT. gen_pld_w_empty: This bit indicates the empty status of the generic write payload FIFO. Dependency : DSI_GENERIC = 1. Otherwise, this bit is reserved. Value after reset : 0x1 > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 4cbbbcb619b7..4be1ff3a42bb 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -545,7 +545,7 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, > static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) > { > int ret; > - u32 val; > + u32 val, mask; > > ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS, > val, !(val & GEN_CMD_FULL), 1000, > @@ -557,8 +557,9 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) > > dsi_write(dsi, DSI_GEN_HDR, hdr_val); > > + mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; > ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS, > - val, val & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY), > + val, (val & mask) == mask, > 1000, CMD_PKT_STATUS_TIMEOUT_US); > if (ret < 0) { > dev_err(dsi->dev, "failed to write command FIFO\n"); From mboxrd@z Thu Jan 1 00:00:00 1970 From: Chris Zhong Subject: Re: [PATCH v2 06/26] drm/rockchip: dw-mipi-dsi: fix generic packet status check Date: Sun, 22 Jan 2017 14:24:13 +0800 Message-ID: <5884500D.7070706@rock-chips.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-7-john@metanate.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8"; Format="flowed" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <20170121163128.22240-7-john@metanate.com> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: dri-devel-bounces@lists.freedesktop.org Sender: "dri-devel" To: John Keeping , Mark Yao Cc: linux-rockchip@lists.infradead.org, linux-arm-kernel@lists.infradead.org, dri-devel@lists.freedesktop.org, linux-kernel@vger.kernel.org List-Id: linux-rockchip.vger.kernel.org SGkgSm9obgoKUmV2aWV3ZWQtYnk6IENocmlzIFpob25nIDx6eXdAcm9jay1jaGlwcy5jb20+CgpP biAwMS8yMi8yMDE3IDEyOjMxIEFNLCBKb2huIEtlZXBpbmcgd3JvdGU6Cj4gV2Ugd2FudCB0byBj aGVjayB0aGF0IGJvdGggdGhlIEdFTl9DTURfRU1QVFkgYW5kIEdFTl9QTERfV19FTVBUWSBiaXRz Cj4gYXJlIHNldCBzbyB3ZSBjYW4ndCBqdXN0IGNoZWNrICJ2YWwgJiBtYXNrIiBiZWNhdXNlIHRo YXQgd2lsbCBiZSB0cnVlIGlmCj4gZWl0aGVyIGJpdCBpcyBzZXQuCkFjY29yZGluZyB0byBEVyBt aXBpIGRzaSBjb250cm9sbGVyIGRhdGFib29rLCB5b3UgYXJlIHJpZ2h0LiB3ZSBzaG91bGQgCmNo ZWNrIGJvdGggdGhlIDIgQklULgpnZW5fcGxkX3dfZW1wdHk6ClRoaXMgYml0IGluZGljYXRlcyB0 aGUgZW1wdHkgc3RhdHVzIG9mIHRoZSBnZW5lcmljIHdyaXRlIHBheWxvYWQgRklGTy4KRGVwZW5k ZW5jeSA6IERTSV9HRU5FUklDID0gMS4gT3RoZXJ3aXNlLCB0aGlzIGJpdCBpcyByZXNlcnZlZC4K VmFsdWUgYWZ0ZXIgcmVzZXQgOiAweDEKCj4gU2lnbmVkLW9mZi1ieTogSm9obiBLZWVwaW5nIDxq b2huQG1ldGFuYXRlLmNvbT4KPiAtLS0KPiBVbmNoYW5nZWQgaW4gdjIKPiAtLS0KPiAgIGRyaXZl cnMvZ3B1L2RybS9yb2NrY2hpcC9kdy1taXBpLWRzaS5jIHwgNSArKystLQo+ICAgMSBmaWxlIGNo YW5nZWQsIDMgaW5zZXJ0aW9ucygrKSwgMiBkZWxldGlvbnMoLSkKPgo+IGRpZmYgLS1naXQgYS9k cml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1kc2kuYyBiL2RyaXZlcnMvZ3B1L2RybS9y b2NrY2hpcC9kdy1taXBpLWRzaS5jCj4gaW5kZXggNGNiYmJjYjYxOWI3Li40YmUxZmYzYTQyYmIg MTAwNjQ0Cj4gLS0tIGEvZHJpdmVycy9ncHUvZHJtL3JvY2tjaGlwL2R3LW1pcGktZHNpLmMKPiAr KysgYi9kcml2ZXJzL2dwdS9kcm0vcm9ja2NoaXAvZHctbWlwaS1kc2kuYwo+IEBAIC01NDUsNyAr NTQ1LDcgQEAgc3RhdGljIGludCBkd19taXBpX2RzaV9ob3N0X2RldGFjaChzdHJ1Y3QgbWlwaV9k c2lfaG9zdCAqaG9zdCwKPiAgIHN0YXRpYyBpbnQgZHdfbWlwaV9kc2lfZ2VuX3BrdF9oZHJfd3Jp dGUoc3RydWN0IGR3X21pcGlfZHNpICpkc2ksIHUzMiBoZHJfdmFsKQo+ICAgewo+ICAgCWludCBy ZXQ7Cj4gLQl1MzIgdmFsOwo+ICsJdTMyIHZhbCwgbWFzazsKPiAgIAo+ICAgCXJldCA9IHJlYWR4 X3BvbGxfdGltZW91dChyZWFkbCwgZHNpLT5iYXNlICsgRFNJX0NNRF9QS1RfU1RBVFVTLAo+ICAg CQkJCSB2YWwsICEodmFsICYgR0VOX0NNRF9GVUxMKSwgMTAwMCwKPiBAQCAtNTU3LDggKzU1Nyw5 IEBAIHN0YXRpYyBpbnQgZHdfbWlwaV9kc2lfZ2VuX3BrdF9oZHJfd3JpdGUoc3RydWN0IGR3X21p cGlfZHNpICpkc2ksIHUzMiBoZHJfdmFsKQo+ICAgCj4gICAJZHNpX3dyaXRlKGRzaSwgRFNJX0dF Tl9IRFIsIGhkcl92YWwpOwo+ICAgCj4gKwltYXNrID0gR0VOX0NNRF9FTVBUWSB8IEdFTl9QTERf V19FTVBUWTsKPiAgIAlyZXQgPSByZWFkeF9wb2xsX3RpbWVvdXQocmVhZGwsIGRzaS0+YmFzZSAr IERTSV9DTURfUEtUX1NUQVRVUywKPiAtCQkJCSB2YWwsIHZhbCAmIChHRU5fQ01EX0VNUFRZIHwg R0VOX1BMRF9XX0VNUFRZKSwKPiArCQkJCSB2YWwsICh2YWwgJiBtYXNrKSA9PSBtYXNrLAo+ICAg CQkJCSAxMDAwLCBDTURfUEtUX1NUQVRVU19USU1FT1VUX1VTKTsKPiAgIAlpZiAocmV0IDwgMCkg ewo+ICAgCQlkZXZfZXJyKGRzaS0+ZGV2LCAiZmFpbGVkIHRvIHdyaXRlIGNvbW1hbmQgRklGT1xu Iik7CgoKX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KZHJp LWRldmVsIG1haWxpbmcgbGlzdApkcmktZGV2ZWxAbGlzdHMuZnJlZWRlc2t0b3Aub3JnCmh0dHBz Oi8vbGlzdHMuZnJlZWRlc2t0b3Aub3JnL21haWxtYW4vbGlzdGluZm8vZHJpLWRldmVsCg== From mboxrd@z Thu Jan 1 00:00:00 1970 From: zyw@rock-chips.com (Chris Zhong) Date: Sun, 22 Jan 2017 14:24:13 +0800 Subject: [PATCH v2 06/26] drm/rockchip: dw-mipi-dsi: fix generic packet status check In-Reply-To: <20170121163128.22240-7-john@metanate.com> References: <20170121163128.22240-1-john@metanate.com> <20170121163128.22240-7-john@metanate.com> Message-ID: <5884500D.7070706@rock-chips.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi John Reviewed-by: Chris Zhong On 01/22/2017 12:31 AM, John Keeping wrote: > We want to check that both the GEN_CMD_EMPTY and GEN_PLD_W_EMPTY bits > are set so we can't just check "val & mask" because that will be true if > either bit is set. According to DW mipi dsi controller databook, you are right. we should check both the 2 BIT. gen_pld_w_empty: This bit indicates the empty status of the generic write payload FIFO. Dependency : DSI_GENERIC = 1. Otherwise, this bit is reserved. Value after reset : 0x1 > Signed-off-by: John Keeping > --- > Unchanged in v2 > --- > drivers/gpu/drm/rockchip/dw-mipi-dsi.c | 5 +++-- > 1 file changed, 3 insertions(+), 2 deletions(-) > > diff --git a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > index 4cbbbcb619b7..4be1ff3a42bb 100644 > --- a/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > +++ b/drivers/gpu/drm/rockchip/dw-mipi-dsi.c > @@ -545,7 +545,7 @@ static int dw_mipi_dsi_host_detach(struct mipi_dsi_host *host, > static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) > { > int ret; > - u32 val; > + u32 val, mask; > > ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS, > val, !(val & GEN_CMD_FULL), 1000, > @@ -557,8 +557,9 @@ static int dw_mipi_dsi_gen_pkt_hdr_write(struct dw_mipi_dsi *dsi, u32 hdr_val) > > dsi_write(dsi, DSI_GEN_HDR, hdr_val); > > + mask = GEN_CMD_EMPTY | GEN_PLD_W_EMPTY; > ret = readx_poll_timeout(readl, dsi->base + DSI_CMD_PKT_STATUS, > - val, val & (GEN_CMD_EMPTY | GEN_PLD_W_EMPTY), > + val, (val & mask) == mask, > 1000, CMD_PKT_STATUS_TIMEOUT_US); > if (ret < 0) { > dev_err(dsi->dev, "failed to write command FIFO\n");