From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 6/8] x86emul: support MMX/SSE/SSE2 insns with only register operands Date: Wed, 25 Jan 2017 08:06:27 -0700 Message-ID: <5888CD030200007800133DBB@prv-mh.provo.novell.com> References: <5888C9110200007800133D98@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__PartE5DC38E3.1__=" Return-path: Received: from mail6.bemta5.messagelabs.com ([195.245.231.135]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1cWP9g-0000ZV-QM for xen-devel@lists.xenproject.org; Wed, 25 Jan 2017 15:06:37 +0000 In-Reply-To: <5888C9110200007800133D98@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel Cc: Andrew Cooper List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__PartE5DC38E3.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline This involves fixing a decode bug: VEX encoded insns aren't necessarily followed by a ModR/M byte. Signed-off-by: Jan Beulich --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -282,11 +282,11 @@ static const struct { [0x6e] =3D { DstImplicit|SrcMem|ModRM|Mov }, [0x6f] =3D { DstImplicit|SrcMem|ModRM|Mov, simd_packed_int }, [0x70] =3D { SrcImmByte|ModRM|TwoOp, simd_other }, - [0x71 ... 0x73] =3D { SrcImmByte|ModRM }, + [0x71 ... 0x73] =3D { DstImplicit|SrcImmByte|ModRM }, [0x74 ... 0x76] =3D { DstImplicit|SrcMem|ModRM, simd_packed_int }, [0x77] =3D { DstImplicit|SrcNone }, - [0x78] =3D { ModRM }, - [0x79] =3D { ModRM }, + [0x78] =3D { ImplicitOps|ModRM }, + [0x79] =3D { ImplicitOps|ModRM }, [0x7c] =3D { DstImplicit|SrcMem|ModRM, simd_other }, [0x7d] =3D { DstImplicit|SrcMem|ModRM, simd_other }, [0x7e] =3D { DstMem|SrcImplicit|ModRM|Mov }, @@ -326,7 +326,7 @@ static const struct { [0xc2] =3D { DstImplicit|SrcImmByte|ModRM, simd_any_fp }, [0xc3] =3D { DstMem|SrcReg|ModRM|Mov }, [0xc4] =3D { DstReg|SrcImmByte|ModRM, simd_packed_int }, - [0xc5] =3D { SrcImmByte|ModRM }, + [0xc5] =3D { DstMem|SrcImmByte|ModRM|Mov }, [0xc6] =3D { DstImplicit|SrcImmByte|ModRM, simd_packed_fp }, [0xc7] =3D { ImplicitOps|ModRM }, [0xc8 ... 0xcf] =3D { ImplicitOps }, @@ -2531,12 +2531,21 @@ x86_decode( =20 opcode |=3D b | MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK); =20 + if ( !(d & ModRM) ) + { + modrm_reg =3D modrm_rm =3D modrm_mod =3D modrm =3D 0; + break; + } + modrm =3D insn_fetch_type(uint8_t); modrm_mod =3D (modrm & 0xc0) >> 6; =20 break; } + } =20 + if ( d & ModRM ) + { modrm_reg =3D ((rex_prefix & 4) << 1) | ((modrm & 0x38) >> 3); modrm_rm =3D modrm & 0x07; =20 @@ -5686,6 +5695,18 @@ x86_emulate( CASE_SIMD_PACKED_FP(_VEX, 0x0f, 0x50): /* vmovmskp{s,d} {x,y}mm,reg = */ CASE_SIMD_PACKED_INT(0x0f, 0xd7): /* pmovmskb {,x}mm,reg */ case X86EMUL_OPC_VEX_66(0x0f, 0xd7): /* vpmovmskb {x,y}mm,reg */ + opc =3D init_prefixes(stub); + opc[0] =3D b; + /* Convert GPR destination to %rAX. */ + rex_prefix &=3D ~REX_R; + vex.r =3D 1; + if ( !mode_64bit() ) + vex.w =3D 0; + opc[1] =3D modrm & 0xc7; + fic.insn_bytes =3D PFX_BYTES + 2; + simd_0f_to_gpr: + opc[fic.insn_bytes - PFX_BYTES] =3D 0xc3; + generate_exception_if(ea.type !=3D OP_REG, EXC_UD); =20 if ( vex.opcx =3D=3D vex_none ) @@ -5713,17 +5734,6 @@ x86_emulate( get_fpu(X86EMUL_FPU_ymm, &fic); } =20 - opc =3D init_prefixes(stub); - opc[0] =3D b; - /* Convert GPR destination to %rAX. */ - rex_prefix &=3D ~REX_R; - vex.r =3D 1; - if ( !mode_64bit() ) - vex.w =3D 0; - opc[1] =3D modrm & 0xc7; - fic.insn_bytes =3D PFX_BYTES + 2; - opc[2] =3D 0xc3; - copy_REX_VEX(opc, rex_prefix, vex); invoke_stub("", "", "=3Da" (dst.val) : [dummy] "i" (0)); =20 @@ -5991,6 +6001,138 @@ x86_emulate( fic.insn_bytes =3D PFX_BYTES + 3; break; =20 + CASE_SIMD_PACKED_INT(0x0f, 0x71): /* Grp12 */ + case X86EMUL_OPC_VEX_66(0x0f, 0x71): + CASE_SIMD_PACKED_INT(0x0f, 0x72): /* Grp13 */ + case X86EMUL_OPC_VEX_66(0x0f, 0x72): + switch ( modrm_reg & 7 ) + { + case 2: /* psrl{w,d} $imm8,{,x}mm */ + /* vpsrl{w,d} $imm8,{x,y}mm,{x,y}mm */ + case 4: /* psra{w,d} $imm8,{,x}mm */ + /* vpsra{w,d} $imm8,{x,y}mm,{x,y}mm */ + case 6: /* psll{w,d} $imm8,{,x}mm */ + /* vpsll{w,d} $imm8,{x,y}mm,{x,y}mm */ + break; + default: + goto cannot_emulate; + } + simd_0f_shift_imm: + generate_exception_if(ea.type !=3D OP_REG, EXC_UD); + + if ( vex.opcx !=3D vex_none ) + { + if ( vex.l ) + host_and_vcpu_must_have(avx2); + else + host_and_vcpu_must_have(avx); + get_fpu(X86EMUL_FPU_ymm, &fic); + } + else if ( vex.pfx ) + { + vcpu_must_have(sse2); + get_fpu(X86EMUL_FPU_xmm, &fic); + } + else + { + host_and_vcpu_must_have(mmx); + get_fpu(X86EMUL_FPU_mmx, &fic); + } + + opc =3D init_prefixes(stub); + opc[0] =3D b; + opc[1] =3D modrm; + opc[2] =3D imm1; + fic.insn_bytes =3D PFX_BYTES + 3; + simd_0f_reg_only: + opc[fic.insn_bytes - PFX_BYTES] =3D 0xc3; + + copy_REX_VEX(opc, rex_prefix, vex); + invoke_stub("", "", [dummy_out] "=3Dg" (cr4) : [dummy_in] "i" (0) = ); + + put_stub(stub); + put_fpu(&fic); + break; + + case X86EMUL_OPC(0x0f, 0x73): /* Grp14 */ + switch ( modrm_reg & 7 ) + { + case 2: /* psrlq $imm8,mm */ + case 6: /* psllq $imm8,mm */ + goto simd_0f_shift_imm; + } + goto cannot_emulate; + + case X86EMUL_OPC_66(0x0f, 0x73): + case X86EMUL_OPC_VEX_66(0x0f, 0x73): + switch ( modrm_reg & 7 ) + { + case 2: /* psrlq $imm8,xmm */ + /* vpsrlq $imm8,{x,y}mm,{x,y}mm */ + case 3: /* psrldq $imm8,xmm */ + /* vpsrldq $imm8,{x,y}mm,{x,y}mm */ + case 6: /* psllq $imm8,xmm */ + /* vpsllq $imm8,{x,y}mm,{x,y}mm */ + case 7: /* pslldq $imm8,xmm */ + /* vpslldq $imm8,{x,y}mm,{x,y}mm */ + goto simd_0f_shift_imm; + } + goto cannot_emulate; + + case X86EMUL_OPC(0x0f, 0x77): /* emms */ + case X86EMUL_OPC_VEX(0x0f, 0x77): /* vzero{all,upper} */ + if ( vex.opcx !=3D vex_none ) + { + host_and_vcpu_must_have(avx); + get_fpu(X86EMUL_FPU_ymm, &fic); + } + else + { + host_and_vcpu_must_have(mmx); + get_fpu(X86EMUL_FPU_mmx, &fic); + } + + opc =3D init_prefixes(stub); + opc[0] =3D b; + fic.insn_bytes =3D PFX_BYTES + 1; + goto simd_0f_reg_only; + + case X86EMUL_OPC_66(0x0f, 0x78): /* Grp17 */ + switch ( modrm_reg & 7 ) + { + case 0: /* extrq $imm8,$imm8,xmm */ + break; + default: + goto cannot_emulate; + } + /* fall through */ + case X86EMUL_OPC_F2(0x0f, 0x78): /* insertq $imm8,$imm8,xmm,xmm = */ + generate_exception_if(ea.type !=3D OP_REG, EXC_UD); + + host_and_vcpu_must_have(sse4a); + get_fpu(X86EMUL_FPU_xmm, &fic); + + opc =3D init_prefixes(stub); + opc[0] =3D b; + opc[1] =3D modrm; + opc[2] =3D imm1; + opc[3] =3D imm2; + fic.insn_bytes =3D PFX_BYTES + 4; + goto simd_0f_reg_only; + + case X86EMUL_OPC_66(0x0f, 0x79): /* extrq xmm,xmm */ + case X86EMUL_OPC_F2(0x0f, 0x79): /* insertq xmm,xmm */ + generate_exception_if(ea.type !=3D OP_REG, EXC_UD); + + host_and_vcpu_must_have(sse4a); + get_fpu(X86EMUL_FPU_xmm, &fic); + + opc =3D init_prefixes(stub); + opc[0] =3D b; + opc[1] =3D modrm; + fic.insn_bytes =3D PFX_BYTES + 2; + goto simd_0f_reg_only; + case X86EMUL_OPC_F3(0x0f, 0x7e): /* movq xmm/m64,xmm */ case X86EMUL_OPC_VEX_F3(0x0f, 0x7e): /* vmovq xmm/m64,xmm */ generate_exception_if(vex.l, EXC_UD); @@ -6361,6 +6503,22 @@ x86_emulate( ea.type =3D OP_MEM; goto simd_0f_int_imm8; =20 + case X86EMUL_OPC_VEX_66(0x0f, 0xc5): /* vpextrw $imm8,xmm,reg */ + generate_exception_if(vex.l, EXC_UD); + /* fall through */ + CASE_SIMD_PACKED_INT(0x0f, 0xc5): /* pextrw $imm8,{,x}mm,reg */ + opc =3D init_prefixes(stub); + opc[0] =3D b; + /* Convert GPR destination to %rAX. */ + rex_prefix &=3D ~REX_R; + vex.r =3D 1; + if ( !mode_64bit() ) + vex.w =3D 0; + opc[1] =3D modrm & 0xc7; + opc[2] =3D imm1; + fic.insn_bytes =3D PFX_BYTES + 3; + goto simd_0f_to_gpr; + case X86EMUL_OPC(0x0f, 0xc7): /* Grp9 */ { union { --=__PartE5DC38E3.1__= Content-Type: text/plain; name="x86emul-SSE-AVX-0f-reg.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86emul-SSE-AVX-0f-reg.patch" x86emul: support MMX/SSE/SSE2 insns with only register operands=0A=0AThis = involves fixing a decode bug: VEX encoded insns aren't necessarily=0Afollow= ed by a ModR/M byte.=0A=0ASigned-off-by: Jan Beulich =0A= =0A--- a/xen/arch/x86/x86_emulate/x86_emulate.c=0A+++ b/xen/arch/x86/x86_em= ulate/x86_emulate.c=0A@@ -282,11 +282,11 @@ static const struct {=0A = [0x6e] =3D { DstImplicit|SrcMem|ModRM|Mov },=0A [0x6f] =3D { DstImplici= t|SrcMem|ModRM|Mov, simd_packed_int },=0A [0x70] =3D { SrcImmByte|ModRM= |TwoOp, simd_other },=0A- [0x71 ... 0x73] =3D { SrcImmByte|ModRM },=0A+ = [0x71 ... 0x73] =3D { DstImplicit|SrcImmByte|ModRM },=0A [0x74 ... = 0x76] =3D { DstImplicit|SrcMem|ModRM, simd_packed_int },=0A [0x77] =3D = { DstImplicit|SrcNone },=0A- [0x78] =3D { ModRM },=0A- [0x79] =3D { = ModRM },=0A+ [0x78] =3D { ImplicitOps|ModRM },=0A+ [0x79] =3D { = ImplicitOps|ModRM },=0A [0x7c] =3D { DstImplicit|SrcMem|ModRM, = simd_other },=0A [0x7d] =3D { DstImplicit|SrcMem|ModRM, simd_other = },=0A [0x7e] =3D { DstMem|SrcImplicit|ModRM|Mov },=0A@@ -326,7 +326,7 = @@ static const struct {=0A [0xc2] =3D { DstImplicit|SrcImmByte|ModRM, = simd_any_fp },=0A [0xc3] =3D { DstMem|SrcReg|ModRM|Mov },=0A = [0xc4] =3D { DstReg|SrcImmByte|ModRM, simd_packed_int },=0A- [0xc5] =3D = { SrcImmByte|ModRM },=0A+ [0xc5] =3D { DstMem|SrcImmByte|ModRM|Mov = },=0A [0xc6] =3D { DstImplicit|SrcImmByte|ModRM, simd_packed_fp },=0A = [0xc7] =3D { ImplicitOps|ModRM },=0A [0xc8 ... 0xcf] =3D { = ImplicitOps },=0A@@ -2531,12 +2531,21 @@ x86_decode(=0A =0A = opcode |=3D b | MASK_INSR(vex.pfx, X86EMUL_OPC_PFX_MASK);=0A =0A+ = if ( !(d & ModRM) )=0A+ {=0A+ = modrm_reg =3D modrm_rm =3D modrm_mod =3D modrm =3D 0;=0A+ = break;=0A+ }=0A+=0A modrm =3D insn_fetch_t= ype(uint8_t);=0A modrm_mod =3D (modrm & 0xc0) >> 6;=0A =0A = break;=0A }=0A+ }=0A =0A+ if ( d & ModRM = )=0A+ {=0A modrm_reg =3D ((rex_prefix & 4) << 1) | ((modrm & = 0x38) >> 3);=0A modrm_rm =3D modrm & 0x07;=0A =0A@@ -5686,6 = +5695,18 @@ x86_emulate(=0A CASE_SIMD_PACKED_FP(_VEX, 0x0f, 0x50): /* = vmovmskp{s,d} {x,y}mm,reg */=0A CASE_SIMD_PACKED_INT(0x0f, 0xd7): = /* pmovmskb {,x}mm,reg */=0A case X86EMUL_OPC_VEX_66(0x0f, 0xd7): /* = vpmovmskb {x,y}mm,reg */=0A+ opc =3D init_prefixes(stub);=0A+ = opc[0] =3D b;=0A+ /* Convert GPR destination to %rAX. */=0A+ = rex_prefix &=3D ~REX_R;=0A+ vex.r =3D 1;=0A+ if ( !mode_64bi= t() )=0A+ vex.w =3D 0;=0A+ opc[1] =3D modrm & 0xc7;=0A+ = fic.insn_bytes =3D PFX_BYTES + 2;=0A+ simd_0f_to_gpr:=0A+ = opc[fic.insn_bytes - PFX_BYTES] =3D 0xc3;=0A+=0A generate_exception= _if(ea.type !=3D OP_REG, EXC_UD);=0A =0A if ( vex.opcx =3D=3D = vex_none )=0A@@ -5713,17 +5734,6 @@ x86_emulate(=0A get_fpu(X86= EMUL_FPU_ymm, &fic);=0A }=0A =0A- opc =3D init_prefixes(stub= );=0A- opc[0] =3D b;=0A- /* Convert GPR destination to %rAX. = */=0A- rex_prefix &=3D ~REX_R;=0A- vex.r =3D 1;=0A- = if ( !mode_64bit() )=0A- vex.w =3D 0;=0A- opc[1] =3D = modrm & 0xc7;=0A- fic.insn_bytes =3D PFX_BYTES + 2;=0A- = opc[2] =3D 0xc3;=0A-=0A copy_REX_VEX(opc, rex_prefix, vex);=0A = invoke_stub("", "", "=3Da" (dst.val) : [dummy] "i" (0));=0A =0A@@ = -5991,6 +6001,138 @@ x86_emulate(=0A fic.insn_bytes =3D PFX_BYTES = + 3;=0A break;=0A =0A+ CASE_SIMD_PACKED_INT(0x0f, 0x71): /* = Grp12 */=0A+ case X86EMUL_OPC_VEX_66(0x0f, 0x71):=0A+ CASE_SIMD_PACKE= D_INT(0x0f, 0x72): /* Grp13 */=0A+ case X86EMUL_OPC_VEX_66(0x0f, = 0x72):=0A+ switch ( modrm_reg & 7 )=0A+ {=0A+ case 2: = /* psrl{w,d} $imm8,{,x}mm */=0A+ /* vpsrl{w,d} $imm8,{x,y}mm= ,{x,y}mm */=0A+ case 4: /* psra{w,d} $imm8,{,x}mm */=0A+ = /* vpsra{w,d} $imm8,{x,y}mm,{x,y}mm */=0A+ case 6: /* psll{w,d} = $imm8,{,x}mm */=0A+ /* vpsll{w,d} $imm8,{x,y}mm,{x,y}mm = */=0A+ break;=0A+ default:=0A+ goto cannot_emu= late;=0A+ }=0A+ simd_0f_shift_imm:=0A+ generate_exception_= if(ea.type !=3D OP_REG, EXC_UD);=0A+=0A+ if ( vex.opcx !=3D = vex_none )=0A+ {=0A+ if ( vex.l )=0A+ = host_and_vcpu_must_have(avx2);=0A+ else=0A+ = host_and_vcpu_must_have(avx);=0A+ get_fpu(X86EMUL_FPU_ymm, = &fic);=0A+ }=0A+ else if ( vex.pfx )=0A+ {=0A+ = vcpu_must_have(sse2);=0A+ get_fpu(X86EMUL_FPU_xmm, = &fic);=0A+ }=0A+ else=0A+ {=0A+ host_and_vc= pu_must_have(mmx);=0A+ get_fpu(X86EMUL_FPU_mmx, &fic);=0A+ = }=0A+=0A+ opc =3D init_prefixes(stub);=0A+ opc[0] =3D = b;=0A+ opc[1] =3D modrm;=0A+ opc[2] =3D imm1;=0A+ = fic.insn_bytes =3D PFX_BYTES + 3;=0A+ simd_0f_reg_only:=0A+ = opc[fic.insn_bytes - PFX_BYTES] =3D 0xc3;=0A+=0A+ copy_REX_VEX(opc, = rex_prefix, vex);=0A+ invoke_stub("", "", [dummy_out] "=3Dg" (cr4) = : [dummy_in] "i" (0) );=0A+=0A+ put_stub(stub);=0A+ = put_fpu(&fic);=0A+ break;=0A+=0A+ case X86EMUL_OPC(0x0f, 0x73): = /* Grp14 */=0A+ switch ( modrm_reg & 7 )=0A+ {=0A+ = case 2: /* psrlq $imm8,mm */=0A+ case 6: /* psllq $imm8,mm = */=0A+ goto simd_0f_shift_imm;=0A+ }=0A+ goto = cannot_emulate;=0A+=0A+ case X86EMUL_OPC_66(0x0f, 0x73):=0A+ case = X86EMUL_OPC_VEX_66(0x0f, 0x73):=0A+ switch ( modrm_reg & 7 )=0A+ = {=0A+ case 2: /* psrlq $imm8,xmm */=0A+ /* = vpsrlq $imm8,{x,y}mm,{x,y}mm */=0A+ case 3: /* psrldq $imm8,xmm = */=0A+ /* vpsrldq $imm8,{x,y}mm,{x,y}mm */=0A+ case = 6: /* psllq $imm8,xmm */=0A+ /* vpsllq $imm8,{x,y}mm,{x,y}mm= */=0A+ case 7: /* pslldq $imm8,xmm */=0A+ /* = vpslldq $imm8,{x,y}mm,{x,y}mm */=0A+ goto simd_0f_shift_imm;=0A+= }=0A+ goto cannot_emulate;=0A+=0A+ case X86EMUL_OPC(0x0f,= 0x77): /* emms */=0A+ case X86EMUL_OPC_VEX(0x0f, 0x77): /* = vzero{all,upper} */=0A+ if ( vex.opcx !=3D vex_none )=0A+ = {=0A+ host_and_vcpu_must_have(avx);=0A+ get_fpu(X86EM= UL_FPU_ymm, &fic);=0A+ }=0A+ else=0A+ {=0A+ = host_and_vcpu_must_have(mmx);=0A+ get_fpu(X86EMUL_FPU_mmx, = &fic);=0A+ }=0A+=0A+ opc =3D init_prefixes(stub);=0A+ = opc[0] =3D b;=0A+ fic.insn_bytes =3D PFX_BYTES + 1;=0A+ goto = simd_0f_reg_only;=0A+=0A+ case X86EMUL_OPC_66(0x0f, 0x78): /* Grp17 = */=0A+ switch ( modrm_reg & 7 )=0A+ {=0A+ case 0: /* = extrq $imm8,$imm8,xmm */=0A+ break;=0A+ default:=0A+ = goto cannot_emulate;=0A+ }=0A+ /* fall through */=0A+ = case X86EMUL_OPC_F2(0x0f, 0x78): /* insertq $imm8,$imm8,xmm,xmm = */=0A+ generate_exception_if(ea.type !=3D OP_REG, EXC_UD);=0A+=0A+ = host_and_vcpu_must_have(sse4a);=0A+ get_fpu(X86EMUL_FPU_xmm, = &fic);=0A+=0A+ opc =3D init_prefixes(stub);=0A+ opc[0] =3D = b;=0A+ opc[1] =3D modrm;=0A+ opc[2] =3D imm1;=0A+ = opc[3] =3D imm2;=0A+ fic.insn_bytes =3D PFX_BYTES + 4;=0A+ = goto simd_0f_reg_only;=0A+=0A+ case X86EMUL_OPC_66(0x0f, 0x79): /* = extrq xmm,xmm */=0A+ case X86EMUL_OPC_F2(0x0f, 0x79): /* insertq = xmm,xmm */=0A+ generate_exception_if(ea.type !=3D OP_REG, = EXC_UD);=0A+=0A+ host_and_vcpu_must_have(sse4a);=0A+ = get_fpu(X86EMUL_FPU_xmm, &fic);=0A+=0A+ opc =3D init_prefixes(stub);= =0A+ opc[0] =3D b;=0A+ opc[1] =3D modrm;=0A+ = fic.insn_bytes =3D PFX_BYTES + 2;=0A+ goto simd_0f_reg_only;=0A+=0A = case X86EMUL_OPC_F3(0x0f, 0x7e): /* movq xmm/m64,xmm */=0A = case X86EMUL_OPC_VEX_F3(0x0f, 0x7e): /* vmovq xmm/m64,xmm */=0A = generate_exception_if(vex.l, EXC_UD);=0A@@ -6361,6 +6503,22 @@ x86_emulate(= =0A ea.type =3D OP_MEM;=0A goto simd_0f_int_imm8;=0A =0A+ = case X86EMUL_OPC_VEX_66(0x0f, 0xc5): /* vpextrw $imm8,xmm,reg */=0A+ = generate_exception_if(vex.l, EXC_UD);=0A+ /* fall through = */=0A+ CASE_SIMD_PACKED_INT(0x0f, 0xc5): /* pextrw $imm8,{,x}mm,reg= */=0A+ opc =3D init_prefixes(stub);=0A+ opc[0] =3D b;=0A+ = /* Convert GPR destination to %rAX. */=0A+ rex_prefix &=3D = ~REX_R;=0A+ vex.r =3D 1;=0A+ if ( !mode_64bit() )=0A+ = vex.w =3D 0;=0A+ opc[1] =3D modrm & 0xc7;=0A+ opc[2] =3D = imm1;=0A+ fic.insn_bytes =3D PFX_BYTES + 3;=0A+ goto = simd_0f_to_gpr;=0A+=0A case X86EMUL_OPC(0x0f, 0xc7): /* Grp9 */=0A = {=0A union {=0A --=__PartE5DC38E3.1__= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwczovL2xpc3RzLnhlbi5v cmcveGVuLWRldmVsCg== --=__PartE5DC38E3.1__=--