From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Jan Beulich" Subject: [PATCH 1/3] x86emul: switch away from temporary 32-bit register names Date: Tue, 07 Mar 2017 09:42:00 -0700 Message-ID: <58BEF0E80200007800140ED7@prv-mh.provo.novell.com> References: <58BEF0470200007800140EB8@prv-mh.provo.novell.com> <58BEF0470200007800140EB8@prv-mh.provo.novell.com> Mime-Version: 1.0 Content-Type: multipart/mixed; boundary="=__PartA49D4FC8.1__=" Return-path: Received: from mail6.bemta3.messagelabs.com ([195.245.230.39]) by lists.xenproject.org with esmtp (Exim 4.84_2) (envelope-from ) id 1clIBd-0000jO-9j for xen-devel@lists.xenproject.org; Tue, 07 Mar 2017 16:42:09 +0000 In-Reply-To: <58BEF0470200007800140EB8@prv-mh.provo.novell.com> List-Unsubscribe: , List-Post: List-Help: List-Subscribe: , Errors-To: xen-devel-bounces@lists.xen.org Sender: "Xen-devel" To: xen-devel Cc: Andrew Cooper List-Id: xen-devel@lists.xenproject.org This is a MIME message. If you are reading this text, you may want to consider changing to a mail reader or gateway that understands how to properly handle MIME multipart messages. --=__PartA49D4FC8.1__= Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: quoted-printable Content-Disposition: inline Signed-off-by: Jan Beulich --- a/xen/arch/x86/x86_emulate/x86_emulate.c +++ b/xen/arch/x86/x86_emulate/x86_emulate.c @@ -811,7 +811,7 @@ do{ asm volatile ( unsigned long tmp; \ invoke_stub(_PRE_EFLAGS("[efl]", "[msk]", "[tmp]"), \ _POST_EFLAGS("[efl]", "[msk]", "[tmp]"), \ - dst, [tmp] "=3D&r" (tmp), [efl] "+g" (_regs._eflags) = \ + dst, [tmp] "=3D&r" (tmp), [efl] "+g" (_regs.eflags) = \ : [msk] "i" (EFLAGS_MASK), ## src); \ } while (0) =20 @@ -890,7 +890,7 @@ do { } while (0) #define register_address_adjust(reg, adj) \ _register_address_increment(reg, \ - _regs._eflags & X86_EFLAGS_DF ? \ + _regs.eflags & X86_EFLAGS_DF ? \ -(adj) : (adj), \ ad_bytes) =20 @@ -914,7 +914,7 @@ do { rc =3D ops->insn_fetch(x86_seg_cs, ip, NULL, 0, ctxt); = \ if ( rc ) goto done; \ _regs.r(ip) =3D ip; = \ - singlestep =3D _regs._eflags & X86_EFLAGS_TF; = \ + singlestep =3D _regs.eflags & X86_EFLAGS_TF; = \ } while (0) =20 #define validate_far_branch(cs, ip) ({ \ @@ -931,7 +931,7 @@ do { #define commit_far_branch(cs, newip) ({ \ validate_far_branch(cs, newip); \ _regs.r(ip) =3D (newip); = \ - singlestep =3D _regs._eflags & X86_EFLAGS_TF; = \ + singlestep =3D _regs.eflags & X86_EFLAGS_TF; = \ ops->write_segment(x86_seg_cs, cs, ctxt); \ }) =20 @@ -984,7 +984,7 @@ static int _get_fpu( if ( type >=3D X86EMUL_FPU_ymm ) { /* Should be unreachable if VEX decoding is working correctly.= */ - ASSERT((cr0 & X86_CR0_PE) && !(ctxt->regs->_eflags & = X86_EFLAGS_VM)); + ASSERT((cr0 & X86_CR0_PE) && !(ctxt->regs->eflags & X86_EFLAGS= _VM)); } if ( cr0 & X86_CR0_EM ) { @@ -1071,7 +1071,7 @@ do { memcpy(get_stub(stub), ((uint8_t[]){ bytes, 0xc3 }), nr_ + 1); \ invoke_stub(_PRE_EFLAGS("[eflags]", "[mask]", "[tmp]"), \ _POST_EFLAGS("[eflags]", "[mask]", "[tmp]"), \ - [eflags] "+g" (_regs._eflags), [tmp] "=3D&r" (tmp_), = \ + [eflags] "+g" (_regs.eflags), [tmp] "=3D&r" (tmp_), = \ "+m" (fic) \ : [mask] "i" (X86_EFLAGS_ZF|X86_EFLAGS_PF|X86_EFLAGS_CF));= \ put_stub(stub); \ @@ -1082,7 +1082,7 @@ static inline unsigned long get_loop_cou int ad_bytes) { return (ad_bytes > 4) ? regs->r(cx) - : (ad_bytes < 4) ? regs->cx : regs->_ecx; + : (ad_bytes < 4) ? regs->cx : regs->ecx; } =20 static inline void put_loop_count( @@ -1110,12 +1110,12 @@ static inline void put_loop_count( if ( mode_64bit() && ad_bytes =3D=3D 4 ) = \ { \ _regs.r(cx) =3D 0; = \ - if ( using_si ) _regs.r(si) =3D _regs._esi; = \ - if ( using_di ) _regs.r(di) =3D _regs._edi; = \ + if ( using_si ) _regs.r(si) =3D _regs.esi; = \ + if ( using_di ) _regs.r(di) =3D _regs.edi; = \ } \ goto complete_insn; \ } \ - if ( max_reps > 1 && (_regs._eflags & X86_EFLAGS_TF) && \ + if ( max_reps > 1 && (_regs.eflags & X86_EFLAGS_TF) && \ !is_branch_step(ctxt, ops) ) \ max_reps =3D 1; = \ max_reps; \ @@ -1149,7 +1149,7 @@ static void __put_rep_prefix( /* Clip maximum repetitions so that the index register at most just = wraps. */ #define truncate_ea_and_reps(ea, reps, bytes_per_rep) ({ = \ unsigned long todo__, ea__ =3D truncate_word(ea, ad_bytes); = \ - if ( !(_regs._eflags & X86_EFLAGS_DF) ) = \ + if ( !(_regs.eflags & X86_EFLAGS_DF) ) = \ todo__ =3D truncate_word(-(ea), ad_bytes) / (bytes_per_rep); = \ else if ( truncate_word((ea) + (bytes_per_rep) - 1, ad_bytes) < ea__ = )\ todo__ =3D 1; = \ @@ -1306,7 +1306,7 @@ get_cpl( { struct segment_register reg; =20 - if ( ctxt->regs->_eflags & X86_EFLAGS_VM ) + if ( ctxt->regs->eflags & X86_EFLAGS_VM ) return 3; =20 if ( (ops->read_segment =3D=3D NULL) || @@ -1324,7 +1324,7 @@ _mode_iopl( int cpl =3D get_cpl(ctxt, ops); if ( cpl =3D=3D -1 ) return -1; - return cpl <=3D MASK_EXTR(ctxt->regs->_eflags, X86_EFLAGS_IOPL); + return cpl <=3D MASK_EXTR(ctxt->regs->eflags, X86_EFLAGS_IOPL); } =20 #define mode_ring0() ({ \ @@ -1344,7 +1344,7 @@ _mode_iopl( rc =3D ops->read_cr(4, &cr4, ctxt); \ if ( rc !=3D X86EMUL_OKAY ) goto done; \ } \ - !!(cr4 & (_regs._eflags & X86_EFLAGS_VM ? X86_CR4_VME : X86_CR4_PVI));= \ + !!(cr4 & (_regs.eflags & X86_EFLAGS_VM ? X86_CR4_VME : X86_CR4_PVI)); = \ }) =20 static int ioport_access_check( @@ -1357,7 +1357,7 @@ static int ioport_access_check( struct segment_register tr; int rc =3D X86EMUL_OKAY; =20 - if ( !(ctxt->regs->_eflags & X86_EFLAGS_VM) && mode_iopl() ) + if ( !(ctxt->regs->eflags & X86_EFLAGS_VM) && mode_iopl() ) return X86EMUL_OKAY; =20 fail_if(ops->read_segment =3D=3D NULL); @@ -1426,7 +1426,7 @@ in_protmode( struct x86_emulate_ctxt *ctxt, const struct x86_emulate_ops *ops) { - return !(in_realmode(ctxt, ops) || (ctxt->regs->_eflags & X86_EFLAGS_V= M)); + return !(in_realmode(ctxt, ops) || (ctxt->regs->eflags & X86_EFLAGS_VM= )); } =20 #define EAX 0 @@ -1958,8 +1958,8 @@ static int inject_swint(enum x86_swint_t * a 32bit OS. Someone with many TUITs can see about reading = the * TSS Software Interrupt Redirection bitmap. */ - if ( (ctxt->regs->_eflags & X86_EFLAGS_VM) && - ((ctxt->regs->_eflags & X86_EFLAGS_IOPL) !=3D X86_EFLAGS_= IOPL) ) + if ( (ctxt->regs->eflags & X86_EFLAGS_VM) && + ((ctxt->regs->eflags & X86_EFLAGS_IOPL) !=3D X86_EFLAGS_I= OPL) ) goto raise_exn; =20 /* @@ -2524,7 +2524,7 @@ x86_decode( default: BUG(); /* Shouldn't be possible. */ case 2: - if ( state->regs->_eflags & X86_EFLAGS_VM ) + if ( state->regs->eflags & X86_EFLAGS_VM ) break; /* fall through */ case 4: @@ -2977,7 +2977,7 @@ x86_emulate( struct x86_emulate_state state; int rc; uint8_t b, d, *opc =3D NULL; - bool singlestep =3D (_regs._eflags & X86_EFLAGS_TF) && + bool singlestep =3D (_regs.eflags & X86_EFLAGS_TF) && !is_branch_step(ctxt, ops); bool sfence =3D false; struct operand src =3D { .reg =3D PTR_POISON }; @@ -3199,36 +3199,36 @@ x86_emulate( unsigned long dummy; =20 case 0x00 ... 0x05: add: /* add */ - emulate_2op_SrcV("add", src, dst, _regs._eflags); + emulate_2op_SrcV("add", src, dst, _regs.eflags); break; =20 case 0x08 ... 0x0d: or: /* or */ - emulate_2op_SrcV("or", src, dst, _regs._eflags); + emulate_2op_SrcV("or", src, dst, _regs.eflags); break; =20 case 0x10 ... 0x15: adc: /* adc */ - emulate_2op_SrcV("adc", src, dst, _regs._eflags); + emulate_2op_SrcV("adc", src, dst, _regs.eflags); break; =20 case 0x18 ... 0x1d: sbb: /* sbb */ - emulate_2op_SrcV("sbb", src, dst, _regs._eflags); + emulate_2op_SrcV("sbb", src, dst, _regs.eflags); break; =20 case 0x20 ... 0x25: and: /* and */ - emulate_2op_SrcV("and", src, dst, _regs._eflags); + emulate_2op_SrcV("and", src, dst, _regs.eflags); break; =20 case 0x28 ... 0x2d: sub: /* sub */ - emulate_2op_SrcV("sub", src, dst, _regs._eflags); + emulate_2op_SrcV("sub", src, dst, _regs.eflags); break; =20 case 0x30 ... 0x35: xor: /* xor */ - emulate_2op_SrcV("xor", src, dst, _regs._eflags); + emulate_2op_SrcV("xor", src, dst, _regs.eflags); break; =20 case 0x38 ... 0x3d: cmp: /* cmp */ generate_exception_if(lock_prefix, EXC_UD); - emulate_2op_SrcV("cmp", src, dst, _regs._eflags); + emulate_2op_SrcV("cmp", src, dst, _regs.eflags); dst.type =3D OP_NONE; break; =20 @@ -3266,36 +3266,36 @@ x86_emulate( case 0x27: /* daa */ case 0x2f: /* das */ { uint8_t al =3D _regs.al; - unsigned int eflags =3D _regs._eflags; + unsigned int eflags =3D _regs.eflags; =20 - _regs._eflags &=3D ~(X86_EFLAGS_CF | X86_EFLAGS_AF | X86_EFLAGS_SF= | + _regs.eflags &=3D ~(X86_EFLAGS_CF | X86_EFLAGS_AF | X86_EFLAGS_SF = | X86_EFLAGS_ZF | X86_EFLAGS_PF); if ( ((al & 0x0f) > 9) || (eflags & X86_EFLAGS_AF) ) { - _regs._eflags |=3D X86_EFLAGS_AF; + _regs.eflags |=3D X86_EFLAGS_AF; if ( b =3D=3D 0x2f && (al < 6 || (eflags & X86_EFLAGS_CF)) ) - _regs._eflags |=3D X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_CF; _regs.al +=3D (b =3D=3D 0x27) ? 6 : -6; } if ( (al > 0x99) || (eflags & X86_EFLAGS_CF) ) { _regs.al +=3D (b =3D=3D 0x27) ? 0x60 : -0x60; - _regs._eflags |=3D X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_CF; } - _regs._eflags |=3D !_regs.al ? X86_EFLAGS_ZF : 0; - _regs._eflags |=3D ((int8_t)_regs.al < 0) ? X86_EFLAGS_SF : 0; - _regs._eflags |=3D even_parity(_regs.al) ? X86_EFLAGS_PF : 0; + _regs.eflags |=3D !_regs.al ? X86_EFLAGS_ZF : 0; + _regs.eflags |=3D ((int8_t)_regs.al < 0) ? X86_EFLAGS_SF : 0; + _regs.eflags |=3D even_parity(_regs.al) ? X86_EFLAGS_PF : 0; break; } =20 case 0x37: /* aaa */ case 0x3f: /* aas */ - _regs._eflags &=3D ~X86_EFLAGS_CF; - if ( (_regs.al > 9) || (_regs._eflags & X86_EFLAGS_AF) ) + _regs.eflags &=3D ~X86_EFLAGS_CF; + if ( (_regs.al > 9) || (_regs.eflags & X86_EFLAGS_AF) ) { _regs.al +=3D (b =3D=3D 0x37) ? 6 : -6; _regs.ah +=3D (b =3D=3D 0x37) ? 1 : -1; - _regs._eflags |=3D X86_EFLAGS_CF | X86_EFLAGS_AF; + _regs.eflags |=3D X86_EFLAGS_CF | X86_EFLAGS_AF; } _regs.al &=3D 0x0f; break; @@ -3306,9 +3306,9 @@ x86_emulate( dst.bytes =3D op_bytes; dst.val =3D *dst.reg; if ( b & 8 ) - emulate_1op("dec", dst, _regs._eflags); + emulate_1op("dec", dst, _regs.eflags); else - emulate_1op("inc", dst, _regs._eflags); + emulate_1op("inc", dst, _regs.eflags); break; =20 case 0x50 ... 0x57: /* push reg */ @@ -3331,8 +3331,8 @@ x86_emulate( case 0x60: /* pusha */ { int i; unsigned int regs[] =3D { - _regs._eax, _regs._ecx, _regs._edx, _regs._ebx, - _regs._esp, _regs._ebp, _regs._esi, _regs._edi }; + _regs.eax, _regs.ecx, _regs.edx, _regs.ebx, + _regs.esp, _regs.ebp, _regs.esi, _regs.edi }; =20 fail_if(!ops->write); for ( i =3D 0; i < 8; i++ ) @@ -3345,8 +3345,8 @@ x86_emulate( case 0x61: /* popa */ { int i; unsigned int dummy_esp, *regs[] =3D { - &_regs._edi, &_regs._esi, &_regs._ebp, &dummy_esp, - &_regs._ebx, &_regs._edx, &_regs._ecx, &_regs._eax }; + &_regs.edi, &_regs.esi, &_regs.ebp, &dummy_esp, + &_regs.ebx, &_regs.edx, &_regs.ecx, &_regs.eax }; =20 for ( i =3D 0; i < 8; i++ ) { @@ -3401,12 +3401,12 @@ x86_emulate( goto done; if ( src_rpl > (dst.val & 3) ) { - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; dst.val =3D (dst.val & ~3) | src_rpl; } else { - _regs._eflags &=3D ~X86_EFLAGS_ZF; + _regs.eflags &=3D ~X86_EFLAGS_ZF; dst.type =3D OP_NONE; } generate_exception_if(!in_protmode(ctxt, ops), EXC_UD); @@ -3518,7 +3518,7 @@ x86_emulate( } =20 case 0x70 ... 0x7f: /* jcc (short) */ - if ( test_cc(b, _regs._eflags) ) + if ( test_cc(b, _regs.eflags) ) jmp_rel((int32_t)src.val); adjust_bnd(ctxt, ops, vex.pfx); break; @@ -3539,7 +3539,7 @@ x86_emulate( =20 case 0xa8 ... 0xa9: /* test imm,%%eax */ case 0x84 ... 0x85: test: /* test */ - emulate_2op_SrcV("test", src, dst, _regs._eflags); + emulate_2op_SrcV("test", src, dst, _regs.eflags); dst.type =3D OP_NONE; break; =20 @@ -3637,7 +3637,7 @@ x86_emulate( { case 2: _regs.ax =3D (int8_t)_regs.al; break; /* cbw */ case 4: _regs.r(ax) =3D (uint32_t)(int16_t)_regs.ax; break; /* = cwde */ - case 8: _regs.r(ax) =3D (int32_t)_regs._eax; break; /* cdqe */ + case 8: _regs.r(ax) =3D (int32_t)_regs.eax; break; /* cdqe */ } break; =20 @@ -3645,7 +3645,7 @@ x86_emulate( switch ( op_bytes ) { case 2: _regs.dx =3D -((int16_t)_regs.ax < 0); break; - case 4: _regs.r(dx) =3D (uint32_t)-((int32_t)_regs._eax < 0); = break; + case 4: _regs.r(dx) =3D (uint32_t)-((int32_t)_regs.eax < 0); = break; #ifdef __x86_64__ case 8: _regs.rdx =3D -((int64_t)_regs.rax < 0); break; #endif @@ -3669,7 +3669,7 @@ x86_emulate( goto done; =20 _regs.r(ip) =3D imm1; - singlestep =3D _regs._eflags & X86_EFLAGS_TF; + singlestep =3D _regs.eflags & X86_EFLAGS_TF; break; =20 case 0x9b: /* wait/fwait */ @@ -3681,8 +3681,8 @@ x86_emulate( break; =20 case 0x9c: /* pushf */ - if ( (_regs._eflags & X86_EFLAGS_VM) && - MASK_EXTR(_regs._eflags, X86_EFLAGS_IOPL) !=3D 3 ) + if ( (_regs.eflags & X86_EFLAGS_VM) && + MASK_EXTR(_regs.eflags, X86_EFLAGS_IOPL) !=3D 3 ) { cr4 =3D 0; if ( op_bytes =3D=3D 2 && ops->read_cr ) @@ -3693,7 +3693,7 @@ x86_emulate( } generate_exception_if(!(cr4 & X86_CR4_VME), EXC_GP, 0); src.val =3D (_regs.flags & ~X86_EFLAGS_IF) | X86_EFLAGS_IOPL; - if ( _regs._eflags & X86_EFLAGS_VIF ) + if ( _regs.eflags & X86_EFLAGS_VIF ) src.val |=3D X86_EFLAGS_IF; } else @@ -3706,7 +3706,7 @@ x86_emulate( cr4 =3D 0; if ( !mode_ring0() ) { - if ( _regs._eflags & X86_EFLAGS_VM ) + if ( _regs.eflags & X86_EFLAGS_VM ) { if ( op_bytes =3D=3D 2 && ops->read_cr ) { @@ -3715,7 +3715,7 @@ x86_emulate( goto done; } generate_exception_if(!(cr4 & X86_CR4_VME) && - MASK_EXTR(_regs._eflags, X86_EFLAGS_= IOPL) !=3D 3, + MASK_EXTR(_regs.eflags, X86_EFLAGS_I= OPL) !=3D 3, EXC_GP, 0); } mask |=3D X86_EFLAGS_IOPL; @@ -3730,12 +3730,12 @@ x86_emulate( goto done; if ( op_bytes =3D=3D 2 ) { - dst.val =3D (uint16_t)dst.val | (_regs._eflags & 0xffff0000u);= + dst.val =3D (uint16_t)dst.val | (_regs.eflags & 0xffff0000u); if ( cr4 & X86_CR4_VME ) { if ( dst.val & X86_EFLAGS_IF ) { - generate_exception_if(_regs._eflags & X86_EFLAGS_VIP, + generate_exception_if(_regs.eflags & X86_EFLAGS_VIP, EXC_GP, 0); dst.val |=3D X86_EFLAGS_VIF; } @@ -3745,21 +3745,21 @@ x86_emulate( } } dst.val &=3D EFLAGS_MODIFIABLE; - _regs._eflags &=3D mask; - _regs._eflags |=3D (dst.val & ~mask) | X86_EFLAGS_MBS; + _regs.eflags &=3D mask; + _regs.eflags |=3D (dst.val & ~mask) | X86_EFLAGS_MBS; break; } =20 case 0x9e: /* sahf */ if ( mode_64bit() ) vcpu_must_have(lahf_lm); - *(uint8_t *)&_regs._eflags =3D (_regs.ah & EFLAGS_MASK) | = X86_EFLAGS_MBS; + *(uint8_t *)&_regs.eflags =3D (_regs.ah & EFLAGS_MASK) | = X86_EFLAGS_MBS; break; =20 case 0x9f: /* lahf */ if ( mode_64bit() ) vcpu_must_have(lahf_lm); - _regs.ah =3D (_regs._eflags & EFLAGS_MASK) | X86_EFLAGS_MBS; + _regs.ah =3D (_regs.eflags & EFLAGS_MASK) | X86_EFLAGS_MBS; break; =20 case 0xa4 ... 0xa5: /* movs */ { @@ -3802,9 +3802,9 @@ x86_emulate( register_address_adjust(_regs.r(di), src.bytes); put_rep_prefix(1); /* cmp: dst - src =3D=3D> src=3D*%%edi,dst=3D*%%esi =3D=3D> = *%%esi - *%%edi */ - emulate_2op_SrcV("cmp", src, dst, _regs._eflags); - if ( (repe_prefix() && !(_regs._eflags & X86_EFLAGS_ZF)) || - (repne_prefix() && (_regs._eflags & X86_EFLAGS_ZF)) ) + emulate_2op_SrcV("cmp", src, dst, _regs.eflags); + if ( (repe_prefix() && !(_regs.eflags & X86_EFLAGS_ZF)) || + (repne_prefix() && (_regs.eflags & X86_EFLAGS_ZF)) ) _regs.r(ip) =3D next_eip; break; } @@ -3852,9 +3852,9 @@ x86_emulate( put_rep_prefix(1); /* cmp: %%eax - *%%edi =3D=3D> src=3D%%eax,dst=3D*%%edi =3D=3D> = src - dst */ dst.bytes =3D src.bytes; - emulate_2op_SrcV("cmp", dst, src, _regs._eflags); - if ( (repe_prefix() && !(_regs._eflags & X86_EFLAGS_ZF)) || - (repne_prefix() && (_regs._eflags & X86_EFLAGS_ZF)) ) + emulate_2op_SrcV("cmp", dst, src, _regs.eflags); + if ( (repe_prefix() && !(_regs.eflags & X86_EFLAGS_ZF)) || + (repne_prefix() && (_regs.eflags & X86_EFLAGS_ZF)) ) _regs.r(ip) =3D next_eip; break; } @@ -3875,26 +3875,26 @@ x86_emulate( switch ( modrm_reg & 7 ) { case 0: /* rol */ - emulate_2op_SrcB("rol", src, dst, _regs._eflags); + emulate_2op_SrcB("rol", src, dst, _regs.eflags); break; case 1: /* ror */ - emulate_2op_SrcB("ror", src, dst, _regs._eflags); + emulate_2op_SrcB("ror", src, dst, _regs.eflags); break; case 2: /* rcl */ - emulate_2op_SrcB("rcl", src, dst, _regs._eflags); + emulate_2op_SrcB("rcl", src, dst, _regs.eflags); break; case 3: /* rcr */ - emulate_2op_SrcB("rcr", src, dst, _regs._eflags); + emulate_2op_SrcB("rcr", src, dst, _regs.eflags); break; case 4: /* sal/shl */ case 6: /* sal/shl */ - emulate_2op_SrcB("sal", src, dst, _regs._eflags); + emulate_2op_SrcB("sal", src, dst, _regs.eflags); break; case 5: /* shr */ - emulate_2op_SrcB("shr", src, dst, _regs._eflags); + emulate_2op_SrcB("shr", src, dst, _regs.eflags); break; case 7: /* sar */ - emulate_2op_SrcB("sar", src, dst, _regs._eflags); + emulate_2op_SrcB("sar", src, dst, _regs.eflags); break; } break; @@ -3964,7 +3964,7 @@ x86_emulate( if ( dst.bytes =3D=3D 2 ) _regs.sp =3D _regs.bp; else - _regs.r(sp) =3D dst.bytes =3D=3D 4 ? _regs._ebp : _regs.r(bp);= + _regs.r(sp) =3D dst.bytes =3D=3D 4 ? _regs.ebp : _regs.r(bp); =20 /* Second writeback, to %%ebp. */ dst.type =3D OP_REG; @@ -3999,7 +3999,7 @@ x86_emulate( goto done; =20 case 0xce: /* into */ - if ( !(_regs._eflags & X86_EFLAGS_OF) ) + if ( !(_regs.eflags & X86_EFLAGS_OF) ) break; src.val =3D EXC_OF; swint_type =3D x86_swint_into; @@ -4018,10 +4018,10 @@ x86_emulate( &eflags, op_bytes, ctxt, ops)) ) goto done; if ( op_bytes =3D=3D 2 ) - eflags =3D (uint16_t)eflags | (_regs._eflags & 0xffff0000u); + eflags =3D (uint16_t)eflags | (_regs.eflags & 0xffff0000u); eflags &=3D EFLAGS_MODIFIABLE; - _regs._eflags &=3D mask; - _regs._eflags |=3D (eflags & ~mask) | X86_EFLAGS_MBS; + _regs.eflags &=3D mask; + _regs.eflags |=3D (eflags & ~mask) | X86_EFLAGS_MBS; if ( (rc =3D load_seg(x86_seg_cs, sel, 1, &cs, ctxt, ops)) || (rc =3D commit_far_branch(&cs, (uint32_t)eip)) ) goto done; @@ -4053,15 +4053,15 @@ x86_emulate( generate_exception_if(!base, EXC_DE); _regs.ax =3D ((al / base) << 8) | (al % base); } - _regs._eflags &=3D ~(X86_EFLAGS_SF | X86_EFLAGS_ZF | X86_EFLAGS_PF= ); - _regs._eflags |=3D !_regs.al ? X86_EFLAGS_ZF : 0; - _regs._eflags |=3D ((int8_t)_regs.al < 0) ? X86_EFLAGS_SF : 0; - _regs._eflags |=3D even_parity(_regs.al) ? X86_EFLAGS_PF : 0; + _regs.eflags &=3D ~(X86_EFLAGS_SF | X86_EFLAGS_ZF | X86_EFLAGS_PF)= ; + _regs.eflags |=3D !_regs.al ? X86_EFLAGS_ZF : 0; + _regs.eflags |=3D ((int8_t)_regs.al < 0) ? X86_EFLAGS_SF : 0; + _regs.eflags |=3D even_parity(_regs.al) ? X86_EFLAGS_PF : 0; break; } =20 case 0xd6: /* salc */ - _regs.al =3D (_regs._eflags & X86_EFLAGS_CF) ? 0xff : 0x00; + _regs.al =3D (_regs.eflags & X86_EFLAGS_CF) ? 0xff : 0x00; break; =20 case 0xd7: /* xlat */ { @@ -4579,7 +4579,7 @@ x86_emulate( =20 case 0xe0 ... 0xe2: /* loop{,z,nz} */ { unsigned long count =3D get_loop_count(&_regs, ad_bytes); - int do_jmp =3D !(_regs._eflags & X86_EFLAGS_ZF); /* loopnz */ + int do_jmp =3D !(_regs.eflags & X86_EFLAGS_ZF); /* loopnz */ =20 if ( b =3D=3D 0xe1 ) do_jmp =3D !do_jmp; /* loopz */ @@ -4613,7 +4613,7 @@ x86_emulate( { /* out */ fail_if(ops->write_io =3D=3D NULL); - rc =3D ops->write_io(port, op_bytes, _regs._eax, ctxt); + rc =3D ops->write_io(port, op_bytes, _regs.eax, ctxt); } else { @@ -4667,7 +4667,7 @@ x86_emulate( break; =20 case 0xf5: /* cmc */ - _regs._eflags ^=3D X86_EFLAGS_CF; + _regs.eflags ^=3D X86_EFLAGS_CF; break; =20 case 0xf6 ... 0xf7: /* Grp3 */ @@ -4684,32 +4684,32 @@ x86_emulate( dst.val =3D ~dst.val; break; case 3: /* neg */ - emulate_1op("neg", dst, _regs._eflags); + emulate_1op("neg", dst, _regs.eflags); break; case 4: /* mul */ - _regs._eflags &=3D ~(X86_EFLAGS_OF | X86_EFLAGS_CF); + _regs.eflags &=3D ~(X86_EFLAGS_OF | X86_EFLAGS_CF); switch ( dst.bytes ) { case 1: dst.val =3D _regs.al; dst.val *=3D src.val; if ( (uint8_t)dst.val !=3D (uint16_t)dst.val ) - _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; dst.bytes =3D 2; break; case 2: dst.val =3D _regs.ax; dst.val *=3D src.val; if ( (uint16_t)dst.val !=3D (uint32_t)dst.val ) - _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; _regs.dx =3D dst.val >> 16; break; #ifdef __x86_64__ case 4: - dst.val =3D _regs._eax; + dst.val =3D _regs.eax; dst.val *=3D src.val; if ( (uint32_t)dst.val !=3D dst.val ) - _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; _regs.rdx =3D dst.val >> 32; break; #endif @@ -4717,7 +4717,7 @@ x86_emulate( u[0] =3D src.val; u[1] =3D _regs.r(ax); if ( mul_dbl(u) ) - _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; _regs.r(dx) =3D u[1]; dst.val =3D u[0]; break; @@ -4725,13 +4725,13 @@ x86_emulate( break; case 5: /* imul */ imul: - _regs._eflags &=3D ~(X86_EFLAGS_OF | X86_EFLAGS_CF); + _regs.eflags &=3D ~(X86_EFLAGS_OF | X86_EFLAGS_CF); switch ( dst.bytes ) { case 1: dst.val =3D (int8_t)src.val * (int8_t)_regs.al; if ( (int8_t)dst.val !=3D (int16_t)dst.val ) - _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; ASSERT(b > 0x6b); dst.bytes =3D 2; break; @@ -4739,16 +4739,16 @@ x86_emulate( dst.val =3D ((uint32_t)(int16_t)src.val * (uint32_t)(int16_t)_regs.ax); if ( (int16_t)dst.val !=3D (int32_t)dst.val ) - _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; if ( b > 0x6b ) _regs.dx =3D dst.val >> 16; break; #ifdef __x86_64__ case 4: dst.val =3D ((uint64_t)(int32_t)src.val * - (uint64_t)(int32_t)_regs._eax); + (uint64_t)(int32_t)_regs.eax); if ( (int32_t)dst.val !=3D dst.val ) - _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; if ( b > 0x6b ) _regs.rdx =3D dst.val >> 32; break; @@ -4757,7 +4757,7 @@ x86_emulate( u[0] =3D src.val; u[1] =3D _regs.r(ax); if ( imul_dbl(u) ) - _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF; if ( b > 0x6b ) _regs.r(dx) =3D u[1]; dst.val =3D u[0]; @@ -4778,7 +4778,7 @@ x86_emulate( _regs.ah =3D u[1]; break; case 2: - u[0] =3D (_regs._edx << 16) | _regs.ax; + u[0] =3D (_regs.edx << 16) | _regs.ax; u[1] =3D 0; v =3D (uint16_t)src.val; generate_exception_if( @@ -4789,7 +4789,7 @@ x86_emulate( break; #ifdef __x86_64__ case 4: - u[0] =3D (_regs.rdx << 32) | _regs._eax; + u[0] =3D (_regs.rdx << 32) | _regs.eax; u[1] =3D 0; v =3D (uint32_t)src.val; generate_exception_if( @@ -4823,7 +4823,7 @@ x86_emulate( _regs.ah =3D u[1]; break; case 2: - u[0] =3D (int32_t)((_regs._edx << 16) | _regs.ax); + u[0] =3D (int32_t)((_regs.edx << 16) | _regs.ax); u[1] =3D ((long)u[0] < 0) ? ~0UL : 0UL; v =3D (int16_t)src.val; generate_exception_if( @@ -4834,7 +4834,7 @@ x86_emulate( break; #ifdef __x86_64__ case 4: - u[0] =3D (_regs.rdx << 32) | _regs._eax; + u[0] =3D (_regs.rdx << 32) | _regs.eax; u[1] =3D ((long)u[0] < 0) ? ~0UL : 0UL; v =3D (int32_t)src.val; generate_exception_if( @@ -4858,47 +4858,47 @@ x86_emulate( break; =20 case 0xf8: /* clc */ - _regs._eflags &=3D ~X86_EFLAGS_CF; + _regs.eflags &=3D ~X86_EFLAGS_CF; break; =20 case 0xf9: /* stc */ - _regs._eflags |=3D X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_CF; break; =20 case 0xfa: /* cli */ if ( mode_iopl() ) - _regs._eflags &=3D ~X86_EFLAGS_IF; + _regs.eflags &=3D ~X86_EFLAGS_IF; else { generate_exception_if(!mode_vif(), EXC_GP, 0); - _regs._eflags &=3D ~X86_EFLAGS_VIF; + _regs.eflags &=3D ~X86_EFLAGS_VIF; } break; =20 case 0xfb: /* sti */ if ( mode_iopl() ) { - if ( !(_regs._eflags & X86_EFLAGS_IF) ) + if ( !(_regs.eflags & X86_EFLAGS_IF) ) ctxt->retire.sti =3D true; - _regs._eflags |=3D X86_EFLAGS_IF; + _regs.eflags |=3D X86_EFLAGS_IF; } else { - generate_exception_if((_regs._eflags & X86_EFLAGS_VIP) || + generate_exception_if((_regs.eflags & X86_EFLAGS_VIP) || !mode_vif(), EXC_GP, 0); - if ( !(_regs._eflags & X86_EFLAGS_VIF) ) + if ( !(_regs.eflags & X86_EFLAGS_VIF) ) ctxt->retire.sti =3D true; - _regs._eflags |=3D X86_EFLAGS_VIF; + _regs.eflags |=3D X86_EFLAGS_VIF; } break; =20 case 0xfc: /* cld */ - _regs._eflags &=3D ~X86_EFLAGS_DF; + _regs.eflags &=3D ~X86_EFLAGS_DF; break; =20 case 0xfd: /* std */ - _regs._eflags |=3D X86_EFLAGS_DF; + _regs.eflags |=3D X86_EFLAGS_DF; break; =20 case 0xfe: /* Grp4 */ @@ -4908,10 +4908,10 @@ x86_emulate( switch ( modrm_reg & 7 ) { case 0: /* inc */ - emulate_1op("inc", dst, _regs._eflags); + emulate_1op("inc", dst, _regs.eflags); break; case 1: /* dec */ - emulate_1op("dec", dst, _regs._eflags); + emulate_1op("dec", dst, _regs.eflags); break; case 2: /* call (near) */ dst.val =3D _regs.r(ip); @@ -4960,7 +4960,7 @@ x86_emulate( goto done; break; case 4: /* verr / verw */ - _regs._eflags &=3D ~X86_EFLAGS_ZF; + _regs.eflags &=3D ~X86_EFLAGS_ZF; switch ( rc =3D protmode_load_seg(x86_seg_none, src.val, = false, &sreg, ctxt, ops) ) { @@ -4968,7 +4968,7 @@ x86_emulate( if ( sreg.attr.fields.s && ((modrm_reg & 1) ? ((sreg.attr.fields.type & 0xa) = =3D=3D 0x2) : ((sreg.attr.fields.type & 0xa) = !=3D 0x8)) ) - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; break; case X86EMUL_EXCEPTION: if ( ctxt->event_pending ) @@ -4998,9 +4998,9 @@ x86_emulate( vcpu_must_have(smap); generate_exception_if(vex.pfx || !mode_ring0(), EXC_UD); =20 - _regs._eflags &=3D ~X86_EFLAGS_AC; + _regs.eflags &=3D ~X86_EFLAGS_AC; if ( modrm =3D=3D 0xcb ) - _regs._eflags |=3D X86_EFLAGS_AC; + _regs.eflags |=3D X86_EFLAGS_AC; goto complete_insn; =20 #ifdef __XEN__ @@ -5010,8 +5010,8 @@ x86_emulate( cr4 =3D 0; generate_exception_if(!(cr4 & X86_CR4_OSXSAVE), EXC_UD); generate_exception_if(!mode_ring0() || - handle_xsetbv(_regs._ecx, - _regs._eax | (_regs.rdx = << 32)), + handle_xsetbv(_regs.ecx, + _regs.eax | (_regs.rdx << = 32)), EXC_GP, 0); goto complete_insn; #endif @@ -5034,7 +5034,7 @@ x86_emulate( generate_exception_if(!vcpu_has_rtm() && !vcpu_has_hle(), EXC_UD); /* Neither HLE nor RTM can be active when we get here. */ - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; goto complete_insn; =20 case 0xdf: /* invlpga */ @@ -5059,7 +5059,7 @@ x86_emulate( unsigned long zero =3D 0; =20 base =3D ad_bytes =3D=3D 8 ? _regs.r(ax) : - ad_bytes =3D=3D 4 ? _regs._eax : _regs.ax; + ad_bytes =3D=3D 4 ? _regs.eax : _regs.ax; limit =3D 0; if ( vcpu_has_clflush() && ops->cpuid(1, 0, &cpuid_leaf, ctxt) =3D=3D X86EMUL_OKAY = ) @@ -5183,7 +5183,7 @@ x86_emulate( =20 case X86EMUL_OPC(0x0f, 0x02): /* lar */ generate_exception_if(!in_protmode(ctxt, ops), EXC_UD); - _regs._eflags &=3D ~X86_EFLAGS_ZF; + _regs.eflags &=3D ~X86_EFLAGS_ZF; switch ( rc =3D protmode_load_seg(x86_seg_none, src.val, false, = &sreg, ctxt, ops) ) { @@ -5203,12 +5203,12 @@ x86_emulate( case 0x09: /* available 32/64-bit TSS */ case 0x0b: /* busy 32/64-bit TSS */ case 0x0c: /* 32/64-bit call gate */ - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; break; } } else - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; break; case X86EMUL_EXCEPTION: if ( ctxt->event_pending ) @@ -5221,7 +5221,7 @@ x86_emulate( rc =3D X86EMUL_OKAY; break; } - if ( _regs._eflags & X86_EFLAGS_ZF ) + if ( _regs.eflags & X86_EFLAGS_ZF ) dst.val =3D ((sreg.attr.bytes & 0xff) << 8) | ((sreg.limit >> (sreg.attr.fields.g ? 12 : 0)) & 0xf0000) | @@ -5232,7 +5232,7 @@ x86_emulate( =20 case X86EMUL_OPC(0x0f, 0x03): /* lsl */ generate_exception_if(!in_protmode(ctxt, ops), EXC_UD); - _regs._eflags &=3D ~X86_EFLAGS_ZF; + _regs.eflags &=3D ~X86_EFLAGS_ZF; switch ( rc =3D protmode_load_seg(x86_seg_none, src.val, false, = &sreg, ctxt, ops) ) { @@ -5249,12 +5249,12 @@ x86_emulate( case 0x02: /* LDT */ case 0x09: /* available 32/64-bit TSS */ case 0x0b: /* busy 32/64-bit TSS */ - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; break; } } else - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; break; case X86EMUL_EXCEPTION: if ( ctxt->event_pending ) @@ -5267,7 +5267,7 @@ x86_emulate( rc =3D X86EMUL_OKAY; break; } - if ( _regs._eflags & X86_EFLAGS_ZF ) + if ( _regs.eflags & X86_EFLAGS_ZF ) dst.val =3D sreg.limit; else dst.type =3D OP_NONE; @@ -5301,7 +5301,7 @@ x86_emulate( cs.attr.bytes =3D 0xa9b; /* L+DB+P+S+Code */ =20 _regs.rcx =3D _regs.rip; - _regs.r11 =3D _regs._eflags & ~X86_EFLAGS_RF; + _regs.r11 =3D _regs.eflags & ~X86_EFLAGS_RF; =20 if ( (rc =3D ops->read_msr(mode_64bit() ? MSR_LSTAR : = MSR_CSTAR, &msr_val, ctxt)) !=3D X86EMUL_OKAY ) @@ -5311,16 +5311,16 @@ x86_emulate( if ( (rc =3D ops->read_msr(MSR_SYSCALL_MASK, &msr_val, ctxt)) !=3D X86EMUL_OKAY ) goto done; - _regs._eflags &=3D ~(msr_val | X86_EFLAGS_RF); + _regs.eflags &=3D ~(msr_val | X86_EFLAGS_RF); } else #endif { cs.attr.bytes =3D 0xc9b; /* G+DB+P+S+Code */ =20 - _regs.r(cx) =3D _regs._eip; - _regs._eip =3D msr_val; - _regs._eflags &=3D ~(X86_EFLAGS_VM | X86_EFLAGS_IF | = X86_EFLAGS_RF); + _regs.r(cx) =3D _regs.eip; + _regs.eip =3D msr_val; + _regs.eflags &=3D ~(X86_EFLAGS_VM | X86_EFLAGS_IF | X86_EFLAGS= _RF); } =20 fail_if(ops->write_segment =3D=3D NULL); @@ -5343,7 +5343,7 @@ x86_emulate( * Their only mitigation is to use a task gate for handling * #DB (or to not use enable EFER.SCE to start with). */ - singlestep =3D _regs._eflags & X86_EFLAGS_TF; + singlestep =3D _regs.eflags & X86_EFLAGS_TF; break; =20 case X86EMUL_OPC(0x0f, 0x06): /* clts */ @@ -5695,8 +5695,8 @@ x86_emulate( case X86EMUL_OPC(0x0f, 0x30): /* wrmsr */ generate_exception_if(!mode_ring0(), EXC_GP, 0); fail_if(ops->write_msr =3D=3D NULL); - if ( (rc =3D ops->write_msr(_regs._ecx, - ((uint64_t)_regs.r(dx) << 32) | = _regs._eax, + if ( (rc =3D ops->write_msr(_regs.ecx, + ((uint64_t)_regs.r(dx) << 32) | = _regs.eax, ctxt)) !=3D 0 ) goto done; break; @@ -5720,7 +5720,7 @@ x86_emulate( case X86EMUL_OPC(0x0f, 0x32): /* rdmsr */ generate_exception_if(!mode_ring0(), EXC_GP, 0); fail_if(ops->read_msr =3D=3D NULL); - if ( (rc =3D ops->read_msr(_regs._ecx, &msr_val, ctxt)) !=3D = X86EMUL_OKAY ) + if ( (rc =3D ops->read_msr(_regs.ecx, &msr_val, ctxt)) !=3D = X86EMUL_OKAY ) goto done; _regs.r(dx) =3D msr_val >> 32; _regs.r(ax) =3D (uint32_t)msr_val; @@ -5728,7 +5728,7 @@ x86_emulate( =20 case X86EMUL_OPC(0x0f, 0x40) ... X86EMUL_OPC(0x0f, 0x4f): /* cmovcc = */ vcpu_must_have(cmov); - if ( test_cc(b, _regs._eflags) ) + if ( test_cc(b, _regs.eflags) ) dst.val =3D src.val; break; =20 @@ -5749,7 +5749,7 @@ x86_emulate( if ( lm < 0 ) goto cannot_emulate; =20 - _regs._eflags &=3D ~(X86_EFLAGS_VM | X86_EFLAGS_IF | X86_EFLAGS_RF= ); + _regs.eflags &=3D ~(X86_EFLAGS_VM | X86_EFLAGS_IF | X86_EFLAGS_RF)= ; =20 cs.sel =3D msr_val & ~3; /* SELECTOR_RPL_MASK */ cs.base =3D 0; /* flat segment */ @@ -5777,7 +5777,7 @@ x86_emulate( goto done; _regs.r(sp) =3D lm ? msr_val : (uint32_t)msr_val; =20 - singlestep =3D _regs._eflags & X86_EFLAGS_TF; + singlestep =3D _regs.eflags & X86_EFLAGS_TF; break; } =20 @@ -5814,10 +5814,10 @@ x86_emulate( (rc =3D ops->write_segment(x86_seg_ss, &sreg, ctxt)) !=3D 0 = ) goto done; =20 - _regs.r(ip) =3D op_bytes =3D=3D 8 ? _regs.r(dx) : _regs._edx; - _regs.r(sp) =3D op_bytes =3D=3D 8 ? _regs.r(cx) : _regs._ecx; + _regs.r(ip) =3D op_bytes =3D=3D 8 ? _regs.r(dx) : _regs.edx; + _regs.r(sp) =3D op_bytes =3D=3D 8 ? _regs.r(cx) : _regs.ecx; =20 - singlestep =3D _regs._eflags & X86_EFLAGS_TF; + singlestep =3D _regs.eflags & X86_EFLAGS_TF; break; =20 CASE_SIMD_PACKED_FP(, 0x0f, 0x50): /* movmskp{s,d} xmm,reg */ @@ -6325,13 +6325,13 @@ x86_emulate( goto simd_0f_sse3_avx; =20 case X86EMUL_OPC(0x0f, 0x80) ... X86EMUL_OPC(0x0f, 0x8f): /* jcc = (near) */ - if ( test_cc(b, _regs._eflags) ) + if ( test_cc(b, _regs.eflags) ) jmp_rel((int32_t)src.val); adjust_bnd(ctxt, ops, vex.pfx); break; =20 case X86EMUL_OPC(0x0f, 0x90) ... X86EMUL_OPC(0x0f, 0x9f): /* setcc */ - dst.val =3D test_cc(b, _regs._eflags); + dst.val =3D test_cc(b, _regs.eflags); break; =20 case X86EMUL_OPC(0x0f, 0xa2): /* cpuid */ @@ -6353,7 +6353,7 @@ x86_emulate( generate_exception_if((msr_val & MSR_MISC_FEATURES_CPUID_FAULTING)= , EXC_GP, 0); /* Faulting active? (Inc. CPL = test) */ =20 - rc =3D ops->cpuid(_regs._eax, _regs._ecx, &cpuid_leaf, ctxt); + rc =3D ops->cpuid(_regs.eax, _regs.ecx, &cpuid_leaf, ctxt); if ( rc !=3D X86EMUL_OKAY ) goto done; _regs.r(ax) =3D cpuid_leaf.a; @@ -6364,7 +6364,7 @@ x86_emulate( =20 case X86EMUL_OPC(0x0f, 0xa3): bt: /* bt */ generate_exception_if(lock_prefix, EXC_UD); - emulate_2op_SrcV_nobyte("bt", src, dst, _regs._eflags); + emulate_2op_SrcV_nobyte("bt", src, dst, _regs.eflags); dst.type =3D OP_NONE; break; =20 @@ -6395,20 +6395,20 @@ x86_emulate( ((dst.orig_val << shift) | ((src.val >> (width - shift)) & ((1ull << shift) - = 1)))); dst.val =3D truncate_word(dst.val, dst.bytes); - _regs._eflags &=3D ~(X86_EFLAGS_OF | X86_EFLAGS_SF | X86_EFLAGS_ZF= | + _regs.eflags &=3D ~(X86_EFLAGS_OF | X86_EFLAGS_SF | X86_EFLAGS_ZF = | X86_EFLAGS_PF | X86_EFLAGS_CF); if ( (dst.val >> ((b & 8) ? (shift - 1) : (width - shift))) & 1 ) - _regs._eflags |=3D X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_CF; if ( ((dst.val ^ dst.orig_val) >> (width - 1)) & 1 ) - _regs._eflags |=3D X86_EFLAGS_OF; - _regs._eflags |=3D ((dst.val >> (width - 1)) & 1) ? X86_EFLAGS_SF = : 0; - _regs._eflags |=3D (dst.val =3D=3D 0) ? X86_EFLAGS_ZF : 0; - _regs._eflags |=3D even_parity(dst.val) ? X86_EFLAGS_PF : 0; + _regs.eflags |=3D X86_EFLAGS_OF; + _regs.eflags |=3D ((dst.val >> (width - 1)) & 1) ? X86_EFLAGS_SF = : 0; + _regs.eflags |=3D (dst.val =3D=3D 0) ? X86_EFLAGS_ZF : 0; + _regs.eflags |=3D even_parity(dst.val) ? X86_EFLAGS_PF : 0; break; } =20 case X86EMUL_OPC(0x0f, 0xab): bts: /* bts */ - emulate_2op_SrcV_nobyte("bts", src, dst, _regs._eflags); + emulate_2op_SrcV_nobyte("bts", src, dst, _regs.eflags); break; =20 case X86EMUL_OPC(0x0f, 0xae): case X86EMUL_OPC_66(0x0f, 0xae): /* = Grp15 */ @@ -6525,7 +6525,7 @@ x86_emulate( break; =20 case X86EMUL_OPC(0x0f, 0xaf): /* imul */ - emulate_2op_SrcV_srcmem("imul", src, dst, _regs._eflags); + emulate_2op_SrcV_srcmem("imul", src, dst, _regs.eflags); break; =20 case X86EMUL_OPC(0x0f, 0xb0): case X86EMUL_OPC(0x0f, 0xb1): /* = cmpxchg */ @@ -6533,8 +6533,8 @@ x86_emulate( src.orig_val =3D src.val; src.val =3D _regs.r(ax); /* cmp: %%eax - dst =3D=3D> dst and src swapped for macro = invocation */ - emulate_2op_SrcV("cmp", dst, src, _regs._eflags); - if ( _regs._eflags & X86_EFLAGS_ZF ) + emulate_2op_SrcV("cmp", dst, src, _regs.eflags); + if ( _regs.eflags & X86_EFLAGS_ZF ) { /* Success: write back to memory. */ dst.val =3D src.orig_val; @@ -6554,7 +6554,7 @@ x86_emulate( goto les; =20 case X86EMUL_OPC(0x0f, 0xb3): btr: /* btr */ - emulate_2op_SrcV_nobyte("btr", src, dst, _regs._eflags); + emulate_2op_SrcV_nobyte("btr", src, dst, _regs.eflags); break; =20 case X86EMUL_OPC(0x0f, 0xb6): /* movzx rm8,r{16,32,64} */ @@ -6571,9 +6571,9 @@ x86_emulate( case X86EMUL_OPC_F3(0x0f, 0xb8): /* popcnt r/m,r */ host_and_vcpu_must_have(popcnt); asm ( "popcnt %1,%0" : "=3Dr" (dst.val) : "rm" (src.val) ); - _regs._eflags &=3D ~EFLAGS_MASK; + _regs.eflags &=3D ~EFLAGS_MASK; if ( !dst.val ) - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; break; =20 case X86EMUL_OPC(0x0f, 0xba): /* Grp8 */ @@ -6588,7 +6588,7 @@ x86_emulate( break; =20 case X86EMUL_OPC(0x0f, 0xbb): btc: /* btc */ - emulate_2op_SrcV_nobyte("btc", src, dst, _regs._eflags); + emulate_2op_SrcV_nobyte("btc", src, dst, _regs.eflags); break; =20 case X86EMUL_OPC(0x0f, 0xbc): /* bsf or tzcnt */ @@ -6598,21 +6598,21 @@ x86_emulate( asm ( "bsf %2,%0" ASM_FLAG_OUT(, "; setz %1") : "=3Dr" (dst.val), ASM_FLAG_OUT("=3D@ccz", "=3Dqm") (zf) : "rm" (src.val) ); - _regs._eflags &=3D ~X86_EFLAGS_ZF; + _regs.eflags &=3D ~X86_EFLAGS_ZF; if ( (vex.pfx =3D=3D vex_f3) && vcpu_has_bmi1() ) { - _regs._eflags &=3D ~X86_EFLAGS_CF; + _regs.eflags &=3D ~X86_EFLAGS_CF; if ( zf ) { - _regs._eflags |=3D X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_CF; dst.val =3D op_bytes * 8; } else if ( !dst.val ) - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; } else if ( zf ) { - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; dst.type =3D OP_NONE; } break; @@ -6625,25 +6625,25 @@ x86_emulate( asm ( "bsr %2,%0" ASM_FLAG_OUT(, "; setz %1") : "=3Dr" (dst.val), ASM_FLAG_OUT("=3D@ccz", "=3Dqm") (zf) : "rm" (src.val) ); - _regs._eflags &=3D ~X86_EFLAGS_ZF; + _regs.eflags &=3D ~X86_EFLAGS_ZF; if ( (vex.pfx =3D=3D vex_f3) && vcpu_has_lzcnt() ) { - _regs._eflags &=3D ~X86_EFLAGS_CF; + _regs.eflags &=3D ~X86_EFLAGS_CF; if ( zf ) { - _regs._eflags |=3D X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_CF; dst.val =3D op_bytes * 8; } else { dst.val =3D op_bytes * 8 - 1 - dst.val; if ( !dst.val ) - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; } } else if ( zf ) { - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; dst.type =3D OP_NONE; } break; @@ -6754,9 +6754,9 @@ x86_emulate( : "=3Dr" (dst.val), ASM_FLAG_OUT("=3D@ccc", = "=3Dqm") (carry) ); break; } - _regs._eflags &=3D ~EFLAGS_MASK; + _regs.eflags &=3D ~EFLAGS_MASK; if ( carry ) - _regs._eflags |=3D X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_CF; break; #endif =20 @@ -6795,9 +6795,9 @@ x86_emulate( : "=3Dr" (dst.val), ASM_FLAG_OUT("=3D@ccc", = "=3Dqm") (carry) ); break; } - _regs._eflags &=3D ~EFLAGS_MASK; + _regs.eflags &=3D ~EFLAGS_MASK; if ( carry ) - _regs._eflags |=3D X86_EFLAGS_CF; + _regs.eflags |=3D X86_EFLAGS_CF; break; #endif } @@ -6832,8 +6832,8 @@ x86_emulate( /* Get expected value. */ if ( !(rex_prefix & REX_W) ) { - aux->u32[0] =3D _regs._eax; - aux->u32[1] =3D _regs._edx; + aux->u32[0] =3D _regs.eax; + aux->u32[1] =3D _regs.edx; } else { @@ -6846,7 +6846,7 @@ x86_emulate( /* Expected !=3D actual: store actual to rDX:rAX and clear = ZF. */ _regs.r(ax) =3D !(rex_prefix & REX_W) ? old->u32[0] : = old->u64[0]; _regs.r(dx) =3D !(rex_prefix & REX_W) ? old->u32[1] : = old->u64[1]; - _regs._eflags &=3D ~X86_EFLAGS_ZF; + _regs.eflags &=3D ~X86_EFLAGS_ZF; } else { @@ -6856,8 +6856,8 @@ x86_emulate( */ if ( !(rex_prefix & REX_W) ) { - aux->u32[0] =3D _regs._ebx; - aux->u32[1] =3D _regs._ecx; + aux->u32[0] =3D _regs.ebx; + aux->u32[1] =3D _regs.ecx; } else { @@ -6868,7 +6868,7 @@ x86_emulate( if ( (rc =3D ops->cmpxchg(ea.mem.seg, ea.mem.off, old, aux, op_bytes, ctxt)) !=3D X86EMUL_OKAY ) goto done; - _regs._eflags |=3D X86_EFLAGS_ZF; + _regs.eflags |=3D X86_EFLAGS_ZF; } break; } @@ -7340,7 +7340,7 @@ x86_emulate( case X86EMUL_OPC_F3(0x0f38, 0xf6): /* adox r/m,r */ { unsigned int mask =3D rep_prefix() ? X86_EFLAGS_OF : X86_EFLAGS_CF= ; - unsigned int aux =3D _regs._eflags & mask ? ~0 : 0; + unsigned int aux =3D _regs.eflags & mask ? ~0 : 0; bool carry; =20 vcpu_must_have(adx); @@ -7363,9 +7363,9 @@ x86_emulate( [aux] "+r" (aux) : [src] "rm" (src.val) ); if ( carry ) - _regs._eflags |=3D mask; + _regs.eflags |=3D mask; else - _regs._eflags &=3D ~mask; + _regs.eflags &=3D ~mask; break; } =20 @@ -7378,7 +7378,7 @@ x86_emulate( : "0" (src.val), "rm" (_regs.r(dx)) ); else asm ( "mull %3" : "=3Da" (*ea.reg), "=3Dd" (dst.val) - : "0" ((uint32_t)src.val), "rm" (_regs._edx) = ); + : "0" ((uint32_t)src.val), "rm" (_regs.edx) = ); break; =20 case X86EMUL_OPC(0x0f3a, 0x0f): /* palignr $imm8,mm/m64,mm */ @@ -7811,7 +7811,7 @@ x86_emulate( complete_insn: /* Commit shadow register state. */ /* Zero the upper 32 bits of %rip if not in 64-bit mode. */ if ( !mode_64bit() ) - _regs.r(ip) =3D _regs._eip; + _regs.r(ip) =3D _regs.eip; =20 /* Should a singlestep #DB be raised? */ if ( rc =3D=3D X86EMUL_OKAY && singlestep && !ctxt->retire.mov_ss ) @@ -7828,7 +7828,7 @@ x86_emulate( rc =3D X86EMUL_OKAY; } =20 - ctxt->regs->_eflags &=3D ~X86_EFLAGS_RF; + ctxt->regs->eflags &=3D ~X86_EFLAGS_RF; =20 done: _put_fpu(); --=__PartA49D4FC8.1__= Content-Type: text/plain; name="x86emul-regnames.patch" Content-Transfer-Encoding: quoted-printable Content-Disposition: attachment; filename="x86emul-regnames.patch" x86emul: switch away from temporary 32-bit register names=0A=0ASigned-off-b= y: Jan Beulich =0A=0A--- a/xen/arch/x86/x86_emulate/x86_= emulate.c=0A+++ b/xen/arch/x86/x86_emulate/x86_emulate.c=0A@@ -811,7 = +811,7 @@ do{ asm volatile (=0A unsigned long tmp; = \=0A invoke_stub(_PRE_EFLAGS("[efl]", = "[msk]", "[tmp]"), \=0A _POST_EFLAGS("[efl]= ", "[msk]", "[tmp]"), \=0A- dst, [tmp] = "=3D&r" (tmp), [efl] "+g" (_regs._eflags) \=0A+ dst, = [tmp] "=3D&r" (tmp), [efl] "+g" (_regs.eflags) \=0A = : [msk] "i" (EFLAGS_MASK), ## src); \=0A } while = (0)=0A =0A@@ -890,7 +890,7 @@ do {=0A } while (0)=0A #define register_addre= ss_adjust(reg, adj) \=0A _register_addres= s_increment(reg, \=0A- = _regs._eflags & X86_EFLAGS_DF ? \=0A+ = _regs.eflags & X86_EFLAGS_DF ? \=0A = -(adj) : (adj), \=0A = ad_bytes)=0A =0A@@ -914,7 +914,7 @@ do {=0A rc =3D = ops->insn_fetch(x86_seg_cs, ip, NULL, 0, ctxt); \=0A if = ( rc ) goto done; \=0A = _regs.r(ip) =3D ip; = \=0A- singlestep =3D _regs._eflags & X86_EFLAGS_TF; = \=0A+ singlestep =3D _regs.eflags & X86_EFLAGS_TF; = \=0A } while (0)=0A =0A #define validate_far_branch(cs, ip) ({ = \=0A@@ -931,7 +931,7 @@ do {=0A #define = commit_far_branch(cs, newip) ({ \=0A = validate_far_branch(cs, newip); \=0A = _regs.r(ip) =3D (newip); = \=0A- singlestep =3D _regs._eflags & X86_EFLAGS_TF; = \=0A+ singlestep =3D _regs.eflags & X86_EFLAGS_TF; = \=0A ops->write_segment(x86_seg_cs, cs, ctxt); = \=0A })=0A =0A@@ -984,7 +984,7 @@ static int _get_fpu(=0A = if ( type >=3D X86EMUL_FPU_ymm )=0A {=0A /* Should be = unreachable if VEX decoding is working correctly. */=0A- = ASSERT((cr0 & X86_CR0_PE) && !(ctxt->regs->_eflags & X86_EFLAGS_VM));=0A+ = ASSERT((cr0 & X86_CR0_PE) && !(ctxt->regs->eflags & X86_EFLAGS_VM= ));=0A }=0A if ( cr0 & X86_CR0_EM )=0A {=0A@@ = -1071,7 +1071,7 @@ do {=0A memcpy(get_stub(stub), ((uint8_t[]){ bytes, = 0xc3 }), nr_ + 1); \=0A invoke_stub(_PRE_EFLAGS("[eflags]", = "[mask]", "[tmp]"), \=0A _POST_EFLAGS("[eflags]= ", "[mask]", "[tmp]"), \=0A- [eflags] "+g" = (_regs._eflags), [tmp] "=3D&r" (tmp_), \=0A+ [eflags] = "+g" (_regs.eflags), [tmp] "=3D&r" (tmp_), \=0A "+m" = (fic) \=0A : = [mask] "i" (X86_EFLAGS_ZF|X86_EFLAGS_PF|X86_EFLAGS_CF)); \=0A = put_stub(stub); \=0A@@ = -1082,7 +1082,7 @@ static inline unsigned long get_loop_cou=0A int = ad_bytes)=0A {=0A return (ad_bytes > 4) ? regs->r(cx)=0A- = : (ad_bytes < 4) ? regs->cx : regs->_ecx;=0A+ = : (ad_bytes < 4) ? regs->cx : regs->ecx;=0A }=0A =0A static inline = void put_loop_count(=0A@@ -1110,12 +1110,12 @@ static inline void = put_loop_count(=0A if ( mode_64bit() && ad_bytes =3D=3D 4 ) = \=0A { = \=0A _regs.r(cx) =3D 0; = \=0A- if ( using_si ) _regs.r(si) =3D = _regs._esi; \=0A- if ( using_di ) _regs.r(di) = =3D _regs._edi; \=0A+ if ( using_si ) = _regs.r(si) =3D _regs.esi; \=0A+ if ( = using_di ) _regs.r(di) =3D _regs.edi; \=0A } = \=0A = goto complete_insn; \=0A } = \=0A- = if ( max_reps > 1 && (_regs._eflags & X86_EFLAGS_TF) && \=0A+ = if ( max_reps > 1 && (_regs.eflags & X86_EFLAGS_TF) && \=0A = !is_branch_step(ctxt, ops) ) = \=0A max_reps =3D 1; = \=0A max_reps; = \=0A@@ -1149,7 +1149,7 @@ static void __put_rep_prefix(=0A /* Clip = maximum repetitions so that the index register at most just wraps. */=0A = #define truncate_ea_and_reps(ea, reps, bytes_per_rep) ({ = \=0A unsigned long todo__, ea__ =3D truncate_word(ea, ad_bytes); = \=0A- if ( !(_regs._eflags & X86_EFLAGS_DF) ) = \=0A+ if ( !(_regs.eflags & X86_EFLAGS_DF) ) = \=0A todo__ =3D truncate_word(-(ea), ad_bytes) / = (bytes_per_rep); \=0A else if ( truncate_word((ea) + (bytes_per_= rep) - 1, ad_bytes) < ea__ )\=0A todo__ =3D 1; = \=0A@@ -1306,7 +1306,7 @@ get_cpl(=0A = {=0A struct segment_register reg;=0A =0A- if ( ctxt->regs->_eflags = & X86_EFLAGS_VM )=0A+ if ( ctxt->regs->eflags & X86_EFLAGS_VM )=0A = return 3;=0A =0A if ( (ops->read_segment =3D=3D NULL) ||=0A@@ = -1324,7 +1324,7 @@ _mode_iopl(=0A int cpl =3D get_cpl(ctxt, ops);=0A = if ( cpl =3D=3D -1 )=0A return -1;=0A- return cpl <=3D = MASK_EXTR(ctxt->regs->_eflags, X86_EFLAGS_IOPL);=0A+ return cpl <=3D = MASK_EXTR(ctxt->regs->eflags, X86_EFLAGS_IOPL);=0A }=0A =0A #define = mode_ring0() ({ \=0A@@ -1344,7 +1344,7 @@ = _mode_iopl(=0A rc =3D ops->read_cr(4, &cr4, ctxt); = \=0A if ( rc !=3D X86EMUL_OKAY ) goto done; = \=0A } \=0A- = !!(cr4 & (_regs._eflags & X86_EFLAGS_VM ? X86_CR4_VME : X86_CR4_PVI)); = \=0A+ !!(cr4 & (_regs.eflags & X86_EFLAGS_VM ? X86_CR4_VME : X86_CR4_PVI= )); \=0A })=0A =0A static int ioport_access_check(=0A@@ -1357,7 +1357,7 @@ = static int ioport_access_check(=0A struct segment_register tr;=0A = int rc =3D X86EMUL_OKAY;=0A =0A- if ( !(ctxt->regs->_eflags & X86_EFLAGS= _VM) && mode_iopl() )=0A+ if ( !(ctxt->regs->eflags & X86_EFLAGS_VM) && = mode_iopl() )=0A return X86EMUL_OKAY;=0A =0A fail_if(ops->read_= segment =3D=3D NULL);=0A@@ -1426,7 +1426,7 @@ in_protmode(=0A struct = x86_emulate_ctxt *ctxt,=0A const struct x86_emulate_ops *ops)=0A = {=0A- return !(in_realmode(ctxt, ops) || (ctxt->regs->_eflags & = X86_EFLAGS_VM));=0A+ return !(in_realmode(ctxt, ops) || (ctxt->regs->efl= ags & X86_EFLAGS_VM));=0A }=0A =0A #define EAX 0=0A@@ -1958,8 +1958,8 @@ = static int inject_swint(enum x86_swint_t=0A * a 32bit OS. = Someone with many TUITs can see about reading the=0A * TSS = Software Interrupt Redirection bitmap.=0A */=0A- = if ( (ctxt->regs->_eflags & X86_EFLAGS_VM) &&=0A- = ((ctxt->regs->_eflags & X86_EFLAGS_IOPL) !=3D X86_EFLAGS_IOPL) )=0A+ = if ( (ctxt->regs->eflags & X86_EFLAGS_VM) &&=0A+ = ((ctxt->regs->eflags & X86_EFLAGS_IOPL) !=3D X86_EFLAGS_IOPL) )=0A = goto raise_exn;=0A =0A /*=0A@@ -2524,7 +2524,7 @@ = x86_decode(=0A default:=0A BUG(); /* Shouldn't = be possible. */=0A case 2:=0A- if ( state->regs-= >_eflags & X86_EFLAGS_VM )=0A+ if ( state->regs->eflags & = X86_EFLAGS_VM )=0A break;=0A /* fall = through */=0A case 4:=0A@@ -2977,7 +2977,7 @@ x86_emulate(=0A = struct x86_emulate_state state;=0A int rc;=0A uint8_t b, d, = *opc =3D NULL;=0A- bool singlestep =3D (_regs._eflags & X86_EFLAGS_TF) = &&=0A+ bool singlestep =3D (_regs.eflags & X86_EFLAGS_TF) &&=0A = !is_branch_step(ctxt, ops);=0A bool sfence =3D false;=0A struct = operand src =3D { .reg =3D PTR_POISON };=0A@@ -3199,36 +3199,36 @@ = x86_emulate(=0A unsigned long dummy;=0A =0A case 0x00 ... = 0x05: add: /* add */=0A- emulate_2op_SrcV("add", src, dst, = _regs._eflags);=0A+ emulate_2op_SrcV("add", src, dst, _regs.eflags);= =0A break;=0A =0A case 0x08 ... 0x0d: or: /* or */=0A- = emulate_2op_SrcV("or", src, dst, _regs._eflags);=0A+ emulate_2op_Src= V("or", src, dst, _regs.eflags);=0A break;=0A =0A case 0x10 = ... 0x15: adc: /* adc */=0A- emulate_2op_SrcV("adc", src, dst, = _regs._eflags);=0A+ emulate_2op_SrcV("adc", src, dst, _regs.eflags);= =0A break;=0A =0A case 0x18 ... 0x1d: sbb: /* sbb */=0A- = emulate_2op_SrcV("sbb", src, dst, _regs._eflags);=0A+ emulate_2op_S= rcV("sbb", src, dst, _regs.eflags);=0A break;=0A =0A case 0x20 = ... 0x25: and: /* and */=0A- emulate_2op_SrcV("and", src, dst, = _regs._eflags);=0A+ emulate_2op_SrcV("and", src, dst, _regs.eflags);= =0A break;=0A =0A case 0x28 ... 0x2d: sub: /* sub */=0A- = emulate_2op_SrcV("sub", src, dst, _regs._eflags);=0A+ emulate_2op_S= rcV("sub", src, dst, _regs.eflags);=0A break;=0A =0A case 0x30 = ... 0x35: xor: /* xor */=0A- emulate_2op_SrcV("xor", src, dst, = _regs._eflags);=0A+ emulate_2op_SrcV("xor", src, dst, _regs.eflags);= =0A break;=0A =0A case 0x38 ... 0x3d: cmp: /* cmp */=0A = generate_exception_if(lock_prefix, EXC_UD);=0A- emulate_2op_SrcV("c= mp", src, dst, _regs._eflags);=0A+ emulate_2op_SrcV("cmp", src, = dst, _regs.eflags);=0A dst.type =3D OP_NONE;=0A break;=0A = =0A@@ -3266,36 +3266,36 @@ x86_emulate(=0A case 0x27: /* daa */=0A = case 0x2f: /* das */ {=0A uint8_t al =3D _regs.al;=0A- = unsigned int eflags =3D _regs._eflags;=0A+ unsigned int eflags =3D = _regs.eflags;=0A =0A- _regs._eflags &=3D ~(X86_EFLAGS_CF | = X86_EFLAGS_AF | X86_EFLAGS_SF |=0A+ _regs.eflags &=3D ~(X86_EFLAGS_C= F | X86_EFLAGS_AF | X86_EFLAGS_SF |=0A = X86_EFLAGS_ZF | X86_EFLAGS_PF);=0A if ( ((al & 0x0f) > 9) || = (eflags & X86_EFLAGS_AF) )=0A {=0A- _regs._eflags |=3D = X86_EFLAGS_AF;=0A+ _regs.eflags |=3D X86_EFLAGS_AF;=0A = if ( b =3D=3D 0x2f && (al < 6 || (eflags & X86_EFLAGS_CF)) )=0A- = _regs._eflags |=3D X86_EFLAGS_CF;=0A+ _regs.eflags = |=3D X86_EFLAGS_CF;=0A _regs.al +=3D (b =3D=3D 0x27) ? 6 : = -6;=0A }=0A if ( (al > 0x99) || (eflags & X86_EFLAGS_CF) = )=0A {=0A _regs.al +=3D (b =3D=3D 0x27) ? 0x60 : = -0x60;=0A- _regs._eflags |=3D X86_EFLAGS_CF;=0A+ = _regs.eflags |=3D X86_EFLAGS_CF;=0A }=0A- _regs._eflags = |=3D !_regs.al ? X86_EFLAGS_ZF : 0;=0A- _regs._eflags |=3D = ((int8_t)_regs.al < 0) ? X86_EFLAGS_SF : 0;=0A- _regs._eflags |=3D = even_parity(_regs.al) ? X86_EFLAGS_PF : 0;=0A+ _regs.eflags |=3D = !_regs.al ? X86_EFLAGS_ZF : 0;=0A+ _regs.eflags |=3D ((int8_t)_regs.= al < 0) ? X86_EFLAGS_SF : 0;=0A+ _regs.eflags |=3D even_parity(_regs= .al) ? X86_EFLAGS_PF : 0;=0A break;=0A }=0A =0A case 0x37: = /* aaa */=0A case 0x3f: /* aas */=0A- _regs._eflags &=3D = ~X86_EFLAGS_CF;=0A- if ( (_regs.al > 9) || (_regs._eflags & = X86_EFLAGS_AF) )=0A+ _regs.eflags &=3D ~X86_EFLAGS_CF;=0A+ = if ( (_regs.al > 9) || (_regs.eflags & X86_EFLAGS_AF) )=0A {=0A = _regs.al +=3D (b =3D=3D 0x37) ? 6 : -6;=0A _regs.ah = +=3D (b =3D=3D 0x37) ? 1 : -1;=0A- _regs._eflags |=3D X86_EFLAGS= _CF | X86_EFLAGS_AF;=0A+ _regs.eflags |=3D X86_EFLAGS_CF | = X86_EFLAGS_AF;=0A }=0A _regs.al &=3D 0x0f;=0A = break;=0A@@ -3306,9 +3306,9 @@ x86_emulate(=0A dst.bytes =3D = op_bytes;=0A dst.val =3D *dst.reg;=0A if ( b & 8 )=0A- = emulate_1op("dec", dst, _regs._eflags);=0A+ emulate_1op= ("dec", dst, _regs.eflags);=0A else=0A- emulate_1op("inc= ", dst, _regs._eflags);=0A+ emulate_1op("inc", dst, _regs.eflags= );=0A break;=0A =0A case 0x50 ... 0x57: /* push reg */=0A@@ = -3331,8 +3331,8 @@ x86_emulate(=0A case 0x60: /* pusha */ {=0A = int i;=0A unsigned int regs[] =3D {=0A- _regs._eax, = _regs._ecx, _regs._edx, _regs._ebx,=0A- _regs._esp, _regs._ebp, = _regs._esi, _regs._edi };=0A+ _regs.eax, _regs.ecx, _regs.edx, = _regs.ebx,=0A+ _regs.esp, _regs.ebp, _regs.esi, _regs.edi };=0A = =0A fail_if(!ops->write);=0A for ( i =3D 0; i < 8; i++ = )=0A@@ -3345,8 +3345,8 @@ x86_emulate(=0A case 0x61: /* popa */ {=0A = int i;=0A unsigned int dummy_esp, *regs[] =3D {=0A- = &_regs._edi, &_regs._esi, &_regs._ebp, &dummy_esp,=0A- = &_regs._ebx, &_regs._edx, &_regs._ecx, &_regs._eax };=0A+ = &_regs.edi, &_regs.esi, &_regs.ebp, &dummy_esp,=0A+ &_regs.ebx, = &_regs.edx, &_regs.ecx, &_regs.eax };=0A =0A for ( i =3D 0; i < 8; = i++ )=0A {=0A@@ -3401,12 +3401,12 @@ x86_emulate(=0A = goto done;=0A if ( src_rpl > (dst.val & 3) )=0A = {=0A- _regs._eflags |=3D X86_EFLAGS_ZF;=0A+ = _regs.eflags |=3D X86_EFLAGS_ZF;=0A dst.val =3D (dst.val & = ~3) | src_rpl;=0A }=0A else=0A {=0A- = _regs._eflags &=3D ~X86_EFLAGS_ZF;=0A+ = _regs.eflags &=3D ~X86_EFLAGS_ZF;=0A dst.type =3D = OP_NONE;=0A }=0A generate_exception_if(!in_protmode= (ctxt, ops), EXC_UD);=0A@@ -3518,7 +3518,7 @@ x86_emulate(=0A }=0A =0A = case 0x70 ... 0x7f: /* jcc (short) */=0A- if ( test_cc(b, = _regs._eflags) )=0A+ if ( test_cc(b, _regs.eflags) )=0A = jmp_rel((int32_t)src.val);=0A adjust_bnd(ctxt, ops, vex.pfx);=0A = break;=0A@@ -3539,7 +3539,7 @@ x86_emulate(=0A =0A case 0xa8 ... = 0xa9: /* test imm,%%eax */=0A case 0x84 ... 0x85: test: /* test */=0A- = emulate_2op_SrcV("test", src, dst, _regs._eflags);=0A+ = emulate_2op_SrcV("test", src, dst, _regs.eflags);=0A dst.type =3D = OP_NONE;=0A break;=0A =0A@@ -3637,7 +3637,7 @@ x86_emulate(=0A = {=0A case 2: _regs.ax =3D (int8_t)_regs.al; break; /* cbw = */=0A case 4: _regs.r(ax) =3D (uint32_t)(int16_t)_regs.ax; break; = /* cwde */=0A- case 8: _regs.r(ax) =3D (int32_t)_regs._eax; break; = /* cdqe */=0A+ case 8: _regs.r(ax) =3D (int32_t)_regs.eax; break; = /* cdqe */=0A }=0A break;=0A =0A@@ -3645,7 +3645,7 @@ = x86_emulate(=0A switch ( op_bytes )=0A {=0A case = 2: _regs.dx =3D -((int16_t)_regs.ax < 0); break;=0A- case 4: = _regs.r(dx) =3D (uint32_t)-((int32_t)_regs._eax < 0); break;=0A+ = case 4: _regs.r(dx) =3D (uint32_t)-((int32_t)_regs.eax < 0); break;=0A = #ifdef __x86_64__=0A case 8: _regs.rdx =3D -((int64_t)_regs.rax < = 0); break;=0A #endif=0A@@ -3669,7 +3669,7 @@ x86_emulate(=0A = goto done;=0A =0A _regs.r(ip) =3D imm1;=0A- singlestep =3D = _regs._eflags & X86_EFLAGS_TF;=0A+ singlestep =3D _regs.eflags & = X86_EFLAGS_TF;=0A break;=0A =0A case 0x9b: /* wait/fwait = */=0A@@ -3681,8 +3681,8 @@ x86_emulate(=0A break;=0A =0A case = 0x9c: /* pushf */=0A- if ( (_regs._eflags & X86_EFLAGS_VM) &&=0A- = MASK_EXTR(_regs._eflags, X86_EFLAGS_IOPL) !=3D 3 )=0A+ if = ( (_regs.eflags & X86_EFLAGS_VM) &&=0A+ MASK_EXTR(_regs.eflags,= X86_EFLAGS_IOPL) !=3D 3 )=0A {=0A cr4 =3D 0;=0A = if ( op_bytes =3D=3D 2 && ops->read_cr )=0A@@ -3693,7 +3693,7 @@ = x86_emulate(=0A }=0A generate_exception_if(!(cr4 & = X86_CR4_VME), EXC_GP, 0);=0A src.val =3D (_regs.flags & = ~X86_EFLAGS_IF) | X86_EFLAGS_IOPL;=0A- if ( _regs._eflags & = X86_EFLAGS_VIF )=0A+ if ( _regs.eflags & X86_EFLAGS_VIF )=0A = src.val |=3D X86_EFLAGS_IF;=0A }=0A else=0A@@ = -3706,7 +3706,7 @@ x86_emulate(=0A cr4 =3D 0;=0A if ( = !mode_ring0() )=0A {=0A- if ( _regs._eflags & X86_EFLAGS= _VM )=0A+ if ( _regs.eflags & X86_EFLAGS_VM )=0A = {=0A if ( op_bytes =3D=3D 2 && ops->read_cr )=0A = {=0A@@ -3715,7 +3715,7 @@ x86_emulate(=0A = goto done;=0A }=0A generate_exception_if(!(= cr4 & X86_CR4_VME) &&=0A- MASK_EXTR(_r= egs._eflags, X86_EFLAGS_IOPL) !=3D 3,=0A+ = MASK_EXTR(_regs.eflags, X86_EFLAGS_IOPL) !=3D 3,=0A = EXC_GP, 0);=0A }=0A mask |=3D = X86_EFLAGS_IOPL;=0A@@ -3730,12 +3730,12 @@ x86_emulate(=0A = goto done;=0A if ( op_bytes =3D=3D 2 )=0A {=0A- = dst.val =3D (uint16_t)dst.val | (_regs._eflags & 0xffff0000u);=0A+ = dst.val =3D (uint16_t)dst.val | (_regs.eflags & 0xffff0000u);=0A = if ( cr4 & X86_CR4_VME )=0A {=0A if ( = dst.val & X86_EFLAGS_IF )=0A {=0A- = generate_exception_if(_regs._eflags & X86_EFLAGS_VIP,=0A+ = generate_exception_if(_regs.eflags & X86_EFLAGS_VIP,=0A = EXC_GP, 0);=0A dst.val |=3D = X86_EFLAGS_VIF;=0A }=0A@@ -3745,21 +3745,21 @@ x86_emulate(= =0A }=0A }=0A dst.val &=3D EFLAGS_MODIFIABLE;= =0A- _regs._eflags &=3D mask;=0A- _regs._eflags |=3D = (dst.val & ~mask) | X86_EFLAGS_MBS;=0A+ _regs.eflags &=3D mask;=0A+ = _regs.eflags |=3D (dst.val & ~mask) | X86_EFLAGS_MBS;=0A = break;=0A }=0A =0A case 0x9e: /* sahf */=0A if ( mode_64bit= () )=0A vcpu_must_have(lahf_lm);=0A- *(uint8_t = *)&_regs._eflags =3D (_regs.ah & EFLAGS_MASK) | X86_EFLAGS_MBS;=0A+ = *(uint8_t *)&_regs.eflags =3D (_regs.ah & EFLAGS_MASK) | X86_EFLAGS_MBS;=0A= break;=0A =0A case 0x9f: /* lahf */=0A if ( mode_64bit= () )=0A vcpu_must_have(lahf_lm);=0A- _regs.ah =3D = (_regs._eflags & EFLAGS_MASK) | X86_EFLAGS_MBS;=0A+ _regs.ah =3D = (_regs.eflags & EFLAGS_MASK) | X86_EFLAGS_MBS;=0A break;=0A =0A = case 0xa4 ... 0xa5: /* movs */ {=0A@@ -3802,9 +3802,9 @@ x86_emulate(=0A = register_address_adjust(_regs.r(di), src.bytes);=0A = put_rep_prefix(1);=0A /* cmp: dst - src =3D=3D> src=3D*%%edi,dst=3D= *%%esi =3D=3D> *%%esi - *%%edi */=0A- emulate_2op_SrcV("cmp", src, = dst, _regs._eflags);=0A- if ( (repe_prefix() && !(_regs._eflags & = X86_EFLAGS_ZF)) ||=0A- (repne_prefix() && (_regs._eflags & = X86_EFLAGS_ZF)) )=0A+ emulate_2op_SrcV("cmp", src, dst, _regs.eflags= );=0A+ if ( (repe_prefix() && !(_regs.eflags & X86_EFLAGS_ZF)) = ||=0A+ (repne_prefix() && (_regs.eflags & X86_EFLAGS_ZF)) )=0A = _regs.r(ip) =3D next_eip;=0A break;=0A }=0A@@ = -3852,9 +3852,9 @@ x86_emulate(=0A put_rep_prefix(1);=0A = /* cmp: %%eax - *%%edi =3D=3D> src=3D%%eax,dst=3D*%%edi =3D=3D> src - dst = */=0A dst.bytes =3D src.bytes;=0A- emulate_2op_SrcV("cmp", = dst, src, _regs._eflags);=0A- if ( (repe_prefix() && !(_regs._eflags= & X86_EFLAGS_ZF)) ||=0A- (repne_prefix() && (_regs._eflags & = X86_EFLAGS_ZF)) )=0A+ emulate_2op_SrcV("cmp", dst, src, _regs.eflags= );=0A+ if ( (repe_prefix() && !(_regs.eflags & X86_EFLAGS_ZF)) = ||=0A+ (repne_prefix() && (_regs.eflags & X86_EFLAGS_ZF)) )=0A = _regs.r(ip) =3D next_eip;=0A break;=0A }=0A@@ = -3875,26 +3875,26 @@ x86_emulate(=0A switch ( modrm_reg & 7 )=0A = {=0A case 0: /* rol */=0A- emulate_2op_SrcB("rol",= src, dst, _regs._eflags);=0A+ emulate_2op_SrcB("rol", src, = dst, _regs.eflags);=0A break;=0A case 1: /* ror */=0A- = emulate_2op_SrcB("ror", src, dst, _regs._eflags);=0A+ = emulate_2op_SrcB("ror", src, dst, _regs.eflags);=0A break;=0A = case 2: /* rcl */=0A- emulate_2op_SrcB("rcl", src, dst, = _regs._eflags);=0A+ emulate_2op_SrcB("rcl", src, dst, _regs.efla= gs);=0A break;=0A case 3: /* rcr */=0A- = emulate_2op_SrcB("rcr", src, dst, _regs._eflags);=0A+ emulate_2o= p_SrcB("rcr", src, dst, _regs.eflags);=0A break;=0A = case 4: /* sal/shl */=0A case 6: /* sal/shl */=0A- = emulate_2op_SrcB("sal", src, dst, _regs._eflags);=0A+ emulate_2o= p_SrcB("sal", src, dst, _regs.eflags);=0A break;=0A = case 5: /* shr */=0A- emulate_2op_SrcB("shr", src, dst, = _regs._eflags);=0A+ emulate_2op_SrcB("shr", src, dst, _regs.efla= gs);=0A break;=0A case 7: /* sar */=0A- = emulate_2op_SrcB("sar", src, dst, _regs._eflags);=0A+ emulate_2o= p_SrcB("sar", src, dst, _regs.eflags);=0A break;=0A = }=0A break;=0A@@ -3964,7 +3964,7 @@ x86_emulate(=0A if ( = dst.bytes =3D=3D 2 )=0A _regs.sp =3D _regs.bp;=0A = else=0A- _regs.r(sp) =3D dst.bytes =3D=3D 4 ? _regs._ebp : = _regs.r(bp);=0A+ _regs.r(sp) =3D dst.bytes =3D=3D 4 ? _regs.ebp = : _regs.r(bp);=0A =0A /* Second writeback, to %%ebp. */=0A = dst.type =3D OP_REG;=0A@@ -3999,7 +3999,7 @@ x86_emulate(=0A goto = done;=0A =0A case 0xce: /* into */=0A- if ( !(_regs._eflags & = X86_EFLAGS_OF) )=0A+ if ( !(_regs.eflags & X86_EFLAGS_OF) )=0A = break;=0A src.val =3D EXC_OF;=0A swint_type =3D = x86_swint_into;=0A@@ -4018,10 +4018,10 @@ x86_emulate(=0A = &eflags, op_bytes, ctxt, ops)) )=0A goto done;=0A = if ( op_bytes =3D=3D 2 )=0A- eflags =3D (uint16_t)eflags= | (_regs._eflags & 0xffff0000u);=0A+ eflags =3D (uint16_t)eflag= s | (_regs.eflags & 0xffff0000u);=0A eflags &=3D EFLAGS_MODIFIABLE;= =0A- _regs._eflags &=3D mask;=0A- _regs._eflags |=3D (eflags = & ~mask) | X86_EFLAGS_MBS;=0A+ _regs.eflags &=3D mask;=0A+ = _regs.eflags |=3D (eflags & ~mask) | X86_EFLAGS_MBS;=0A if ( (rc = =3D load_seg(x86_seg_cs, sel, 1, &cs, ctxt, ops)) ||=0A (rc = =3D commit_far_branch(&cs, (uint32_t)eip)) )=0A goto done;=0A@@= -4053,15 +4053,15 @@ x86_emulate(=0A generate_exception_if(!ba= se, EXC_DE);=0A _regs.ax =3D ((al / base) << 8) | (al % = base);=0A }=0A- _regs._eflags &=3D ~(X86_EFLAGS_SF | = X86_EFLAGS_ZF | X86_EFLAGS_PF);=0A- _regs._eflags |=3D !_regs.al ? = X86_EFLAGS_ZF : 0;=0A- _regs._eflags |=3D ((int8_t)_regs.al < 0) ? = X86_EFLAGS_SF : 0;=0A- _regs._eflags |=3D even_parity(_regs.al) ? = X86_EFLAGS_PF : 0;=0A+ _regs.eflags &=3D ~(X86_EFLAGS_SF | = X86_EFLAGS_ZF | X86_EFLAGS_PF);=0A+ _regs.eflags |=3D !_regs.al ? = X86_EFLAGS_ZF : 0;=0A+ _regs.eflags |=3D ((int8_t)_regs.al < 0) ? = X86_EFLAGS_SF : 0;=0A+ _regs.eflags |=3D even_parity(_regs.al) ? = X86_EFLAGS_PF : 0;=0A break;=0A }=0A =0A case 0xd6: /* = salc */=0A- _regs.al =3D (_regs._eflags & X86_EFLAGS_CF) ? 0xff : = 0x00;=0A+ _regs.al =3D (_regs.eflags & X86_EFLAGS_CF) ? 0xff : = 0x00;=0A break;=0A =0A case 0xd7: /* xlat */ {=0A@@ -4579,7 = +4579,7 @@ x86_emulate(=0A =0A case 0xe0 ... 0xe2: /* loop{,z,nz} */ = {=0A unsigned long count =3D get_loop_count(&_regs, ad_bytes);=0A- = int do_jmp =3D !(_regs._eflags & X86_EFLAGS_ZF); /* loopnz */=0A+ = int do_jmp =3D !(_regs.eflags & X86_EFLAGS_ZF); /* loopnz */=0A =0A = if ( b =3D=3D 0xe1 )=0A do_jmp =3D !do_jmp; /* loopz = */=0A@@ -4613,7 +4613,7 @@ x86_emulate(=0A {=0A /* out = */=0A fail_if(ops->write_io =3D=3D NULL);=0A- rc = =3D ops->write_io(port, op_bytes, _regs._eax, ctxt);=0A+ rc =3D = ops->write_io(port, op_bytes, _regs.eax, ctxt);=0A }=0A = else=0A {=0A@@ -4667,7 +4667,7 @@ x86_emulate(=0A = break;=0A =0A case 0xf5: /* cmc */=0A- _regs._eflags ^=3D = X86_EFLAGS_CF;=0A+ _regs.eflags ^=3D X86_EFLAGS_CF;=0A = break;=0A =0A case 0xf6 ... 0xf7: /* Grp3 */=0A@@ -4684,32 +4684,32 @@ = x86_emulate(=0A dst.val =3D ~dst.val;=0A break;=0A = case 3: /* neg */=0A- emulate_1op("neg", dst, _regs._efl= ags);=0A+ emulate_1op("neg", dst, _regs.eflags);=0A = break;=0A case 4: /* mul */=0A- _regs._eflags &=3D = ~(X86_EFLAGS_OF | X86_EFLAGS_CF);=0A+ _regs.eflags &=3D = ~(X86_EFLAGS_OF | X86_EFLAGS_CF);=0A switch ( dst.bytes )=0A = {=0A case 1:=0A dst.val =3D = _regs.al;=0A dst.val *=3D src.val;=0A if ( = (uint8_t)dst.val !=3D (uint16_t)dst.val )=0A- _regs._efl= ags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A+ _regs.eflags= |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A dst.bytes =3D = 2;=0A break;=0A case 2:=0A = dst.val =3D _regs.ax;=0A dst.val *=3D src.val;=0A = if ( (uint16_t)dst.val !=3D (uint32_t)dst.val )=0A- = _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A+ = _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A = _regs.dx =3D dst.val >> 16;=0A break;=0A #ifdef __x86_64__= =0A case 4:=0A- dst.val =3D _regs._eax;=0A+ = dst.val =3D _regs.eax;=0A dst.val *=3D = src.val;=0A if ( (uint32_t)dst.val !=3D dst.val )=0A- = _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A+ = _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A = _regs.rdx =3D dst.val >> 32;=0A break;=0A #endif=0A@@ = -4717,7 +4717,7 @@ x86_emulate(=0A u[0] =3D src.val;=0A = u[1] =3D _regs.r(ax);=0A if ( mul_dbl(u) = )=0A- _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;= =0A+ _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A= _regs.r(dx) =3D u[1];=0A dst.val =3D = u[0];=0A break;=0A@@ -4725,13 +4725,13 @@ x86_emulate(=0A = break;=0A case 5: /* imul */=0A imul:=0A- = _regs._eflags &=3D ~(X86_EFLAGS_OF | X86_EFLAGS_CF);=0A+ = _regs.eflags &=3D ~(X86_EFLAGS_OF | X86_EFLAGS_CF);=0A switch = ( dst.bytes )=0A {=0A case 1:=0A = dst.val =3D (int8_t)src.val * (int8_t)_regs.al;=0A if ( = (int8_t)dst.val !=3D (int16_t)dst.val )=0A- _regs._eflag= s |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A+ _regs.eflags = |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A ASSERT(b > = 0x6b);=0A dst.bytes =3D 2;=0A break;=0A@@ = -4739,16 +4739,16 @@ x86_emulate(=0A dst.val =3D ((uint32_t= )(int16_t)src.val *=0A (uint32_t)(int16_t)_regs.= ax);=0A if ( (int16_t)dst.val !=3D (int32_t)dst.val )=0A- = _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A+ = _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A = if ( b > 0x6b )=0A _regs.dx =3D dst.val >> = 16;=0A break;=0A #ifdef __x86_64__=0A case = 4:=0A dst.val =3D ((uint64_t)(int32_t)src.val *=0A- = (uint64_t)(int32_t)_regs._eax);=0A+ = (uint64_t)(int32_t)_regs.eax);=0A if ( (int32_t)dst.v= al !=3D dst.val )=0A- _regs._eflags |=3D X86_EFLAGS_OF = | X86_EFLAGS_CF;=0A+ _regs.eflags |=3D X86_EFLAGS_OF | = X86_EFLAGS_CF;=0A if ( b > 0x6b )=0A = _regs.rdx =3D dst.val >> 32;=0A break;=0A@@ -4757,7 = +4757,7 @@ x86_emulate(=0A u[0] =3D src.val;=0A = u[1] =3D _regs.r(ax);=0A if ( imul_dbl(u) )=0A- = _regs._eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A+ = _regs.eflags |=3D X86_EFLAGS_OF | X86_EFLAGS_CF;=0A = if ( b > 0x6b )=0A _regs.r(dx) =3D u[1];=0A = dst.val =3D u[0];=0A@@ -4778,7 +4778,7 @@ x86_emulate(=0A = _regs.ah =3D u[1];=0A break;=0A case = 2:=0A- u[0] =3D (_regs._edx << 16) | _regs.ax;=0A+ = u[0] =3D (_regs.edx << 16) | _regs.ax;=0A u[1] =3D = 0;=0A v =3D (uint16_t)src.val;=0A = generate_exception_if(=0A@@ -4789,7 +4789,7 @@ x86_emulate(=0A = break;=0A #ifdef __x86_64__=0A case 4:=0A- = u[0] =3D (_regs.rdx << 32) | _regs._eax;=0A+ u[0] =3D = (_regs.rdx << 32) | _regs.eax;=0A u[1] =3D 0;=0A = v =3D (uint32_t)src.val;=0A generate_exception_if(= =0A@@ -4823,7 +4823,7 @@ x86_emulate(=0A _regs.ah =3D = u[1];=0A break;=0A case 2:=0A- = u[0] =3D (int32_t)((_regs._edx << 16) | _regs.ax);=0A+ u[0] = =3D (int32_t)((_regs.edx << 16) | _regs.ax);=0A u[1] =3D = ((long)u[0] < 0) ? ~0UL : 0UL;=0A v =3D (int16_t)src.val= ;=0A generate_exception_if(=0A@@ -4834,7 +4834,7 @@ = x86_emulate(=0A break;=0A #ifdef __x86_64__=0A = case 4:=0A- u[0] =3D (_regs.rdx << 32) | _regs._eax;=0A+ = u[0] =3D (_regs.rdx << 32) | _regs.eax;=0A = u[1] =3D ((long)u[0] < 0) ? ~0UL : 0UL;=0A v =3D = (int32_t)src.val;=0A generate_exception_if(=0A@@ -4858,47 = +4858,47 @@ x86_emulate(=0A break;=0A =0A case 0xf8: /* clc = */=0A- _regs._eflags &=3D ~X86_EFLAGS_CF;=0A+ _regs.eflags = &=3D ~X86_EFLAGS_CF;=0A break;=0A =0A case 0xf9: /* stc */=0A- = _regs._eflags |=3D X86_EFLAGS_CF;=0A+ _regs.eflags |=3D = X86_EFLAGS_CF;=0A break;=0A =0A case 0xfa: /* cli */=0A = if ( mode_iopl() )=0A- _regs._eflags &=3D ~X86_EFLAGS_IF;=0A+ = _regs.eflags &=3D ~X86_EFLAGS_IF;=0A else=0A = {=0A generate_exception_if(!mode_vif(), EXC_GP, 0);=0A- = _regs._eflags &=3D ~X86_EFLAGS_VIF;=0A+ _regs.eflags &=3D = ~X86_EFLAGS_VIF;=0A }=0A break;=0A =0A case 0xfb: /* = sti */=0A if ( mode_iopl() )=0A {=0A- if ( = !(_regs._eflags & X86_EFLAGS_IF) )=0A+ if ( !(_regs.eflags & = X86_EFLAGS_IF) )=0A ctxt->retire.sti =3D true;=0A- = _regs._eflags |=3D X86_EFLAGS_IF;=0A+ _regs.eflags |=3D = X86_EFLAGS_IF;=0A }=0A else=0A {=0A- = generate_exception_if((_regs._eflags & X86_EFLAGS_VIP) ||=0A+ = generate_exception_if((_regs.eflags & X86_EFLAGS_VIP) ||=0A = !mode_vif(),=0A EXC_GP, = 0);=0A- if ( !(_regs._eflags & X86_EFLAGS_VIF) )=0A+ = if ( !(_regs.eflags & X86_EFLAGS_VIF) )=0A ctxt->retire.sti= =3D true;=0A- _regs._eflags |=3D X86_EFLAGS_VIF;=0A+ = _regs.eflags |=3D X86_EFLAGS_VIF;=0A }=0A break;=0A =0A = case 0xfc: /* cld */=0A- _regs._eflags &=3D ~X86_EFLAGS_DF;=0A+ = _regs.eflags &=3D ~X86_EFLAGS_DF;=0A break;=0A =0A case = 0xfd: /* std */=0A- _regs._eflags |=3D X86_EFLAGS_DF;=0A+ = _regs.eflags |=3D X86_EFLAGS_DF;=0A break;=0A =0A case 0xfe: = /* Grp4 */=0A@@ -4908,10 +4908,10 @@ x86_emulate(=0A switch ( = modrm_reg & 7 )=0A {=0A case 0: /* inc */=0A- = emulate_1op("inc", dst, _regs._eflags);=0A+ emulate_1op("inc", = dst, _regs.eflags);=0A break;=0A case 1: /* dec */=0A- = emulate_1op("dec", dst, _regs._eflags);=0A+ = emulate_1op("dec", dst, _regs.eflags);=0A break;=0A = case 2: /* call (near) */=0A dst.val =3D _regs.r(ip);=0A@@ = -4960,7 +4960,7 @@ x86_emulate(=0A goto done;=0A = break;=0A case 4: /* verr / verw */=0A- _regs._eflags = &=3D ~X86_EFLAGS_ZF;=0A+ _regs.eflags &=3D ~X86_EFLAGS_ZF;=0A = switch ( rc =3D protmode_load_seg(x86_seg_none, src.val, = false,=0A &sreg, ctxt, ops) = )=0A {=0A@@ -4968,7 +4968,7 @@ x86_emulate(=0A = if ( sreg.attr.fields.s &&=0A ((modrm_reg & 1) ? = ((sreg.attr.fields.type & 0xa) =3D=3D 0x2)=0A = : ((sreg.attr.fields.type & 0xa) !=3D 0x8)) )=0A- = _regs._eflags |=3D X86_EFLAGS_ZF;=0A+ _regs.eflags = |=3D X86_EFLAGS_ZF;=0A break;=0A case = X86EMUL_EXCEPTION:=0A if ( ctxt->event_pending )=0A@@ = -4998,9 +4998,9 @@ x86_emulate(=0A vcpu_must_have(smap);=0A = generate_exception_if(vex.pfx || !mode_ring0(), EXC_UD);=0A =0A- = _regs._eflags &=3D ~X86_EFLAGS_AC;=0A+ _regs.eflags = &=3D ~X86_EFLAGS_AC;=0A if ( modrm =3D=3D 0xcb )=0A- = _regs._eflags |=3D X86_EFLAGS_AC;=0A+ _regs.eflags = |=3D X86_EFLAGS_AC;=0A goto complete_insn;=0A =0A #ifdef = __XEN__=0A@@ -5010,8 +5010,8 @@ x86_emulate(=0A cr4 =3D = 0;=0A generate_exception_if(!(cr4 & X86_CR4_OSXSAVE), = EXC_UD);=0A generate_exception_if(!mode_ring0() ||=0A- = handle_xsetbv(_regs._ecx,=0A- = _regs._eax | (_regs.rdx << 32)),=0A+ = handle_xsetbv(_regs.ecx,=0A+ = _regs.eax | (_regs.rdx << 32)),=0A = EXC_GP, 0);=0A goto complete_insn;=0A = #endif=0A@@ -5034,7 +5034,7 @@ x86_emulate(=0A generate_excepti= on_if(!vcpu_has_rtm() && !vcpu_has_hle(),=0A = EXC_UD);=0A /* Neither HLE nor RTM can be active when we = get here. */=0A- _regs._eflags |=3D X86_EFLAGS_ZF;=0A+ = _regs.eflags |=3D X86_EFLAGS_ZF;=0A goto complete_insn;=0A = =0A case 0xdf: /* invlpga */=0A@@ -5059,7 +5059,7 @@ x86_emulate(= =0A unsigned long zero =3D 0;=0A =0A base =3D = ad_bytes =3D=3D 8 ? _regs.r(ax) :=0A- ad_bytes =3D=3D 4 = ? _regs._eax : _regs.ax;=0A+ ad_bytes =3D=3D 4 ? = _regs.eax : _regs.ax;=0A limit =3D 0;=0A if ( = vcpu_has_clflush() &&=0A ops->cpuid(1, 0, &cpuid_leaf, = ctxt) =3D=3D X86EMUL_OKAY )=0A@@ -5183,7 +5183,7 @@ x86_emulate(=0A =0A = case X86EMUL_OPC(0x0f, 0x02): /* lar */=0A generate_exception_if(!= in_protmode(ctxt, ops), EXC_UD);=0A- _regs._eflags &=3D ~X86_EFLAGS_= ZF;=0A+ _regs.eflags &=3D ~X86_EFLAGS_ZF;=0A switch ( rc = =3D protmode_load_seg(x86_seg_none, src.val, false, &sreg,=0A = ctxt, ops) )=0A {=0A@@ -5203,12 = +5203,12 @@ x86_emulate(=0A case 0x09: /* available = 32/64-bit TSS */=0A case 0x0b: /* busy 32/64-bit TSS */=0A = case 0x0c: /* 32/64-bit call gate */=0A- = _regs._eflags |=3D X86_EFLAGS_ZF;=0A+ _regs.eflags = |=3D X86_EFLAGS_ZF;=0A break;=0A }=0A = }=0A else=0A- _regs._eflags |=3D = X86_EFLAGS_ZF;=0A+ _regs.eflags |=3D X86_EFLAGS_ZF;=0A = break;=0A case X86EMUL_EXCEPTION:=0A if ( = ctxt->event_pending )=0A@@ -5221,7 +5221,7 @@ x86_emulate(=0A = rc =3D X86EMUL_OKAY;=0A break;=0A }=0A- if ( = _regs._eflags & X86_EFLAGS_ZF )=0A+ if ( _regs.eflags & X86_EFLAGS_Z= F )=0A dst.val =3D ((sreg.attr.bytes & 0xff) << 8) |=0A = ((sreg.limit >> (sreg.attr.fields.g ? 12 : 0)) &=0A = 0xf0000) |=0A@@ -5232,7 +5232,7 @@ x86_emulate(=0A =0A = case X86EMUL_OPC(0x0f, 0x03): /* lsl */=0A generate_exception_if(!i= n_protmode(ctxt, ops), EXC_UD);=0A- _regs._eflags &=3D ~X86_EFLAGS_Z= F;=0A+ _regs.eflags &=3D ~X86_EFLAGS_ZF;=0A switch ( rc =3D = protmode_load_seg(x86_seg_none, src.val, false, &sreg,=0A = ctxt, ops) )=0A {=0A@@ -5249,12 +5249,12 @@ = x86_emulate(=0A case 0x02: /* LDT */=0A = case 0x09: /* available 32/64-bit TSS */=0A case 0x0b: /* = busy 32/64-bit TSS */=0A- _regs._eflags |=3D X86_EFLAGS_= ZF;=0A+ _regs.eflags |=3D X86_EFLAGS_ZF;=0A = break;=0A }=0A }=0A = else=0A- _regs._eflags |=3D X86_EFLAGS_ZF;=0A+ = _regs.eflags |=3D X86_EFLAGS_ZF;=0A break;=0A case = X86EMUL_EXCEPTION:=0A if ( ctxt->event_pending )=0A@@ -5267,7 = +5267,7 @@ x86_emulate(=0A rc =3D X86EMUL_OKAY;=0A = break;=0A }=0A- if ( _regs._eflags & X86_EFLAGS_ZF )=0A+ = if ( _regs.eflags & X86_EFLAGS_ZF )=0A dst.val =3D = sreg.limit;=0A else=0A dst.type =3D OP_NONE;=0A@@ = -5301,7 +5301,7 @@ x86_emulate(=0A cs.attr.bytes =3D 0xa9b; /* = L+DB+P+S+Code */=0A =0A _regs.rcx =3D _regs.rip;=0A- = _regs.r11 =3D _regs._eflags & ~X86_EFLAGS_RF;=0A+ _regs.r11 = =3D _regs.eflags & ~X86_EFLAGS_RF;=0A =0A if ( (rc =3D = ops->read_msr(mode_64bit() ? MSR_LSTAR : MSR_CSTAR,=0A = &msr_val, ctxt)) !=3D X86EMUL_OKAY )=0A@@ -5311,16 = +5311,16 @@ x86_emulate(=0A if ( (rc =3D ops->read_msr(MSR_SYSC= ALL_MASK,=0A &msr_val, ctxt)) !=3D = X86EMUL_OKAY )=0A goto done;=0A- _regs._eflags = &=3D ~(msr_val | X86_EFLAGS_RF);=0A+ _regs.eflags &=3D = ~(msr_val | X86_EFLAGS_RF);=0A }=0A else=0A #endif=0A = {=0A cs.attr.bytes =3D 0xc9b; /* G+DB+P+S+Code */=0A =0A- = _regs.r(cx) =3D _regs._eip;=0A- _regs._eip =3D = msr_val;=0A- _regs._eflags &=3D ~(X86_EFLAGS_VM | X86_EFLAGS_IF = | X86_EFLAGS_RF);=0A+ _regs.r(cx) =3D _regs.eip;=0A+ = _regs.eip =3D msr_val;=0A+ _regs.eflags &=3D ~(X86_EFLAGS_VM | = X86_EFLAGS_IF | X86_EFLAGS_RF);=0A }=0A =0A fail_if(ops->wr= ite_segment =3D=3D NULL);=0A@@ -5343,7 +5343,7 @@ x86_emulate(=0A = * Their only mitigation is to use a task gate for handling=0A * = #DB (or to not use enable EFER.SCE to start with).=0A */=0A- = singlestep =3D _regs._eflags & X86_EFLAGS_TF;=0A+ singlestep =3D = _regs.eflags & X86_EFLAGS_TF;=0A break;=0A =0A case X86EMUL_OPC= (0x0f, 0x06): /* clts */=0A@@ -5695,8 +5695,8 @@ x86_emulate(=0A case = X86EMUL_OPC(0x0f, 0x30): /* wrmsr */=0A generate_exception_if(!mode= _ring0(), EXC_GP, 0);=0A fail_if(ops->write_msr =3D=3D NULL);=0A- = if ( (rc =3D ops->write_msr(_regs._ecx,=0A- = ((uint64_t)_regs.r(dx) << 32) | _regs._eax,=0A+ if ( (rc = =3D ops->write_msr(_regs.ecx,=0A+ = ((uint64_t)_regs.r(dx) << 32) | _regs.eax,=0A = ctxt)) !=3D 0 )=0A goto done;=0A break;=0A@@ = -5720,7 +5720,7 @@ x86_emulate(=0A case X86EMUL_OPC(0x0f, 0x32): /* = rdmsr */=0A generate_exception_if(!mode_ring0(), EXC_GP, 0);=0A = fail_if(ops->read_msr =3D=3D NULL);=0A- if ( (rc =3D ops->read_= msr(_regs._ecx, &msr_val, ctxt)) !=3D X86EMUL_OKAY )=0A+ if ( (rc = =3D ops->read_msr(_regs.ecx, &msr_val, ctxt)) !=3D X86EMUL_OKAY )=0A = goto done;=0A _regs.r(dx) =3D msr_val >> 32;=0A = _regs.r(ax) =3D (uint32_t)msr_val;=0A@@ -5728,7 +5728,7 @@ x86_emulate(=0A = =0A case X86EMUL_OPC(0x0f, 0x40) ... X86EMUL_OPC(0x0f, 0x4f): /* = cmovcc */=0A vcpu_must_have(cmov);=0A- if ( test_cc(b, = _regs._eflags) )=0A+ if ( test_cc(b, _regs.eflags) )=0A = dst.val =3D src.val;=0A break;=0A =0A@@ -5749,7 +5749,7 @@ = x86_emulate(=0A if ( lm < 0 )=0A goto cannot_emulate;= =0A =0A- _regs._eflags &=3D ~(X86_EFLAGS_VM | X86_EFLAGS_IF | = X86_EFLAGS_RF);=0A+ _regs.eflags &=3D ~(X86_EFLAGS_VM | X86_EFLAGS_I= F | X86_EFLAGS_RF);=0A =0A cs.sel =3D msr_val & ~3; /* SELECTOR_RPL= _MASK */=0A cs.base =3D 0; /* flat segment */=0A@@ -5777,7 = +5777,7 @@ x86_emulate(=0A goto done;=0A _regs.r(sp) = =3D lm ? msr_val : (uint32_t)msr_val;=0A =0A- singlestep =3D = _regs._eflags & X86_EFLAGS_TF;=0A+ singlestep =3D _regs.eflags & = X86_EFLAGS_TF;=0A break;=0A }=0A =0A@@ -5814,10 +5814,10 @@ = x86_emulate(=0A (rc =3D ops->write_segment(x86_seg_ss, &sreg, = ctxt)) !=3D 0 )=0A goto done;=0A =0A- _regs.r(ip) =3D = op_bytes =3D=3D 8 ? _regs.r(dx) : _regs._edx;=0A- _regs.r(sp) =3D = op_bytes =3D=3D 8 ? _regs.r(cx) : _regs._ecx;=0A+ _regs.r(ip) =3D = op_bytes =3D=3D 8 ? _regs.r(dx) : _regs.edx;=0A+ _regs.r(sp) =3D = op_bytes =3D=3D 8 ? _regs.r(cx) : _regs.ecx;=0A =0A- singlestep =3D = _regs._eflags & X86_EFLAGS_TF;=0A+ singlestep =3D _regs.eflags & = X86_EFLAGS_TF;=0A break;=0A =0A CASE_SIMD_PACKED_FP(, 0x0f, = 0x50): /* movmskp{s,d} xmm,reg */=0A@@ -6325,13 +6325,13 @@ x86_emulate= (=0A goto simd_0f_sse3_avx;=0A =0A case X86EMUL_OPC(0x0f, = 0x80) ... X86EMUL_OPC(0x0f, 0x8f): /* jcc (near) */=0A- if ( = test_cc(b, _regs._eflags) )=0A+ if ( test_cc(b, _regs.eflags) )=0A = jmp_rel((int32_t)src.val);=0A adjust_bnd(ctxt, ops, = vex.pfx);=0A break;=0A =0A case X86EMUL_OPC(0x0f, 0x90) ... = X86EMUL_OPC(0x0f, 0x9f): /* setcc */=0A- dst.val =3D test_cc(b, = _regs._eflags);=0A+ dst.val =3D test_cc(b, _regs.eflags);=0A = break;=0A =0A case X86EMUL_OPC(0x0f, 0xa2): /* cpuid */=0A@@ -6353,7 = +6353,7 @@ x86_emulate(=0A generate_exception_if((msr_val & = MSR_MISC_FEATURES_CPUID_FAULTING),=0A = EXC_GP, 0); /* Faulting active? (Inc. CPL test) */=0A =0A- rc =3D = ops->cpuid(_regs._eax, _regs._ecx, &cpuid_leaf, ctxt);=0A+ rc =3D = ops->cpuid(_regs.eax, _regs.ecx, &cpuid_leaf, ctxt);=0A if ( rc = !=3D X86EMUL_OKAY )=0A goto done;=0A _regs.r(ax) =3D = cpuid_leaf.a;=0A@@ -6364,7 +6364,7 @@ x86_emulate(=0A =0A case = X86EMUL_OPC(0x0f, 0xa3): bt: /* bt */=0A generate_exception_if(lock= _prefix, EXC_UD);=0A- emulate_2op_SrcV_nobyte("bt", src, dst, = _regs._eflags);=0A+ emulate_2op_SrcV_nobyte("bt", src, dst, = _regs.eflags);=0A dst.type =3D OP_NONE;=0A break;=0A =0A@@ = -6395,20 +6395,20 @@ x86_emulate(=0A ((dst.orig_val << = shift) |=0A ((src.val >> (width - shift)) & ((1ull << = shift) - 1))));=0A dst.val =3D truncate_word(dst.val, dst.bytes);= =0A- _regs._eflags &=3D ~(X86_EFLAGS_OF | X86_EFLAGS_SF | X86_EFLAGS= _ZF |=0A+ _regs.eflags &=3D ~(X86_EFLAGS_OF | X86_EFLAGS_SF | = X86_EFLAGS_ZF |=0A X86_EFLAGS_PF | X86_EFLAGS_CF= );=0A if ( (dst.val >> ((b & 8) ? (shift - 1) : (width - shift))) = & 1 )=0A- _regs._eflags |=3D X86_EFLAGS_CF;=0A+ = _regs.eflags |=3D X86_EFLAGS_CF;=0A if ( ((dst.val ^ dst.orig_val) = >> (width - 1)) & 1 )=0A- _regs._eflags |=3D X86_EFLAGS_OF;=0A- = _regs._eflags |=3D ((dst.val >> (width - 1)) & 1) ? X86_EFLAGS_SF : = 0;=0A- _regs._eflags |=3D (dst.val =3D=3D 0) ? X86_EFLAGS_ZF : = 0;=0A- _regs._eflags |=3D even_parity(dst.val) ? X86_EFLAGS_PF : = 0;=0A+ _regs.eflags |=3D X86_EFLAGS_OF;=0A+ _regs.eflags = |=3D ((dst.val >> (width - 1)) & 1) ? X86_EFLAGS_SF : 0;=0A+ = _regs.eflags |=3D (dst.val =3D=3D 0) ? X86_EFLAGS_ZF : 0;=0A+ = _regs.eflags |=3D even_parity(dst.val) ? X86_EFLAGS_PF : 0;=0A = break;=0A }=0A =0A case X86EMUL_OPC(0x0f, 0xab): bts: /* bts = */=0A- emulate_2op_SrcV_nobyte("bts", src, dst, _regs._eflags);=0A+ = emulate_2op_SrcV_nobyte("bts", src, dst, _regs.eflags);=0A = break;=0A =0A case X86EMUL_OPC(0x0f, 0xae): case X86EMUL_OPC_66(0x0f, = 0xae): /* Grp15 */=0A@@ -6525,7 +6525,7 @@ x86_emulate(=0A = break;=0A =0A case X86EMUL_OPC(0x0f, 0xaf): /* imul */=0A- = emulate_2op_SrcV_srcmem("imul", src, dst, _regs._eflags);=0A+ = emulate_2op_SrcV_srcmem("imul", src, dst, _regs.eflags);=0A = break;=0A =0A case X86EMUL_OPC(0x0f, 0xb0): case X86EMUL_OPC(0x0f, = 0xb1): /* cmpxchg */=0A@@ -6533,8 +6533,8 @@ x86_emulate(=0A = src.orig_val =3D src.val;=0A src.val =3D _regs.r(ax);=0A = /* cmp: %%eax - dst =3D=3D> dst and src swapped for macro invocation = */=0A- emulate_2op_SrcV("cmp", dst, src, _regs._eflags);=0A- = if ( _regs._eflags & X86_EFLAGS_ZF )=0A+ emulate_2op_SrcV("cmp", = dst, src, _regs.eflags);=0A+ if ( _regs.eflags & X86_EFLAGS_ZF )=0A = {=0A /* Success: write back to memory. */=0A = dst.val =3D src.orig_val;=0A@@ -6554,7 +6554,7 @@ x86_emulate(=0A = goto les;=0A =0A case X86EMUL_OPC(0x0f, 0xb3): btr: /* btr */=0A- = emulate_2op_SrcV_nobyte("btr", src, dst, _regs._eflags);=0A+ = emulate_2op_SrcV_nobyte("btr", src, dst, _regs.eflags);=0A = break;=0A =0A case X86EMUL_OPC(0x0f, 0xb6): /* movzx rm8,r{16,32,64} = */=0A@@ -6571,9 +6571,9 @@ x86_emulate(=0A case X86EMUL_OPC_F3(0x0f, = 0xb8): /* popcnt r/m,r */=0A host_and_vcpu_must_have(popcnt);=0A = asm ( "popcnt %1,%0" : "=3Dr" (dst.val) : "rm" (src.val) );=0A- = _regs._eflags &=3D ~EFLAGS_MASK;=0A+ _regs.eflags &=3D ~EFLAGS_MAS= K;=0A if ( !dst.val )=0A- _regs._eflags |=3D X86_EFLAGS_= ZF;=0A+ _regs.eflags |=3D X86_EFLAGS_ZF;=0A break;=0A = =0A case X86EMUL_OPC(0x0f, 0xba): /* Grp8 */=0A@@ -6588,7 +6588,7 @@ = x86_emulate(=0A break;=0A =0A case X86EMUL_OPC(0x0f, 0xbb): = btc: /* btc */=0A- emulate_2op_SrcV_nobyte("btc", src, dst, = _regs._eflags);=0A+ emulate_2op_SrcV_nobyte("btc", src, dst, = _regs.eflags);=0A break;=0A =0A case X86EMUL_OPC(0x0f, 0xbc): = /* bsf or tzcnt */=0A@@ -6598,21 +6598,21 @@ x86_emulate(=0A asm ( = "bsf %2,%0" ASM_FLAG_OUT(, "; setz %1")=0A : "=3Dr" = (dst.val), ASM_FLAG_OUT("=3D@ccz", "=3Dqm") (zf)=0A : "rm" = (src.val) );=0A- _regs._eflags &=3D ~X86_EFLAGS_ZF;=0A+ = _regs.eflags &=3D ~X86_EFLAGS_ZF;=0A if ( (vex.pfx =3D=3D vex_f3) = && vcpu_has_bmi1() )=0A {=0A- _regs._eflags &=3D = ~X86_EFLAGS_CF;=0A+ _regs.eflags &=3D ~X86_EFLAGS_CF;=0A = if ( zf )=0A {=0A- _regs._eflags |=3D = X86_EFLAGS_CF;=0A+ _regs.eflags |=3D X86_EFLAGS_CF;=0A = dst.val =3D op_bytes * 8;=0A }=0A else = if ( !dst.val )=0A- _regs._eflags |=3D X86_EFLAGS_ZF;=0A+ = _regs.eflags |=3D X86_EFLAGS_ZF;=0A }=0A else = if ( zf )=0A {=0A- _regs._eflags |=3D X86_EFLAGS_ZF;=0A+= _regs.eflags |=3D X86_EFLAGS_ZF;=0A dst.type =3D = OP_NONE;=0A }=0A break;=0A@@ -6625,25 +6625,25 @@ = x86_emulate(=0A asm ( "bsr %2,%0" ASM_FLAG_OUT(, "; setz %1")=0A = : "=3Dr" (dst.val), ASM_FLAG_OUT("=3D@ccz", "=3Dqm") (zf)=0A = : "rm" (src.val) );=0A- _regs._eflags &=3D ~X86_EFLAGS_Z= F;=0A+ _regs.eflags &=3D ~X86_EFLAGS_ZF;=0A if ( (vex.pfx = =3D=3D vex_f3) && vcpu_has_lzcnt() )=0A {=0A- _regs._efl= ags &=3D ~X86_EFLAGS_CF;=0A+ _regs.eflags &=3D ~X86_EFLAGS_CF;= =0A if ( zf )=0A {=0A- _regs._eflags= |=3D X86_EFLAGS_CF;=0A+ _regs.eflags |=3D X86_EFLAGS_CF;=0A= dst.val =3D op_bytes * 8;=0A }=0A = else=0A {=0A dst.val =3D op_bytes * 8 - 1 - = dst.val;=0A if ( !dst.val )=0A- = _regs._eflags |=3D X86_EFLAGS_ZF;=0A+ _regs.eflags |=3D = X86_EFLAGS_ZF;=0A }=0A }=0A else if ( zf )=0A = {=0A- _regs._eflags |=3D X86_EFLAGS_ZF;=0A+ = _regs.eflags |=3D X86_EFLAGS_ZF;=0A dst.type =3D OP_NONE;=0A = }=0A break;=0A@@ -6754,9 +6754,9 @@ x86_emulate(=0A = : "=3Dr" (dst.val), ASM_FLAG_OUT("=3D@ccc", "=3Dqm") = (carry) );=0A break;=0A }=0A- = _regs._eflags &=3D ~EFLAGS_MASK;=0A+ _regs.eflags = &=3D ~EFLAGS_MASK;=0A if ( carry )=0A- = _regs._eflags |=3D X86_EFLAGS_CF;=0A+ _regs.eflags |=3D = X86_EFLAGS_CF;=0A break;=0A #endif=0A =0A@@ -6795,9 = +6795,9 @@ x86_emulate(=0A : "=3Dr" (dst.val), = ASM_FLAG_OUT("=3D@ccc", "=3Dqm") (carry) );=0A = break;=0A }=0A- _regs._eflags &=3D = ~EFLAGS_MASK;=0A+ _regs.eflags &=3D ~EFLAGS_MASK;=0A = if ( carry )=0A- _regs._eflags |=3D X86_EFLAGS_= CF;=0A+ _regs.eflags |=3D X86_EFLAGS_CF;=0A = break;=0A #endif=0A }=0A@@ -6832,8 +6832,8 @@ x86_emulate(= =0A /* Get expected value. */=0A if ( !(rex_prefix & = REX_W) )=0A {=0A- aux->u32[0] =3D _regs._eax;=0A- = aux->u32[1] =3D _regs._edx;=0A+ aux->u32[0] =3D _regs.eax;= =0A+ aux->u32[1] =3D _regs.edx;=0A }=0A else=0A = {=0A@@ -6846,7 +6846,7 @@ x86_emulate(=0A /* Expected = !=3D actual: store actual to rDX:rAX and clear ZF. */=0A = _regs.r(ax) =3D !(rex_prefix & REX_W) ? old->u32[0] : old->u64[0];=0A = _regs.r(dx) =3D !(rex_prefix & REX_W) ? old->u32[1] : old->u64[1];= =0A- _regs._eflags &=3D ~X86_EFLAGS_ZF;=0A+ = _regs.eflags &=3D ~X86_EFLAGS_ZF;=0A }=0A else=0A = {=0A@@ -6856,8 +6856,8 @@ x86_emulate(=0A */=0A = if ( !(rex_prefix & REX_W) )=0A {=0A- aux->u32[0= ] =3D _regs._ebx;=0A- aux->u32[1] =3D _regs._ecx;=0A+ = aux->u32[0] =3D _regs.ebx;=0A+ aux->u32[1] =3D = _regs.ecx;=0A }=0A else=0A {=0A@@ = -6868,7 +6868,7 @@ x86_emulate(=0A if ( (rc =3D ops->cmpxchg(ea= .mem.seg, ea.mem.off, old, aux,=0A = op_bytes, ctxt)) !=3D X86EMUL_OKAY )=0A goto done;=0A- = _regs._eflags |=3D X86_EFLAGS_ZF;=0A+ _regs.eflags |=3D = X86_EFLAGS_ZF;=0A }=0A break;=0A }=0A@@ -7340,7 = +7340,7 @@ x86_emulate(=0A case X86EMUL_OPC_F3(0x0f38, 0xf6): /* adox = r/m,r */=0A {=0A unsigned int mask =3D rep_prefix() ? = X86_EFLAGS_OF : X86_EFLAGS_CF;=0A- unsigned int aux =3D _regs._eflag= s & mask ? ~0 : 0;=0A+ unsigned int aux =3D _regs.eflags & mask ? = ~0 : 0;=0A bool carry;=0A =0A vcpu_must_have(adx);=0A@@ = -7363,9 +7363,9 @@ x86_emulate(=0A [aux] "+r" (aux)=0A = : [src] "rm" (src.val) );=0A if ( carry )=0A- = _regs._eflags |=3D mask;=0A+ _regs.eflags |=3D mask;=0A = else=0A- _regs._eflags &=3D ~mask;=0A+ = _regs.eflags &=3D ~mask;=0A break;=0A }=0A =0A@@ -7378,7 = +7378,7 @@ x86_emulate(=0A : "0" (src.val), = "rm" (_regs.r(dx)) );=0A else=0A asm ( "mull %3" : = "=3Da" (*ea.reg), "=3Dd" (dst.val)=0A- : "0" = ((uint32_t)src.val), "rm" (_regs._edx) );=0A+ : = "0" ((uint32_t)src.val), "rm" (_regs.edx) );=0A break;=0A =0A = case X86EMUL_OPC(0x0f3a, 0x0f): /* palignr $imm8,mm/m64,mm */=0A@@ = -7811,7 +7811,7 @@ x86_emulate(=0A complete_insn: /* Commit shadow = register state. */=0A /* Zero the upper 32 bits of %rip if not in = 64-bit mode. */=0A if ( !mode_64bit() )=0A- _regs.r(ip) =3D = _regs._eip;=0A+ _regs.r(ip) =3D _regs.eip;=0A =0A /* Should a = singlestep #DB be raised? */=0A if ( rc =3D=3D X86EMUL_OKAY && = singlestep && !ctxt->retire.mov_ss )=0A@@ -7828,7 +7828,7 @@ x86_emulate(= =0A rc =3D X86EMUL_OKAY;=0A }=0A =0A- ctxt->regs->_eflags = &=3D ~X86_EFLAGS_RF;=0A+ ctxt->regs->eflags &=3D ~X86_EFLAGS_RF;=0A =0A = done:=0A _put_fpu();=0A --=__PartA49D4FC8.1__= Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Content-Disposition: inline X19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KWGVuLWRldmVs IG1haWxpbmcgbGlzdApYZW4tZGV2ZWxAbGlzdHMueGVuLm9yZwpodHRwczovL2xpc3RzLnhlbi5v cmcveGVuLWRldmVsCg== --=__PartA49D4FC8.1__=--