From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751997AbdC0Gdx (ORCPT ); Mon, 27 Mar 2017 02:33:53 -0400 Received: from mail-pg0-f65.google.com ([74.125.83.65]:33355 "EHLO mail-pg0-f65.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751407AbdC0Gdo (ORCPT ); Mon, 27 Mar 2017 02:33:44 -0400 Subject: Re: [PATCH v6 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow To: Mark Rutland References: <1489127325-112821-1-git-send-email-anurup.m@huawei.com> <20170321171605.GB29116@leverpostej> <58D4C006.2010907@gmail.com> <20170324114325.GC22771@leverpostej> Cc: will.deacon@arm.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, anurup.m@huawei.com, zhangshaokun@hisilicon.com, tanxiaojun@huawei.com, xuwei5@hisilicon.com, sanil.kumar@hisilicon.com, john.garry@huawei.com, gabriele.paoloni@huawei.com, shiju.jose@huawei.com, huangdaode@hisilicon.com, linuxarm@huawei.com, dikshit.n@huawei.com, shyju.pv@huawei.com From: Anurup M Message-ID: <58D8B234.3020004@gmail.com> Date: Mon, 27 Mar 2017 12:03:24 +0530 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:38.0) Gecko/20100101 Thunderbird/38.5.1 MIME-Version: 1.0 In-Reply-To: <20170324114325.GC22771@leverpostej> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Friday 24 March 2017 05:13 PM, Mark Rutland wrote: >>> How do we ensure that we don't take the interrupt in the middle of a >>> > >sequence of accesses to the HW? >> > >> >The L3 cache and MN PMU does not use the overflow IRQ and it does >> >not occur here >> >as the interrupt Mask register is by default masked in hardware. > I was referring to the timer interrupt which backs the hrtimer. > > i.e. how do we guarantee that hisi_hrtimer_callback() is not called > while we are in the middle of a RMW sequence? Are interrupts disabled > for all of those seqeunces? The HW access via djtag read and write are protected by spin_lock_irqsave. Thanks, Anurup > Thanks, > Mark. From mboxrd@z Thu Jan 1 00:00:00 1970 From: anurupvasu@gmail.com (Anurup M) Date: Mon, 27 Mar 2017 12:03:24 +0530 Subject: [PATCH v6 08/11] drivers: perf: hisi: use poll method to avoid L3C counter overflow In-Reply-To: <20170324114325.GC22771@leverpostej> References: <1489127325-112821-1-git-send-email-anurup.m@huawei.com> <20170321171605.GB29116@leverpostej> <58D4C006.2010907@gmail.com> <20170324114325.GC22771@leverpostej> Message-ID: <58D8B234.3020004@gmail.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org On Friday 24 March 2017 05:13 PM, Mark Rutland wrote: >>> How do we ensure that we don't take the interrupt in the middle of a >>> > >sequence of accesses to the HW? >> > >> >The L3 cache and MN PMU does not use the overflow IRQ and it does >> >not occur here >> >as the interrupt Mask register is by default masked in hardware. > I was referring to the timer interrupt which backs the hrtimer. > > i.e. how do we guarantee that hisi_hrtimer_callback() is not called > while we are in the middle of a RMW sequence? Are interrupts disabled > for all of those seqeunces? The HW access via djtag read and write are protected by spin_lock_irqsave. Thanks, Anurup > Thanks, > Mark.