Re: [PATCH v9 14/25] x86: refactor psr: CDP: implement CPU init and free flow.

["Jan Beulich" <JBeulich@suse.com>]

>>> On 16.03.17 at 12:08, <yi.y.sun@linux.intel.com> wrote:
> @@ -209,12 +212,29 @@ static DEFINE_PER_CPU(struct psr_assoc, psr_assoc);
>   * array creation. It is used to transiently store a spare node.
>   */
>  static struct feat_node *feat_l3_cat;
> +static struct feat_node *feat_l3_cdp;
>  
>  /* Common functions */
>  #define cat_default_val(len)                 \
>              ( (uint32_t)((1ul << len) - 1) )
>  
>  /*
> + * get_data - get DATA COS register value from input COS ID.
> + * @feat:        the feature node.
> + * @cos:         the COS ID.
> + */
> +#define get_cdp_data(feat, cos)              \
> +            ( (feat)->cos_reg_val[(cos) * 2] )

The comment above should have the correct macro name.

> @@ -303,20 +323,56 @@ static void cat_init_feature(struct cpuid_leaf regs,
>      cat.cbm_len = (regs.a & CAT_CBM_LEN_MASK) + 1;
>      cat.cos_max = min(opt_cos_max, regs.d & CAT_COS_MAX_MASK);
>  
> -    /* cos=0 is reserved as default cbm(all bits within cbm_len are 1). */
> -    feat->cos_reg_val[0] = cat_default_val(cat.cbm_len);
> -    /*
> -     * To handle cpu offline and then online case, we need read MSRs back to
> -     * save values into cos_reg_val array.
> -     */
> -    for ( i = 1; i <= cat.cos_max; i++ )
> +    if ( type == PSR_SOCKET_L3_CDP )
> +    {

Considering this change, I think you'd better make this a switch
statement right in the earlier patch, which will avoid the need to
re-indent things here.

Apart from these many comments given earlier apply here too.

Jan


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