From mboxrd@z Thu Jan 1 00:00:00 1970 From: Laxman Dewangan Subject: Re: [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume Date: Thu, 6 Apr 2017 22:18:18 +0530 Message-ID: <58E67152.1080400@nvidia.com> References: <1491488461-24621-1-git-send-email-ldewangan@nvidia.com> <1491488461-24621-4-git-send-email-ldewangan@nvidia.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-tegra-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: Jon Hunter , thierry.reding-Re5JQEeQqe8AvxtiuMwx3w@public.gmane.org, robh+dt-DgEjT+Ai2ygdnm+yROfE0A@public.gmane.org Cc: mark.rutland-5wv7dgnIgG8@public.gmane.org, linux-pwm-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-tegra-u79uwXL29TY76Z2rM5mHXA@public.gmane.org, linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org List-Id: linux-tegra@vger.kernel.org On Thursday 06 April 2017 08:56 PM, Jon Hunter wrote: > On 06/04/17 15:21, Laxman Dewangan wrote: >> In some of NVIDIA Tegra's platform, PWM controller is used to >> control the PWM controlled regulators. PWM signal is connected to >> the VID pin of the regulator where duty cycle of PWM signal decide >> the voltage level of the regulator output. >> >> The tristate (high impedance of PWM pin form Tegra) also define > s/form/from/ > s/define/defines/ > >> one of the state of PWM regulator which needs to be configure in >> suspend state of system. > It maybe clearer to say that when the system enters suspend the > regulator requires the pwm output to be tristated. Not necessarily that every PWM regulator interfaces needs it. It depends on the devices. So I will say: When system enters suspend, in some of PWM regulator interface, it is required to to set the PWM output to be tristated. > pwm: pwm@7000a000 { > @@ -29,3 +42,33 @@ Example: > resets = <&tegra_car 17>; > reset-names = "pwm"; > }; > + > + > +Example with the pin configuration for suspend and resume: > +========================================================= > +Pin PE7 is used as PWM interface. > Nit-pick. On what devices? Sounds like this is verbatim. Maybe state > what device this is an example for. Let me phrase it as: Suppose pin PE7 (On tegra210) interfaced with the regulator device and this requires PWM output to be tristated when system enters suspend. Following will be DT binding to achieve this: From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S933723AbdDFRG5 (ORCPT ); Thu, 6 Apr 2017 13:06:57 -0400 Received: from hqemgate15.nvidia.com ([216.228.121.64]:1851 "EHLO hqemgate15.nvidia.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752486AbdDFRGu (ORCPT ); Thu, 6 Apr 2017 13:06:50 -0400 X-PGP-Universal: processed; by hqpgpgate101.nvidia.com on Thu, 06 Apr 2017 10:06:49 -0700 Message-ID: <58E67152.1080400@nvidia.com> Date: Thu, 6 Apr 2017 22:18:18 +0530 From: Laxman Dewangan User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:24.0) Gecko/20100101 Thunderbird/24.4.0 MIME-Version: 1.0 To: Jon Hunter , , CC: , , , , Subject: Re: [PATCH V3 3/4] pwm: tegra: Add DT binding details to configure pin in suspends/resume References: <1491488461-24621-1-git-send-email-ldewangan@nvidia.com> <1491488461-24621-4-git-send-email-ldewangan@nvidia.com> In-Reply-To: X-Originating-IP: [10.19.65.30] X-ClientProxiedBy: DRBGMAIL103.nvidia.com (10.18.16.22) To bgmail102.nvidia.com (10.25.59.11) Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thursday 06 April 2017 08:56 PM, Jon Hunter wrote: > On 06/04/17 15:21, Laxman Dewangan wrote: >> In some of NVIDIA Tegra's platform, PWM controller is used to >> control the PWM controlled regulators. PWM signal is connected to >> the VID pin of the regulator where duty cycle of PWM signal decide >> the voltage level of the regulator output. >> >> The tristate (high impedance of PWM pin form Tegra) also define > s/form/from/ > s/define/defines/ > >> one of the state of PWM regulator which needs to be configure in >> suspend state of system. > It maybe clearer to say that when the system enters suspend the > regulator requires the pwm output to be tristated. Not necessarily that every PWM regulator interfaces needs it. It depends on the devices. So I will say: When system enters suspend, in some of PWM regulator interface, it is required to to set the PWM output to be tristated. > pwm: pwm@7000a000 { > @@ -29,3 +42,33 @@ Example: > resets = <&tegra_car 17>; > reset-names = "pwm"; > }; > + > + > +Example with the pin configuration for suspend and resume: > +========================================================= > +Pin PE7 is used as PWM interface. > Nit-pick. On what devices? Sounds like this is verbatim. Maybe state > what device this is an example for. Let me phrase it as: Suppose pin PE7 (On tegra210) interfaced with the regulator device and this requires PWM output to be tristated when system enters suspend. Following will be DT binding to achieve this: