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From: "Jan Beulich" <JBeulich@suse.com>
To: Roger Pau Monne <roger.pau@citrix.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>,
	xen-devel@lists.xenproject.org
Subject: Re: [PATCH 1/5] x86/dpci: allow hvm_irq_dpci to handle a variable number of GSIs
Date: Tue, 18 Apr 2017 06:13:54 -0600	[thread overview]
Message-ID: <58F61F2202000078001518F0@prv-mh.provo.novell.com> (raw)
In-Reply-To: <20170327104429.99992-2-roger.pau@citrix.com>

>>> On 27.03.17 at 12:44, <roger.pau@citrix.com> wrote:
> --- a/xen/include/xen/hvm/irq.h
> +++ b/xen/include/xen/hvm/irq.h
> @@ -81,14 +81,16 @@ struct hvm_girq_dpci_mapping {
>  
>  /* Protected by domain's event_lock */
>  struct hvm_irq_dpci {
> -    /* Guest IRQ to guest device/intx mapping. */
> -    struct list_head girq[NR_HVM_IRQS];
>      /* Record of mapped ISA IRQs */
>      DECLARE_BITMAP(isairq_map, NR_ISAIRQS);
>      /* Record of mapped Links */
>      uint8_t link_cnt[NR_LINK];
> +    /* Guest IRQ to guest device/intx mapping. */
> +    struct list_head girq[];
>  };

Considering what you say in the overview mail I don't think the
comment can be moved without adjusting it, as it doesn't seem
to reflect Dom0 in any way. Which then puts under question
whether struct hvm_girq_dpci_mapping is the right data format
for Dom0 in the first place: With bus, device, and intx taken
out, all that's left if machine_gsi, and iirc you identity map GSIs.

Even if the array needed to remain, the sparseness of the GSI
space opens up the question whether using a simple array here
is the right choice.

The patch needs re-basing anyway afaict.

Jan


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  reply	other threads:[~2017-04-18 12:13 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2017-03-27 10:44 [PATCH 0/5] x86/dpci: bind legacy PCI interrupts to PVHv2 Dom0 Roger Pau Monne
2017-03-27 10:44 ` [PATCH 1/5] x86/dpci: allow hvm_irq_dpci to handle a variable number of GSIs Roger Pau Monne
2017-04-18 12:13   ` Jan Beulich [this message]
2017-04-18 14:36     ` Roger Pau Monne
2017-03-27 10:44 ` [PATCH 2/5] x86/ioapic: introduce helper to fetch triggering mode of GSI Roger Pau Monne
2017-04-18 12:19   ` Jan Beulich
2017-04-19 11:52     ` Roger Pau Monne
2017-03-27 10:44 ` [PATCH 3/5] x86/pt: introduce PT_IRQ_TYPE_GSI to bind GSIs to a PVH Dom0 Roger Pau Monne
2017-03-27 11:58   ` Roger Pau Monne
2017-03-27 10:44 ` [PATCH 4/5] x86/physdev: move prototypes of physdev_{map/unmap}_pirq to headers Roger Pau Monne
2017-04-18 12:21   ` Jan Beulich
2017-03-27 10:44 ` [PATCH 5/5] x86/vioapic: bind interrupts to PVH Dom0 Roger Pau Monne
2017-04-18 12:35   ` Jan Beulich
2017-04-18 13:44     ` Roger Pau Monne
2017-04-18 14:17       ` Jan Beulich
2017-03-27 12:19 ` [PATCH 0/5] x86/dpci: bind legacy PCI interrupts to PVHv2 Dom0 Jan Beulich
2017-03-27 12:56   ` Roger Pau Monne
2017-03-30 10:56     ` Roger Pau Monne
2017-03-30 11:50       ` Jan Beulich

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