From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id A3629C433EF for ; Thu, 21 Oct 2021 21:42:18 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 7B0CD6108B for ; Thu, 21 Oct 2021 21:42:18 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231952AbhJUVoe (ORCPT ); Thu, 21 Oct 2021 17:44:34 -0400 Received: from foss.arm.com ([217.140.110.172]:48026 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231138AbhJUVoc (ORCPT ); Thu, 21 Oct 2021 17:44:32 -0400 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EDFF8D6E; Thu, 21 Oct 2021 14:42:15 -0700 (PDT) Received: from [10.57.25.70] (unknown [10.57.25.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 34EF13F73D; Thu, 21 Oct 2021 14:42:14 -0700 (PDT) Subject: Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds To: Mathieu Poirier , Will Deacon , Greg KH Cc: Catalin Marinas , Anshuman Khandual , Mike Leach , Leo Yan , Marc Zyngier , Coresight ML , linux-arm-kernel , Linux Kernel Mailing List References: <20211019163153.3692640-1-suzuki.poulose@arm.com> <20211020154207.GA3456574@p14s> <20211021085313.GA15622@willie-the-truck> <20211021163531.GA3561043@p14s> <20211021164730.GA16889@willie-the-truck> From: Suzuki K Poulose Message-ID: <599078af-e321-01b0-65e8-69020393c00d@arm.com> Date: Thu, 21 Oct 2021 22:42:12 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-GB Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Mathieu, On 21/10/2021 18:11, Mathieu Poirier wrote: > On Thu, 21 Oct 2021 at 10:47, Will Deacon wrote: >> >> Hi Mathieu, >> >> [CC Greg] >> >> On Thu, Oct 21, 2021 at 10:35:31AM -0600, Mathieu Poirier wrote: >>> On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: >>>> On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: >>>>> On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: >>>>>> Suzuki K Poulose (15): >>>>>> arm64: Add Neoverse-N2, Cortex-A710 CPU part definition >>>>>> arm64: errata: Add detection for TRBE overwrite in FILL mode >>>>>> arm64: errata: Add workaround for TSB flush failures >>>>>> arm64: errata: Add detection for TRBE write to out-of-range >>>>>> coresight: trbe: Add a helper to calculate the trace generated >>>>>> coresight: trbe: Add a helper to pad a given buffer area >>>>>> coresight: trbe: Decouple buffer base from the hardware base >>>>>> coresight: trbe: Allow driver to choose a different alignment >>>>>> coresight: trbe: Add infrastructure for Errata handling >>>>>> coresight: trbe: Workaround TRBE errata overwrite in FILL mode >>>>>> coresight: trbe: Add a helper to determine the minimum buffer size >>>>>> coresight: trbe: Make sure we have enough space >>>>>> coresight: trbe: Work around write to out of range >>>>>> arm64: errata: Enable workaround for TRBE overwrite in FILL mode >>>>>> arm64: errata: Enable TRBE workaround for write to out-of-range >>>>>> address >>>>>> >>>>>> Documentation/arm64/silicon-errata.rst | 12 + >>>>>> arch/arm64/Kconfig | 111 ++++++ >>>>>> arch/arm64/include/asm/barrier.h | 16 +- >>>>>> arch/arm64/include/asm/cputype.h | 4 + >>>>>> arch/arm64/kernel/cpu_errata.c | 64 +++ >>>>>> arch/arm64/tools/cpucaps | 3 + >>>>>> drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- >>>>>> 7 files changed, 567 insertions(+), 37 deletions(-) >>>>> >>>>> I have applied this set. >>>> >>>> Mathieu -- the plan here (which we have discussed on the list [1]) is >>>> for the first four patches to be shared with arm64. Since you've gone >>>> ahead and applied the whole series, please can you provide me a stable >>>> branch with the first four patches only so that I can include them in >>>> the arm64 tree? >>>> >>>> Failing that, I can create a branch for you to pull and apply the remaining >>>> patches on top. >>>> >>>> Please let me know. >>> >>> Coresight patches flow through Greg's tree and as such the coresight-next tree >>> gets rebased anyway. I will remove the first 4 patches and push again. By the >>> way do you also want to pick up patches 14 and 16 since they are concerned with >>> "arch/arm64/Kconfig" or should I keep them? >> >> I'll take the first 4 and put them on a stable branch, which you can choose >> to pull if you like (but please don't rebase it or we'll end up with >> duplicate commits). The rest of the patches, including the later Kconfig >> changes, are yours but I doubt they'll apply cleanly without the initial >> changes. > > Right - I just had another look at them and what I suggested above won't work. > >> >> Are you sure Greg rebases everything? That sounds a bit weird to me, as it >> means it's impossible to share branches with other trees. How do you usually >> handle this situation? > > Greg applies the patches I send to him near the end of every cycle - > see this one [1] as an example. Unfortunately that way of working > makes it hard to deal with patchsets such as this one. > > To move forward you can either pick up this whole series (just add my > RB to all the CS patches) or I start sending pull requests to Greg. I don't think that may work well, as the CoreSight bits in the series depend on what is in coresight/next. So this series can't be pulled in to arm64 without what is already in coresight/next. Suzuki From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 6B5BEC433EF for ; Thu, 21 Oct 2021 21:43:50 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 3189A6128E for ; Thu, 21 Oct 2021 21:43:50 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org 3189A6128E Authentication-Results: mail.kernel.org; dmarc=fail (p=none dis=none) header.from=arm.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=lists.infradead.org DKIM-Signature: v=1; a=rsa-sha256; q=dns/txt; c=relaxed/relaxed; d=lists.infradead.org; s=bombadil.20210309; h=Sender:Content-Type: Content-Transfer-Encoding:List-Subscribe:List-Help:List-Post:List-Archive: List-Unsubscribe:List-Id:In-Reply-To:MIME-Version:Date:Message-ID:From: References:Cc:To:Subject:Reply-To:Content-ID:Content-Description:Resent-Date: Resent-From:Resent-Sender:Resent-To:Resent-Cc:Resent-Message-ID:List-Owner; bh=GL+HibLEGcKm9VMn6Y6B//g9fIyW1phGZnbVFPJqtes=; b=ZE6XXAVgvWjfLn6WDvq3one7Ec pFSQzVIChqzGzUXFABLfazfBF8x1sqhxrDm/SyQZKjlKRWLGYt8IZ/aHsU0/GB7WPTr/Y98V6bpOm 7gCS1Y7qmc0obXam1HDqSSsyMnSfG1aGL/UkJw0nItBUgeyUnMTP5tLBAF+LlLdCaqy38iIHAAAt0 BdnjtETsDd65EkS5YEjt9+Eq/WPRWI3HNlWA3wlp9XIJUF+AARL3hKmrLfwnBhgLHKN9fYRI34Av/ tvVOTYDw1tuNTYe83AMblXwMHzpiNeWwLJko9W64cH4SoOOvw2GWJGym9/DJ02uHAz+ve5KXdiIrt waUl16/Q==; Received: from localhost ([::1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdfpQ-009CLL-KB; Thu, 21 Oct 2021 21:42:24 +0000 Received: from foss.arm.com ([217.140.110.172]) by bombadil.infradead.org with esmtp (Exim 4.94.2 #2 (Red Hat Linux)) id 1mdfpM-009CKf-QW for linux-arm-kernel@lists.infradead.org; Thu, 21 Oct 2021 21:42:22 +0000 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id EDFF8D6E; Thu, 21 Oct 2021 14:42:15 -0700 (PDT) Received: from [10.57.25.70] (unknown [10.57.25.70]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 34EF13F73D; Thu, 21 Oct 2021 14:42:14 -0700 (PDT) Subject: Re: [PATCH v6 00/15] arm64: Self-hosted trace related errata workarounds To: Mathieu Poirier , Will Deacon , Greg KH Cc: Catalin Marinas , Anshuman Khandual , Mike Leach , Leo Yan , Marc Zyngier , Coresight ML , linux-arm-kernel , Linux Kernel Mailing List References: <20211019163153.3692640-1-suzuki.poulose@arm.com> <20211020154207.GA3456574@p14s> <20211021085313.GA15622@willie-the-truck> <20211021163531.GA3561043@p14s> <20211021164730.GA16889@willie-the-truck> From: Suzuki K Poulose Message-ID: <599078af-e321-01b0-65e8-69020393c00d@arm.com> Date: Thu, 21 Oct 2021 22:42:12 +0100 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Language: en-GB X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20211021_144221_020070_1817C64A X-CRM114-Status: GOOD ( 26.36 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Transfer-Encoding: 7bit Content-Type: text/plain; charset="us-ascii"; Format="flowed" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Mathieu, On 21/10/2021 18:11, Mathieu Poirier wrote: > On Thu, 21 Oct 2021 at 10:47, Will Deacon wrote: >> >> Hi Mathieu, >> >> [CC Greg] >> >> On Thu, Oct 21, 2021 at 10:35:31AM -0600, Mathieu Poirier wrote: >>> On Thu, Oct 21, 2021 at 09:53:14AM +0100, Will Deacon wrote: >>>> On Wed, Oct 20, 2021 at 09:42:07AM -0600, Mathieu Poirier wrote: >>>>> On Tue, Oct 19, 2021 at 05:31:38PM +0100, Suzuki K Poulose wrote: >>>>>> Suzuki K Poulose (15): >>>>>> arm64: Add Neoverse-N2, Cortex-A710 CPU part definition >>>>>> arm64: errata: Add detection for TRBE overwrite in FILL mode >>>>>> arm64: errata: Add workaround for TSB flush failures >>>>>> arm64: errata: Add detection for TRBE write to out-of-range >>>>>> coresight: trbe: Add a helper to calculate the trace generated >>>>>> coresight: trbe: Add a helper to pad a given buffer area >>>>>> coresight: trbe: Decouple buffer base from the hardware base >>>>>> coresight: trbe: Allow driver to choose a different alignment >>>>>> coresight: trbe: Add infrastructure for Errata handling >>>>>> coresight: trbe: Workaround TRBE errata overwrite in FILL mode >>>>>> coresight: trbe: Add a helper to determine the minimum buffer size >>>>>> coresight: trbe: Make sure we have enough space >>>>>> coresight: trbe: Work around write to out of range >>>>>> arm64: errata: Enable workaround for TRBE overwrite in FILL mode >>>>>> arm64: errata: Enable TRBE workaround for write to out-of-range >>>>>> address >>>>>> >>>>>> Documentation/arm64/silicon-errata.rst | 12 + >>>>>> arch/arm64/Kconfig | 111 ++++++ >>>>>> arch/arm64/include/asm/barrier.h | 16 +- >>>>>> arch/arm64/include/asm/cputype.h | 4 + >>>>>> arch/arm64/kernel/cpu_errata.c | 64 +++ >>>>>> arch/arm64/tools/cpucaps | 3 + >>>>>> drivers/hwtracing/coresight/coresight-trbe.c | 394 +++++++++++++++++-- >>>>>> 7 files changed, 567 insertions(+), 37 deletions(-) >>>>> >>>>> I have applied this set. >>>> >>>> Mathieu -- the plan here (which we have discussed on the list [1]) is >>>> for the first four patches to be shared with arm64. Since you've gone >>>> ahead and applied the whole series, please can you provide me a stable >>>> branch with the first four patches only so that I can include them in >>>> the arm64 tree? >>>> >>>> Failing that, I can create a branch for you to pull and apply the remaining >>>> patches on top. >>>> >>>> Please let me know. >>> >>> Coresight patches flow through Greg's tree and as such the coresight-next tree >>> gets rebased anyway. I will remove the first 4 patches and push again. By the >>> way do you also want to pick up patches 14 and 16 since they are concerned with >>> "arch/arm64/Kconfig" or should I keep them? >> >> I'll take the first 4 and put them on a stable branch, which you can choose >> to pull if you like (but please don't rebase it or we'll end up with >> duplicate commits). The rest of the patches, including the later Kconfig >> changes, are yours but I doubt they'll apply cleanly without the initial >> changes. > > Right - I just had another look at them and what I suggested above won't work. > >> >> Are you sure Greg rebases everything? That sounds a bit weird to me, as it >> means it's impossible to share branches with other trees. How do you usually >> handle this situation? > > Greg applies the patches I send to him near the end of every cycle - > see this one [1] as an example. Unfortunately that way of working > makes it hard to deal with patchsets such as this one. > > To move forward you can either pick up this whole series (just add my > RB to all the CS patches) or I start sending pull requests to Greg. I don't think that may work well, as the CoreSight bits in the series depend on what is in coresight/next. So this series can't be pulled in to arm64 without what is already in coresight/next. Suzuki _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel