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[83.9.31.184]) by smtp.gmail.com with ESMTPSA id o12-20020ac24e8c000000b004cb131751dcsm123810lfr.158.2022.12.27.04.19.23 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 27 Dec 2022 04:19:24 -0800 (PST) Message-ID: <59d18498-a56f-a992-f3f3-1fc2de308d72@linaro.org> Date: Tue, 27 Dec 2022 13:19:22 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.6.0 Subject: Re: [RFC PATCH 07/12] clk: qcom: gcc-apq8084: add GCC_MMSS_GPLL0_CLK_SRC Content-Language: en-US To: Dmitry Baryshkov Cc: Andy Gross , Bjorn Andersson , Stephen Boyd , Michael Turquette , Rob Herring , Krzysztof Kozlowski , Taniya Das , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, devicetree@vger.kernel.org References: <20221227013225.2847382-1-dmitry.baryshkov@linaro.org> <20221227013225.2847382-8-dmitry.baryshkov@linaro.org> From: Konrad Dybcio In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arm-msm@vger.kernel.org On 27.12.2022 13:17, Dmitry Baryshkov wrote: > On Tue, 27 Dec 2022 at 13:58, Konrad Dybcio wrote: >> >> >> >> On 27.12.2022 02:32, Dmitry Baryshkov wrote: >>> Add the GCC_MMSS_GPLL0_CLK_SRC, the branch clock gating gpll0 clock for >>> the multimedia subsystem. >>> >>> Signed-off-by: Dmitry Baryshkov >>> --- >> I'm thinking whether it would maybe make sense to put 8974 >> and 8084 clocks in a single driver.. They seem close to identical. > > Unfortunately the bindings are quite different. So even if we pack > both gcc drivers into a single one, we'd still have to cope with > different numeric ids. > The only sensible solution that I have in mind is to have a common C > file, containing common clock definitions. Right, let's forget it then. Konrad > >> >> Reviewed-by: Konrad Dybcio >> >> Konrad >>> drivers/clk/qcom/gcc-apq8084.c | 14 ++++++++++++++ >>> 1 file changed, 14 insertions(+) >>> >>> diff --git a/drivers/clk/qcom/gcc-apq8084.c b/drivers/clk/qcom/gcc-apq8084.c >>> index c26e222c78d4..7085d2ccae49 100644 >>> --- a/drivers/clk/qcom/gcc-apq8084.c >>> +++ b/drivers/clk/qcom/gcc-apq8084.c >>> @@ -1382,6 +1382,19 @@ static struct clk_rcg2 usb_hsic_system_clk_src = { >>> }, >>> }; >>> >>> +static struct clk_regmap gcc_mmss_gpll0_clk_src = { >>> + .enable_reg = 0x1484, >>> + .enable_mask = BIT(26), >>> + .hw.init = &(struct clk_init_data){ >>> + .name = "mmss_gpll0_vote", >>> + .parent_hws = (const struct clk_hw*[]){ >>> + &gpll0_vote.hw, >>> + }, >>> + .num_parents = 1, >>> + .ops = &clk_branch_simple_ops, >>> + }, >>> +}; >>> + >>> static struct clk_branch gcc_bam_dma_ahb_clk = { >>> .halt_reg = 0x0d44, >>> .halt_check = BRANCH_HALT_VOTED, >>> @@ -3480,6 +3493,7 @@ static struct clk_regmap *gcc_apq8084_clocks[] = { >>> [GCC_USB_HSIC_IO_CAL_SLEEP_CLK] = &gcc_usb_hsic_io_cal_sleep_clk.clkr, >>> [GCC_USB_HSIC_MOCK_UTMI_CLK] = &gcc_usb_hsic_mock_utmi_clk.clkr, >>> [GCC_USB_HSIC_SYSTEM_CLK] = &gcc_usb_hsic_system_clk.clkr, >>> + [GCC_MMSS_GPLL0_CLK_SRC] = &gcc_mmss_gpll0_clk_src, >>> }; >>> >>> static struct gdsc *gcc_apq8084_gdscs[] = { > > >