From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1758189AbdLVJiq (ORCPT ); Fri, 22 Dec 2017 04:38:46 -0500 Received: from szxga05-in.huawei.com ([45.249.212.191]:2756 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1757805AbdLVJij (ORCPT ); Fri, 22 Dec 2017 04:38:39 -0500 Subject: Re: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information To: Valentin Schneider , References: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> CC: Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Dietmar Eggemann , , From: Wei Xu Message-ID: <5A3CD286.2010705@hisilicon.com> Date: Fri, 22 Dec 2017 09:38:14 +0000 User-Agent: Mozilla/5.0 (Windows NT 6.1; WOW64; rv:38.0) Gecko/20100101 Thunderbird/38.6.0 MIME-Version: 1.0 In-Reply-To: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit X-Originating-IP: [10.202.226.123] X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Valentin, On 2017/12/13 14:21, Valentin Schneider wrote: > The following dt entries are added: > cpus [0-3] (Cortex A53): > - capacity-dmips-mhz = <592>; > > cpus [4-7] (Cortex A73): > - capacity-dmips-mhz = <1024>; > > Those values were obtained by running dhrystone 2.1 on a > HiKey960 with the following procedure: > - Offline all CPUs but CPU0 (A53) > - Set CPU0 frequency to maximum > - Run Dhrystone 2.1 for 20 seconds > > - Offline all CPUs but CPU4 (A73) > - set CPU4 frequency to maximum > - Run Dhrystone 2.1 for 20 seconds > > The results are as follows: > A53: 129633887 loops > A73: 287034147 loops > > By scaling those values so that the A73s use 1024, we end up with 462 > for the A53s. However, they have different maximum frequencies: > 1.844GHz for A53s and 2.362GHz for A73s. Thus, we can scale the A53 > value to truly represent dmips per MHz, and we end up with 592. > > The impact of this change can be verified on HiKey960: > > $ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq > 1844000 > 1844000 > 1844000 > 1844000 > 2362000 > 2362000 > 2362000 > 2362000 > > $ cat /sys/devices/system/cpu/cpu*/cpu_capacity > 462 > 462 > 462 > 462 > 1024 > 1024 > 1024 > 1024 > > Signed-off-by: Valentin Schneider > --- Applied into hisilicon dt tree. Thanks! Best Regards, Wei > arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > index ab0b95b..04a8d28 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > @@ -61,6 +61,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu1: cpu@1 { > @@ -70,6 +71,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu2: cpu@2 { > @@ -79,6 +81,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu3: cpu@3 { > @@ -88,6 +91,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu4: cpu@100 { > @@ -101,6 +105,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > cpu5: cpu@101 { > @@ -114,6 +119,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > cpu6: cpu@102 { > @@ -127,6 +133,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > cpu7: cpu@103 { > @@ -140,6 +147,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > idle-states { > -- > 2.7.4 > > > . > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Wei Xu Subject: Re: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information Date: Fri, 22 Dec 2017 09:38:14 +0000 Message-ID: <5A3CD286.2010705@hisilicon.com> References: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> Sender: linux-kernel-owner@vger.kernel.org To: Valentin Schneider , linux-kernel@vger.kernel.org Cc: Rob Herring , Mark Rutland , Catalin Marinas , Will Deacon , Dietmar Eggemann , linux-arm-kernel@lists.infradead.org, devicetree@vger.kernel.org List-Id: devicetree@vger.kernel.org Hi Valentin, On 2017/12/13 14:21, Valentin Schneider wrote: > The following dt entries are added: > cpus [0-3] (Cortex A53): > - capacity-dmips-mhz = <592>; > > cpus [4-7] (Cortex A73): > - capacity-dmips-mhz = <1024>; > > Those values were obtained by running dhrystone 2.1 on a > HiKey960 with the following procedure: > - Offline all CPUs but CPU0 (A53) > - Set CPU0 frequency to maximum > - Run Dhrystone 2.1 for 20 seconds > > - Offline all CPUs but CPU4 (A73) > - set CPU4 frequency to maximum > - Run Dhrystone 2.1 for 20 seconds > > The results are as follows: > A53: 129633887 loops > A73: 287034147 loops > > By scaling those values so that the A73s use 1024, we end up with 462 > for the A53s. However, they have different maximum frequencies: > 1.844GHz for A53s and 2.362GHz for A73s. Thus, we can scale the A53 > value to truly represent dmips per MHz, and we end up with 592. > > The impact of this change can be verified on HiKey960: > > $ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq > 1844000 > 1844000 > 1844000 > 1844000 > 2362000 > 2362000 > 2362000 > 2362000 > > $ cat /sys/devices/system/cpu/cpu*/cpu_capacity > 462 > 462 > 462 > 462 > 1024 > 1024 > 1024 > 1024 > > Signed-off-by: Valentin Schneider > --- Applied into hisilicon dt tree. Thanks! Best Regards, Wei > arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > index ab0b95b..04a8d28 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > @@ -61,6 +61,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu1: cpu@1 { > @@ -70,6 +71,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu2: cpu@2 { > @@ -79,6 +81,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu3: cpu@3 { > @@ -88,6 +91,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu4: cpu@100 { > @@ -101,6 +105,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > cpu5: cpu@101 { > @@ -114,6 +119,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > cpu6: cpu@102 { > @@ -127,6 +133,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > cpu7: cpu@103 { > @@ -140,6 +147,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > idle-states { > -- > 2.7.4 > > > . > From mboxrd@z Thu Jan 1 00:00:00 1970 From: xuwei5@hisilicon.com (Wei Xu) Date: Fri, 22 Dec 2017 09:38:14 +0000 Subject: [PATCH] arm64: dts: hisilicon: Add hi3660 cpu capacity-dmips-mhz information In-Reply-To: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> References: <1513174866-6678-1-git-send-email-valentin.schneider@arm.com> Message-ID: <5A3CD286.2010705@hisilicon.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Valentin, On 2017/12/13 14:21, Valentin Schneider wrote: > The following dt entries are added: > cpus [0-3] (Cortex A53): > - capacity-dmips-mhz = <592>; > > cpus [4-7] (Cortex A73): > - capacity-dmips-mhz = <1024>; > > Those values were obtained by running dhrystone 2.1 on a > HiKey960 with the following procedure: > - Offline all CPUs but CPU0 (A53) > - Set CPU0 frequency to maximum > - Run Dhrystone 2.1 for 20 seconds > > - Offline all CPUs but CPU4 (A73) > - set CPU4 frequency to maximum > - Run Dhrystone 2.1 for 20 seconds > > The results are as follows: > A53: 129633887 loops > A73: 287034147 loops > > By scaling those values so that the A73s use 1024, we end up with 462 > for the A53s. However, they have different maximum frequencies: > 1.844GHz for A53s and 2.362GHz for A73s. Thus, we can scale the A53 > value to truly represent dmips per MHz, and we end up with 592. > > The impact of this change can be verified on HiKey960: > > $ cat /sys/devices/system/cpu/cpu*/cpufreq/scaling_cur_freq > 1844000 > 1844000 > 1844000 > 1844000 > 2362000 > 2362000 > 2362000 > 2362000 > > $ cat /sys/devices/system/cpu/cpu*/cpu_capacity > 462 > 462 > 462 > 462 > 1024 > 1024 > 1024 > 1024 > > Signed-off-by: Valentin Schneider > --- Applied into hisilicon dt tree. Thanks! Best Regards, Wei > arch/arm64/boot/dts/hisilicon/hi3660.dtsi | 8 ++++++++ > 1 file changed, 8 insertions(+) > > diff --git a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > index ab0b95b..04a8d28 100644 > --- a/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > +++ b/arch/arm64/boot/dts/hisilicon/hi3660.dtsi > @@ -61,6 +61,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu1: cpu at 1 { > @@ -70,6 +71,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu2: cpu at 2 { > @@ -79,6 +81,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu3: cpu at 3 { > @@ -88,6 +91,7 @@ > enable-method = "psci"; > next-level-cache = <&A53_L2>; > cpu-idle-states = <&CPU_SLEEP &CLUSTER_SLEEP_0>; > + capacity-dmips-mhz = <592>; > }; > > cpu4: cpu at 100 { > @@ -101,6 +105,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > cpu5: cpu at 101 { > @@ -114,6 +119,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > cpu6: cpu at 102 { > @@ -127,6 +133,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > cpu7: cpu at 103 { > @@ -140,6 +147,7 @@ > &CPU_SLEEP > &CLUSTER_SLEEP_1 > >; > + capacity-dmips-mhz = <1024>; > }; > > idle-states { > -- > 2.7.4 > > > . >