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From: "Jan Beulich" <JBeulich@suse.com>
To: Andrew Cooper <andrew.cooper3@citrix.com>,
	Roger Pau Monne <roger.pau@citrix.com>
Cc: xen-devel@lists.xenproject.org
Subject: Re: [PATCH RFC 3/3] xtf: add minimal HPET functionality test
Date: Thu, 01 Mar 2018 05:57:18 -0700	[thread overview]
Message-ID: <5A9806BE02000078001AD49A@prv-mh.provo.novell.com> (raw)
In-Reply-To: <ae34d54d-d44e-a624-5e60-3d10854062e3@citrix.com>

>>> On 01.03.18 at 12:46, <andrew.cooper3@citrix.com> wrote:
> On 23/02/18 13:27, Roger Pau Monne wrote:
>> Add a basic HPET functionality test, note that this test requires the
>> HPET to support level triggered interrupts.
>>
>> Further improvements should add support for interrupt delivery, and
>> testing all the available timers.
>>
>> Signed-off-by: Roger Pau Monné <roger.pau@citrix.com>
>> ---
>> Cc: Andrew Cooper <andrew.cooper3@citrix.com>
>> ---
>>  arch/x86/include/arch/lib.h |  14 ++++
>>  docs/all-tests.dox          |   2 +
>>  tests/hpet/Makefile         |   9 +++
>>  tests/hpet/main.c           | 187 
> ++++++++++++++++++++++++++++++++++++++++++++
>>  4 files changed, 212 insertions(+)
>>  create mode 100644 tests/hpet/Makefile
>>  create mode 100644 tests/hpet/main.c
>>
>> diff --git a/arch/x86/include/arch/lib.h b/arch/x86/include/arch/lib.h
>> index 6714bdc..3400890 100644
>> --- a/arch/x86/include/arch/lib.h
>> +++ b/arch/x86/include/arch/lib.h
>> @@ -392,6 +392,20 @@ static inline void write_xcr0(uint64_t xcr0)
>>      xsetbv(0, xcr0);
>>  }
>>  
>> +static inline uint64_t rdtsc(void)
>> +{
>> +    uint32_t low, high;
>> +
>> +    asm volatile ("rdtsc" : "=a" (low), "=d" (high));
> 
> For my own timing purposes, I've been using rdtscp because it is
> strictly more helpful, but this isn't a general solution.
> 
> For rdtsc, (contrary to the way the other thread is progressing), what
> matters is a dispatch serialising event, which is different to an
> architecturally serialising event.
> 
> The easiest fix for now is to unconditionally use mfence, leaving a
> comment saying that this should be lfence on Intel and when the AMD
> pipeline is configured correctly.  Please name the function
> rdtscp_ordered() though, to distinguish it from a plain rdtsc instruction.

Interesting. Right above you say "dispatch serialising", but then
you suggest MFENCE, which isn't on Intel? It's those differences
that I've been trying to explain on that other part of the thread
(apparently with little success, seeing your "contrary to").

Jan

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      reply	other threads:[~2018-03-01 12:57 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-02-23 13:27 [PATCH RFC 0/3] hpet: add support for level triggered interrupts Roger Pau Monne
2018-02-23 13:27 ` [PATCH RFC 1/3] x86/vpt: execute callbacks for masked interrupts Roger Pau Monne
2018-02-26 12:35   ` Wei Liu
2018-02-26 12:48     ` Roger Pau Monné
2018-02-26 13:04       ` Jan Beulich
2018-02-26 14:12         ` Roger Pau Monné
2018-02-23 13:27 ` [PATCH RFC 2/3] vhpet: add support for level triggered interrupts Roger Pau Monne
2018-02-23 13:27 ` [PATCH RFC 3/3] xtf: add minimal HPET functionality test Roger Pau Monne
2018-02-23 19:07   ` Wei Liu
2018-02-28 15:37     ` Roger Pau Monné
2018-02-28 16:24       ` Jan Beulich
2018-03-01  9:55         ` Roger Pau Monné
2018-03-01 10:04           ` Jan Beulich
2018-03-01 10:14             ` Roger Pau Monné
2018-03-01 10:22               ` Jan Beulich
2018-03-01 11:46   ` Andrew Cooper
2018-03-01 12:57     ` Jan Beulich [this message]

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