[U-Boot] [PATCH v2 0/5] rockchip: Add a read-only efuse driver for the RK3399 (and derive serial# from fuses on the RK3399-Q7)

[U-Boot] [PATCH v2 0/5] rockchip: Add a read-only efuse driver for the RK3399 (and derive serial# from fuses on the RK3399-Q7)

[Philipp Tomsich]

As the RK3399-Q7 (Puma) differs from our previous modules in how we
can force an external boot (on the RK3399-Q7 this holds the eMMC and
SPI in reset, until an external signal is removed) through the 'BIOS
disable'-signal of the Qseven specification, we can't derive the
unique board id reliably from the eMMC's unique id.

Instead, for the RK3399-Q7, we rely on the efuse block of the RK3399
and use the (assumed to be unique) cpu_id region.

This patch-series adds the required infrastructure and switches the
RK3399-Q7 (puma_rk3399) over to this new infrastructure:
 - adds a rockchip-efuse driver as a misc-device (and permits requests
   for the clock gate listed in the DTS for the efuse node)
 - ports the CRC32-based 'serial#' derivation over from Linux
 - exposes the complete cpu_id field through 'cpuid#'

Changes in v2:
- added derivation of ethaddr from cpuid

Klaus Goger (1):
  rockchip: board: puma_rk3399: derive ethaddr from cpuid

Philipp Tomsich (4):
  rockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NS
  rockchip: efuse: add (misc) driver for RK3399 non-secure efuse block
  rockchip: board: puma_rk3399: add support for serial# and cpuid# via
    efuses
  rockchip: defconfig: puma-rk3399: enable RK3399 efuse driver

 board/theobroma-systems/puma_rk3399/puma-rk3399.c | 117 ++++++++++++++++
 configs/puma-rk3399_defconfig                     |   2 +
 drivers/clk/rockchip/clk_rk3399.c                 |   4 +
 drivers/misc/Kconfig                              |  14 ++
 drivers/misc/Makefile                             |   1 +
 drivers/misc/rockchip-efuse.c                     | 163 ++++++++++++++++++++++
 include/configs/puma_rk3399.h                     |   4 +
 7 files changed, 305 insertions(+)
 create mode 100644 drivers/misc/rockchip-efuse.c

-- 
1.9.1

[U-Boot] [PATCH v2 1/5] rockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NS

[Philipp Tomsich]

The (non-secure) efuse node in the DTS requests PCLK_EFUSE1024NS.
To allow us to add a efuse-driver (and more importantly, to allow
probes of such a driver to succeed), we need need to accept requests
for PCLK_EFUSE1024NS and return a non-error result.

As PCLK_EFUSE1024NS is enabled by default (i.e. after reset), we don't
implement any logic to manage this clock gate and simply assume that
the reset-default has not been changed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
---

Changes in v2: None

 drivers/clk/rockchip/clk_rk3399.c | 4 ++++
 1 file changed, 4 insertions(+)

diff --git a/drivers/clk/rockchip/clk_rk3399.c b/drivers/clk/rockchip/clk_rk3399.c
index 72395e2..4dbc1b0 100644
--- a/drivers/clk/rockchip/clk_rk3399.c
+++ b/drivers/clk/rockchip/clk_rk3399.c
@@ -882,6 +882,8 @@ static ulong rk3399_clk_get_rate(struct clk *clk)
 	case DCLK_VOP0:
 	case DCLK_VOP1:
 		break;
+	case PCLK_EFUSE1024NS:
+		break;
 	default:
 		return -ENOENT;
 	}
@@ -923,6 +925,8 @@ static ulong rk3399_clk_set_rate(struct clk *clk, ulong rate)
 	case SCLK_DDRCLK:
 		ret = rk3399_ddr_set_clk(priv->cru, rate);
 		break;
+	case PCLK_EFUSE1024NS:
+		break;
 	default:
 		return -ENOENT;
 	}
-- 
1.9.1

[U-Boot] [PATCH v2 2/5] rockchip: efuse: add (misc) driver for RK3399 non-secure efuse block

[Philipp Tomsich]

This adds a simple driver for reading the efuse block of the RK3399.
It should be easy enough to add drivers for other devices (e.g. the
RK3328, RK3368, etc.) by passing the device details via driver_data.

Unlike the kernel driver (using the nvmem subsystem), we don't expose
the efuse as multiple named cells, but rather as a linear memory that
can be read using misc_read(...).

The primary use case (as of today) is the generation of a 'serial#'
(and a 'cpuid#') environment variable for the RK3399-Q7 (Puma)
system-on-module.

Note that this adds a debug-only (i.e. only if DEBUG is defined)
command 'rk3399_dump_efuses' that dumps the efuse block's content.
N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to
      include a SoC-name (together with a comment in the function) to
      remind whoever adds support for additional SoCs that this
      function currently makes assumptions regarding the size of the
      fuse-box based on the RK3399. The hope is that the function is
      adjusted to reflect any changes resulting from generalising the
      driver for multiple SoCs and is then renamed.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
---

Changes in v2: None

 drivers/misc/Kconfig          |  14 ++++
 drivers/misc/Makefile         |   1 +
 drivers/misc/rockchip-efuse.c | 163 ++++++++++++++++++++++++++++++++++++++++++
 3 files changed, 178 insertions(+)
 create mode 100644 drivers/misc/rockchip-efuse.c

diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 1aae4bc..ed57414 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -20,6 +20,19 @@ config ALTERA_SYSID
 	  Select this to enable a sysid for Altera devices. Please find
 	  details on the "Embedded Peripherals IP User Guide" of Altera.
 
+config ROCKCHIP_EFUSE
+        bool "Rockchip e-fuse support"
+	depends on MISC
+	help
+	  Enable (read-only) access for the e-fuse block found in Rockchip
+	  SoCs: accesses can either be made using byte addressing and a length
+	  or through child-nodes that are generated based on the e-fuse map
+	  retrieved from the DTS.
+
+	  This driver currently supports the RK3399 only, but can easily be
+	  extended (by porting the read function from the Linux kernel sources)
+	  to support other recent Rockchip devices.
+
 config CMD_CROS_EC
 	bool "Enable crosec command"
 	depends on CROS_EC
@@ -167,4 +180,5 @@ config I2C_EEPROM
 	depends on MISC
 	help
 	  Enable a generic driver for EEPROMs attached via I2C.
+
 endmenu
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index e3151ea..77196fd 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -51,3 +51,4 @@ obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
 obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
 obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
 obj-$(CONFIG_QFW) += qfw.o
+obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
new file mode 100644
index 0000000..6eb3616
--- /dev/null
+++ b/drivers/misc/rockchip-efuse.c
@@ -0,0 +1,163 @@
+/*
+ * eFuse driver for Rockchip devices
+ *
+ * Copyright 2017, Theobroma Systems Design und Consulting GmbH
+ * Written by Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
+ *
+ * SPDX-License-Identifier:	GPL-2.0+
+ */
+
+#define DEBUG
+
+#include <common.h>
+#include <asm/io.h>
+#include <command.h>
+#include <display_options.h>
+#include <dm.h>
+#include <linux/bitops.h>
+#include <linux/delay.h>
+#include <misc.h>
+
+#define RK3399_A_SHIFT          16
+#define RK3399_A_MASK           0x3ff
+#define RK3399_NFUSES           32
+#define RK3399_BYTES_PER_FUSE   4
+#define RK3399_STROBSFTSEL      BIT(9)
+#define RK3399_RSB              BIT(7)
+#define RK3399_PD               BIT(5)
+#define RK3399_PGENB            BIT(3)
+#define RK3399_LOAD             BIT(2)
+#define RK3399_STROBE           BIT(1)
+#define RK3399_CSB              BIT(0)
+
+struct rockchip_efuse_regs {
+	u32 ctrl;      /* 0x00  efuse control register */
+	u32 dout;      /* 0x04  efuse data out register */
+	u32 rf;        /* 0x08  efuse redundancy bit used register */
+	u32 _rsvd0;
+	u32 jtag_pass; /* 0x10  JTAG password */
+	u32 strobe_finish_ctrl;
+		       /* 0x14	efuse strobe finish control register */
+};
+
+struct rockchip_efuse_platdata {
+	void __iomem *base;
+	struct clk *clk;
+};
+
+#if defined(DEBUG)
+static int dump_efuses(cmd_tbl_t *cmdtp, int flag,
+		       int argc, char * const argv[])
+{
+	/*
+	 * N.B.: This function is tailored towards the RK3399 and assumes that
+	 *       there's always 32 fuses x 32 bits (i.e. 128 bytes of data) to
+	 *       be read.
+	 */
+
+	struct udevice *dev;
+	u8 fuses[128];
+	int ret;
+
+	/* the first misc device will be used */
+	ret = uclass_first_device_err(UCLASS_MISC, &dev);
+	if (ret) {
+		printf("%s: no misc-device found\n", __func__);
+		return 0;
+	}
+
+	ret = misc_read(dev, 0, &fuses, sizeof(fuses));
+	if (ret) {
+		printf("%s: misc_read failed\n", __func__);
+		return 0;
+	}
+
+	printf("efuse-contents:\n");
+	print_buffer(0, fuses, 1, 128, 16);
+
+	return 0;
+}
+
+U_BOOT_CMD(
+	rk3399_dump_efuses, 1, 1, dump_efuses,
+	"Dump the content of the efuses",
+	""
+);
+#endif
+
+static int rockchip_rk3399_efuse_read(struct udevice *dev, int offset,
+				      void *buf, int size)
+{
+	struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
+	struct rockchip_efuse_regs *efuse =
+		(struct rockchip_efuse_regs *)plat->base;
+
+	unsigned int addr_start, addr_end, addr_offset;
+	u32 out_value;
+	u8  bytes[RK3399_NFUSES * RK3399_BYTES_PER_FUSE];
+	int i = 0;
+	u32 addr;
+
+	addr_start = offset / RK3399_BYTES_PER_FUSE;
+	addr_offset = offset % RK3399_BYTES_PER_FUSE;
+	addr_end = DIV_ROUND_UP(offset + size, RK3399_BYTES_PER_FUSE);
+
+	/* cap to the size of the efuse block */
+	if (addr_end > RK3399_NFUSES)
+		addr_end = RK3399_NFUSES;
+
+	writel(RK3399_LOAD | RK3399_PGENB | RK3399_STROBSFTSEL | RK3399_RSB,
+	       &efuse->ctrl);
+	udelay(1);
+	for (addr = addr_start; addr < addr_end; addr++) {
+		setbits_le32(&efuse->ctrl,
+			     RK3399_STROBE | (addr << RK3399_A_SHIFT));
+		udelay(1);
+		out_value = readl(&efuse->dout);
+		clrbits_le32(&efuse->ctrl, RK3399_STROBE);
+		udelay(1);
+
+		memcpy(&bytes[i], &out_value, RK3399_BYTES_PER_FUSE);
+		i += RK3399_BYTES_PER_FUSE;
+	}
+
+	/* Switch to standby mode */
+	writel(RK3399_PD | RK3399_CSB, &efuse->ctrl);
+
+	memcpy(buf, bytes + addr_offset, size);
+
+	return 0;
+}
+
+static int rockchip_efuse_read(struct udevice *dev, int offset,
+			       void *buf, int size)
+{
+	return rockchip_rk3399_efuse_read(dev, offset, buf, size);
+}
+
+static const struct misc_ops rockchip_efuse_ops = {
+	.read = rockchip_efuse_read,
+};
+
+static int rockchip_efuse_ofdata_to_platdata(struct udevice *dev)
+{
+	struct rockchip_efuse_platdata *plat = dev_get_platdata(dev);
+
+	plat->base = (void *)dev_get_addr(dev);
+	return 0;
+}
+
+static const struct udevice_id rockchip_efuse_ids[] = {
+	{ .compatible = "rockchip,rk3399-efuse" },
+	{}
+};
+
+U_BOOT_DRIVER(rockchip_efuse) = {
+	.name = "rockchip_efuse",
+	.id = UCLASS_MISC,
+	.of_match = rockchip_efuse_ids,
+	.ofdata_to_platdata = rockchip_efuse_ofdata_to_platdata,
+	.platdata_auto_alloc_size = sizeof(struct rockchip_efuse_platdata),
+	.ops = &rockchip_efuse_ops,
+};
+
-- 
1.9.1

[U-Boot] [PATCH v2 3/5] rockchip: board: puma_rk3399: add support for serial# and cpuid# via efuses

[Philipp Tomsich]

With our efuse driver for the RK3399 ready, we can add the
board-specific code that consumes the cpuid from the efuse block and
postprocesses it into the system serial (using the same CRC32 based
derivation as in Linux).

We expose the cpuid via two distinct environment variables:
   serial# - the serial number, as derived in Linux
   cpuid#  - the raw 16 byte CPU id field from the fuse block

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
---

Changes in v2: None

 board/theobroma-systems/puma_rk3399/puma-rk3399.c | 79 +++++++++++++++++++++++
 include/configs/puma_rk3399.h                     |  4 ++
 2 files changed, 83 insertions(+)

diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index fb4d31e..b434ad5 100644
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -7,9 +7,13 @@
 #include <dm.h>
 #include <dm/pinctrl.h>
 #include <dm/uclass-internal.h>
+#include <misc.h>
 #include <asm/arch/periph.h>
 #include <power/regulator.h>
 
+#define RK3399_CPUID_OFF  0x7
+#define RK3399_CPUID_LEN  0x10
+
 DECLARE_GLOBAL_DATA_PTR;
 
 int board_init(void)
@@ -55,6 +59,81 @@ out:
 	return 0;
 }
 
+static void setup_serial(void)
+{
+#if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
+	struct udevice *dev;
+	int ret, i;
+	u8 cpuid[RK3399_CPUID_LEN];
+	u8 low[RK3399_CPUID_LEN/2], high[RK3399_CPUID_LEN/2];
+	char cpuid_str[RK3399_CPUID_LEN * 2 + 1];
+	u64 serialno;
+	char serialno_str[16];
+
+	/* the first misc device will be used */
+	ret = uclass_get_device(UCLASS_MISC, 0, &dev);
+	if (ret) {
+		debug("%s: could not find efuse device\n", __func__);
+		return;
+	}
+
+	/* read the cpu_id range from the efuses */
+	ret = misc_read(dev, RK3399_CPUID_OFF, &cpuid, sizeof(cpuid));
+	if (ret) {
+		debug("%s: reading cpuid from the efuses failed\n",
+		      __func__);
+		return;
+	}
+
+	memset(cpuid_str, 0, sizeof(cpuid_str));
+	for (i = 0; i < 16; i++)
+		sprintf(&cpuid_str[i * 2], "%02x", cpuid[i]);
+
+	debug("cpuid: %s\n", cpuid_str);
+
+	/*
+	 * Mix the cpuid bytes using the same rules as in
+	 *   ${linux}/drivers/soc/rockchip/rockchip-cpuinfo.c
+	 */
+	for (i = 0; i < 8; i++) {
+		low[i] = cpuid[1 + (i << 1)];
+		high[i] = cpuid[i << 1];
+	}
+
+	serialno = crc32_no_comp(0, low, 8);
+	serialno |= (u64)crc32_no_comp(serialno, high, 8) << 32;
+	snprintf(serialno_str, sizeof(serialno_str), "%llx", serialno);
+
+	setenv("cpuid#", cpuid_str);
+	setenv("serial#", serialno_str);
+#endif
+
+	return;
+}
+
+int misc_init_r(void)
+{
+	setup_serial();
+
+	return 0;
+}
+
+#ifdef CONFIG_SERIAL_TAG
+void get_board_serial(struct tag_serialnr *serialnr)
+{
+	char *serial_string;
+	u64 serial = 0;
+
+	serial_string = getenv("serial#");
+
+	if (serial_string)
+		serial = simple_strtoull(serial_string, NULL, 16);
+
+	serialnr->high = (u32)(serial >> 32);
+	serialnr->low = (u32)(serial & 0xffffffff);
+}
+#endif
+
 int dram_init(void)
 {
 	gd->ram_size = 0x80000000;
diff --git a/include/configs/puma_rk3399.h b/include/configs/puma_rk3399.h
index fd62c72..4081362 100644
--- a/include/configs/puma_rk3399.h
+++ b/include/configs/puma_rk3399.h
@@ -22,6 +22,10 @@
 
 #define SDRAM_BANK_SIZE			(2UL << 30)
 
+#define CONFIG_MISC_INIT_R
+#define CONFIG_SERIAL_TAG
+#define CONFIG_ENV_OVERWRITE
+
 #define CONFIG_SYS_WHITE_ON_BLACK
 
 #endif
-- 
1.9.1

[U-Boot] [PATCH v2 4/5] rockchip: defconfig: puma-rk3399: enable RK3399 efuse driver

[Philipp Tomsich]

With everything in place (i.e. the new efuse driver, the clk-support
for the non-secure efuse block, and the board-specific functions to
derive 'serial#' from the cpu-id within the efuses), enable this in
the RK3399-Q7 defconfig.

Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>

---

Changes in v2: None

 configs/puma-rk3399_defconfig | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/configs/puma-rk3399_defconfig b/configs/puma-rk3399_defconfig
index 500f220..238dffb 100644
--- a/configs/puma-rk3399_defconfig
+++ b/configs/puma-rk3399_defconfig
@@ -37,6 +37,8 @@ CONFIG_SPL_SYSCON=y
 CONFIG_CLK=y
 CONFIG_SPL_CLK=y
 CONFIG_ROCKCHIP_GPIO=y
+CONFIG_MISC=y
+CONFIG_ROCKCHIP_EFUSE=y
 CONFIG_MMC_DW=y
 CONFIG_MMC_DW_ROCKCHIP=y
 CONFIG_MMC_SDHCI=y
-- 
1.9.1

[U-Boot] [PATCH v2 5/5] rockchip: board: puma_rk3399: derive ethaddr from cpuid

[Philipp Tomsich]

From: Klaus Goger <klaus.goger@theobroma-systems.com>

Generate a MAC address based on the cpuid available in the efuse
block: Use the first 6 byte of the cpuid's SHA256 hash and set the
locally administered bits. Also ensure that the multicast bit is
cleared.

The MAC address is only generated and set if there is no ethaddr
present in the saved environment.

Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>

---

Changes in v2:
- added derivation of ethaddr from cpuid

 board/theobroma-systems/puma_rk3399/puma-rk3399.c | 38 +++++++++++++++++++++++
 1 file changed, 38 insertions(+)

diff --git a/board/theobroma-systems/puma_rk3399/puma-rk3399.c b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
index b434ad5..e209ae0 100644
--- a/board/theobroma-systems/puma_rk3399/puma-rk3399.c
+++ b/board/theobroma-systems/puma_rk3399/puma-rk3399.c
@@ -10,6 +10,7 @@
 #include <misc.h>
 #include <asm/arch/periph.h>
 #include <power/regulator.h>
+#include <u-boot/sha256.h>
 
 #define RK3399_CPUID_OFF  0x7
 #define RK3399_CPUID_LEN  0x10
@@ -59,6 +60,42 @@ out:
 	return 0;
 }
 
+static void setup_macaddr(void)
+{
+#if CONFIG_IS_ENABLED(CMD_NET)
+	int ret;
+	const char *cpuid = getenv("cpuid#");
+	u8 hash[SHA256_SUM_LEN];
+	int size = sizeof(hash);
+	u8 mac_addr[6];
+
+	/* Only generate a MAC address, if none is set in the environment */
+	if (getenv("ethaddr"))
+		return;
+
+	if (!cpuid) {
+		debug("%s: could not retrieve 'cpuid#'\n", __func__);
+		return;
+	}
+
+	ret = hash_block("sha256", (void *)cpuid, strlen(cpuid), hash, &size);
+	if (ret) {
+		debug("%s: failed to calculate SHA256\n", __func__);
+		return;
+	}
+
+	/* Copy 6 bytes of the hash to base the MAC address on */
+	memcpy(mac_addr, hash, 6);
+
+	/* Make this a valid MAC address and set it */
+	mac_addr[0] &= 0xfe;  /* clear multicast bit */
+	mac_addr[0] |= 0x02;  /* set local assignment bit (IEEE802) */
+	eth_setenv_enetaddr("ethaddr", mac_addr);
+#endif
+
+	return;
+}
+
 static void setup_serial(void)
 {
 #if CONFIG_IS_ENABLED(ROCKCHIP_EFUSE)
@@ -114,6 +151,7 @@ static void setup_serial(void)
 int misc_init_r(void)
 {
 	setup_serial();
+	setup_macaddr();
 
 	return 0;
 }
-- 
1.9.1

[U-Boot] [PATCH v2 1/5] rockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NS

[Simon Glass]

On 28 April 2017 at 09:11, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The (non-secure) efuse node in the DTS requests PCLK_EFUSE1024NS.
> To allow us to add a efuse-driver (and more importantly, to allow
> probes of such a driver to succeed), we need need to accept requests
> for PCLK_EFUSE1024NS and return a non-error result.
>
> As PCLK_EFUSE1024NS is enabled by default (i.e. after reset), we don't
> implement any logic to manage this clock gate and simply assume that
> the reset-default has not been changed.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/clk/rockchip/clk_rk3399.c | 4 ++++
>  1 file changed, 4 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 2/5] rockchip: efuse: add (misc) driver for RK3399 non-secure efuse block

[Simon Glass]

Hi Philipp,

On 28 April 2017 at 09:11, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> This adds a simple driver for reading the efuse block of the RK3399.
> It should be easy enough to add drivers for other devices (e.g. the
> RK3328, RK3368, etc.) by passing the device details via driver_data.
>
> Unlike the kernel driver (using the nvmem subsystem), we don't expose
> the efuse as multiple named cells, but rather as a linear memory that
> can be read using misc_read(...).
>
> The primary use case (as of today) is the generation of a 'serial#'
> (and a 'cpuid#') environment variable for the RK3399-Q7 (Puma)
> system-on-module.
>
> Note that this adds a debug-only (i.e. only if DEBUG is defined)
> command 'rk3399_dump_efuses' that dumps the efuse block's content.
> N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to
>       include a SoC-name (together with a comment in the function) to
>       remind whoever adds support for additional SoCs that this
>       function currently makes assumptions regarding the size of the
>       fuse-box based on the RK3399. The hope is that the function is
>       adjusted to reflect any changes resulting from generalising the
>       driver for multiple SoCs and is then renamed.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/misc/Kconfig          |  14 ++++
>  drivers/misc/Makefile         |   1 +
>  drivers/misc/rockchip-efuse.c | 163 ++++++++++++++++++++++++++++++++++++++++++
>  3 files changed, 178 insertions(+)
>  create mode 100644 drivers/misc/rockchip-efuse.c

Reviewed-by: Simon Glass <sjg@chromium.org>

But please see below.

>
> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> index 1aae4bc..ed57414 100644
> --- a/drivers/misc/Kconfig
> +++ b/drivers/misc/Kconfig
> @@ -20,6 +20,19 @@ config ALTERA_SYSID
>           Select this to enable a sysid for Altera devices. Please find
>           details on the "Embedded Peripherals IP User Guide" of Altera.
>
> +config ROCKCHIP_EFUSE
> +        bool "Rockchip e-fuse support"
> +       depends on MISC
> +       help
> +         Enable (read-only) access for the e-fuse block found in Rockchip
> +         SoCs: accesses can either be made using byte addressing and a length
> +         or through child-nodes that are generated based on the e-fuse map
> +         retrieved from the DTS.
> +
> +         This driver currently supports the RK3399 only, but can easily be
> +         extended (by porting the read function from the Linux kernel sources)
> +         to support other recent Rockchip devices.
> +
>  config CMD_CROS_EC
>         bool "Enable crosec command"
>         depends on CROS_EC
> @@ -167,4 +180,5 @@ config I2C_EEPROM
>         depends on MISC
>         help
>           Enable a generic driver for EEPROMs attached via I2C.
> +
>  endmenu
> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> index e3151ea..77196fd 100644
> --- a/drivers/misc/Makefile
> +++ b/drivers/misc/Makefile
> @@ -51,3 +51,4 @@ obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
>  obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
>  obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
>  obj-$(CONFIG_QFW) += qfw.o
> +obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
> diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
> new file mode 100644
> index 0000000..6eb3616
> --- /dev/null
> +++ b/drivers/misc/rockchip-efuse.c
> @@ -0,0 +1,163 @@
> +/*
> + * eFuse driver for Rockchip devices
> + *
> + * Copyright 2017, Theobroma Systems Design und Consulting GmbH
> + * Written by Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> + *
> + * SPDX-License-Identifier:    GPL-2.0+
> + */
> +
> +#define DEBUG
> +
> +#include <common.h>
> +#include <asm/io.h>
> +#include <command.h>
> +#include <display_options.h>
> +#include <dm.h>
> +#include <linux/bitops.h>
> +#include <linux/delay.h>
> +#include <misc.h>
> +
> +#define RK3399_A_SHIFT          16
> +#define RK3399_A_MASK           0x3ff
> +#define RK3399_NFUSES           32
> +#define RK3399_BYTES_PER_FUSE   4
> +#define RK3399_STROBSFTSEL      BIT(9)
> +#define RK3399_RSB              BIT(7)
> +#define RK3399_PD               BIT(5)
> +#define RK3399_PGENB            BIT(3)
> +#define RK3399_LOAD             BIT(2)
> +#define RK3399_STROBE           BIT(1)
> +#define RK3399_CSB              BIT(0)
> +
> +struct rockchip_efuse_regs {
> +       u32 ctrl;      /* 0x00  efuse control register */
> +       u32 dout;      /* 0x04  efuse data out register */
> +       u32 rf;        /* 0x08  efuse redundancy bit used register */
> +       u32 _rsvd0;
> +       u32 jtag_pass; /* 0x10  JTAG password */
> +       u32 strobe_finish_ctrl;
> +                      /* 0x14  efuse strobe finish control register */
> +};
> +
> +struct rockchip_efuse_platdata {
> +       void __iomem *base;
> +       struct clk *clk;
> +};
> +
> +#if defined(DEBUG)
> +static int dump_efuses(cmd_tbl_t *cmdtp, int flag,
> +                      int argc, char * const argv[])
> +{
> +       /*
> +        * N.B.: This function is tailored towards the RK3399 and assumes that
> +        *       there's always 32 fuses x 32 bits (i.e. 128 bytes of data) to
> +        *       be read.
> +        */
> +
> +       struct udevice *dev;
> +       u8 fuses[128];
> +       int ret;
> +
> +       /* the first misc device will be used */
> +       ret = uclass_first_device_err(UCLASS_MISC, &dev);

This might pick up a different device. Can you use
uclass_get_device_by_driver() perhaps?

Regards,
Simon

[U-Boot] [PATCH v2 3/5] rockchip: board: puma_rk3399: add support for serial# and cpuid# via efuses

[Simon Glass]

On 28 April 2017 at 09:11, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> With our efuse driver for the RK3399 ready, we can add the
> board-specific code that consumes the cpuid from the efuse block and
> postprocesses it into the system serial (using the same CRC32 based
> derivation as in Linux).
>
> We expose the cpuid via two distinct environment variables:
>    serial# - the serial number, as derived in Linux
>    cpuid#  - the raw 16 byte CPU id field from the fuse block
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  board/theobroma-systems/puma_rk3399/puma-rk3399.c | 79 +++++++++++++++++++++++
>  include/configs/puma_rk3399.h                     |  4 ++
>  2 files changed, 83 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

Similar comment to the previous patch about finding the right device.

[U-Boot] [PATCH v2 4/5] rockchip: defconfig: puma-rk3399: enable RK3399 efuse driver

[Simon Glass]

On 28 April 2017 at 09:11, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> With everything in place (i.e. the new efuse driver, the clk-support
> for the non-secure efuse block, and the board-specific functions to
> derive 'serial#' from the cpu-id within the efuses), enable this in
> the RK3399-Q7 defconfig.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
>
> ---
>
> Changes in v2: None
>
>  configs/puma-rk3399_defconfig | 2 ++
>  1 file changed, 2 insertions(+)

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 5/5] rockchip: board: puma_rk3399: derive ethaddr from cpuid

[Simon Glass]

On 28 April 2017 at 09:11, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> From: Klaus Goger <klaus.goger@theobroma-systems.com>
>
> Generate a MAC address based on the cpuid available in the efuse
> block: Use the first 6 byte of the cpuid's SHA256 hash and set the
> locally administered bits. Also ensure that the multicast bit is
> cleared.
>
> The MAC address is only generated and set if there is no ethaddr
> present in the saved environment.
>
> Signed-off-by: Klaus Goger <klaus.goger@theobroma-systems.com>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>
> ---
>
> Changes in v2:
> - added derivation of ethaddr from cpuid
>
>  board/theobroma-systems/puma_rk3399/puma-rk3399.c | 38 +++++++++++++++++++++++
>  1 file changed, 38 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

[U-Boot] [PATCH v2 1/5] rockchip: clk: rk3399: allow requests for PCLK_EFUSE1024NS

[sjg at google.com]

On 28 April 2017 at 09:11, Philipp Tomsich
<philipp.tomsich@theobroma-systems.com> wrote:
> The (non-secure) efuse node in the DTS requests PCLK_EFUSE1024NS.
> To allow us to add a efuse-driver (and more importantly, to allow
> probes of such a driver to succeed), we need need to accept requests
> for PCLK_EFUSE1024NS and return a non-error result.
>
> As PCLK_EFUSE1024NS is enabled by default (i.e. after reset), we don't
> implement any logic to manage this clock gate and simply assume that
> the reset-default has not been changed.
>
> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
> ---
>
> Changes in v2: None
>
>  drivers/clk/rockchip/clk_rk3399.c | 4 ++++
>  1 file changed, 4 insertions(+)
>

Reviewed-by: Simon Glass <sjg@chromium.org>

Applied to u-boot-rockchip/next, thanks!

[U-Boot] [PATCH v2 2/5] rockchip: efuse: add (misc) driver for RK3399 non-secure efuse block

[Simon Glass]

Hi Philipp,

On 29 April 2017 at 21:48, Simon Glass <sjg@chromium.org> wrote:
>
> Hi Philipp,
>
> On 28 April 2017 at 09:11, Philipp Tomsich
> <philipp.tomsich@theobroma-systems.com> wrote:
> > This adds a simple driver for reading the efuse block of the RK3399.
> > It should be easy enough to add drivers for other devices (e.g. the
> > RK3328, RK3368, etc.) by passing the device details via driver_data.
> >
> > Unlike the kernel driver (using the nvmem subsystem), we don't expose
> > the efuse as multiple named cells, but rather as a linear memory that
> > can be read using misc_read(...).
> >
> > The primary use case (as of today) is the generation of a 'serial#'
> > (and a 'cpuid#') environment variable for the RK3399-Q7 (Puma)
> > system-on-module.
> >
> > Note that this adds a debug-only (i.e. only if DEBUG is defined)
> > command 'rk3399_dump_efuses' that dumps the efuse block's content.
> > N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to
> >       include a SoC-name (together with a comment in the function) to
> >       remind whoever adds support for additional SoCs that this
> >       function currently makes assumptions regarding the size of the
> >       fuse-box based on the RK3399. The hope is that the function is
> >       adjusted to reflect any changes resulting from generalising the
> >       driver for multiple SoCs and is then renamed.
> >
> > Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> > Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
> > ---
> >
> > Changes in v2: None
> >
> >  drivers/misc/Kconfig          |  14 ++++
> >  drivers/misc/Makefile         |   1 +
> >  drivers/misc/rockchip-efuse.c | 163 ++++++++++++++++++++++++++++++++++++++++++
> >  3 files changed, 178 insertions(+)
> >  create mode 100644 drivers/misc/rockchip-efuse.c
>
> Reviewed-by: Simon Glass <sjg@chromium.org>
>
> But please see below.
>
> >
> > diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
> > index 1aae4bc..ed57414 100644
> > --- a/drivers/misc/Kconfig
> > +++ b/drivers/misc/Kconfig
> > @@ -20,6 +20,19 @@ config ALTERA_SYSID
> >           Select this to enable a sysid for Altera devices. Please find
> >           details on the "Embedded Peripherals IP User Guide" of Altera.
> >
> > +config ROCKCHIP_EFUSE
> > +        bool "Rockchip e-fuse support"
> > +       depends on MISC
> > +       help
> > +         Enable (read-only) access for the e-fuse block found in Rockchip
> > +         SoCs: accesses can either be made using byte addressing and a length
> > +         or through child-nodes that are generated based on the e-fuse map
> > +         retrieved from the DTS.
> > +
> > +         This driver currently supports the RK3399 only, but can easily be
> > +         extended (by porting the read function from the Linux kernel sources)
> > +         to support other recent Rockchip devices.
> > +
> >  config CMD_CROS_EC
> >         bool "Enable crosec command"
> >         depends on CROS_EC
> > @@ -167,4 +180,5 @@ config I2C_EEPROM
> >         depends on MISC
> >         help
> >           Enable a generic driver for EEPROMs attached via I2C.
> > +
> >  endmenu
> > diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
> > index e3151ea..77196fd 100644
> > --- a/drivers/misc/Makefile
> > +++ b/drivers/misc/Makefile
> > @@ -51,3 +51,4 @@ obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
> >  obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
> >  obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
> >  obj-$(CONFIG_QFW) += qfw.o
> > +obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
> > diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
> > new file mode 100644
> > index 0000000..6eb3616
> > --- /dev/null
> > +++ b/drivers/misc/rockchip-efuse.c
> > @@ -0,0 +1,163 @@
> > +/*
> > + * eFuse driver for Rockchip devices
> > + *
> > + * Copyright 2017, Theobroma Systems Design und Consulting GmbH
> > + * Written by Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
> > + *
> > + * SPDX-License-Identifier:    GPL-2.0+
> > + */
> > +
> > +#define DEBUG
> > +
> > +#include <common.h>
> > +#include <asm/io.h>
> > +#include <command.h>
> > +#include <display_options.h>
> > +#include <dm.h>
> > +#include <linux/bitops.h>
> > +#include <linux/delay.h>
> > +#include <misc.h>
> > +
> > +#define RK3399_A_SHIFT          16
> > +#define RK3399_A_MASK           0x3ff
> > +#define RK3399_NFUSES           32
> > +#define RK3399_BYTES_PER_FUSE   4
> > +#define RK3399_STROBSFTSEL      BIT(9)
> > +#define RK3399_RSB              BIT(7)
> > +#define RK3399_PD               BIT(5)
> > +#define RK3399_PGENB            BIT(3)
> > +#define RK3399_LOAD             BIT(2)
> > +#define RK3399_STROBE           BIT(1)
> > +#define RK3399_CSB              BIT(0)
> > +
> > +struct rockchip_efuse_regs {
> > +       u32 ctrl;      /* 0x00  efuse control register */
> > +       u32 dout;      /* 0x04  efuse data out register */
> > +       u32 rf;        /* 0x08  efuse redundancy bit used register */
> > +       u32 _rsvd0;
> > +       u32 jtag_pass; /* 0x10  JTAG password */
> > +       u32 strobe_finish_ctrl;
> > +                      /* 0x14  efuse strobe finish control register */
> > +};
> > +
> > +struct rockchip_efuse_platdata {
> > +       void __iomem *base;
> > +       struct clk *clk;
> > +};
> > +
> > +#if defined(DEBUG)
> > +static int dump_efuses(cmd_tbl_t *cmdtp, int flag,
> > +                      int argc, char * const argv[])
> > +{
> > +       /*
> > +        * N.B.: This function is tailored towards the RK3399 and assumes that
> > +        *       there's always 32 fuses x 32 bits (i.e. 128 bytes of data) to
> > +        *       be read.
> > +        */
> > +
> > +       struct udevice *dev;
> > +       u8 fuses[128];
> > +       int ret;
> > +
> > +       /* the first misc device will be used */
> > +       ret = uclass_first_device_err(UCLASS_MISC, &dev);
>
> This might pick up a different device. Can you use
> uclass_get_device_by_driver() perhaps?

I've applied just the first patch in this series for now. Let me know
if you would rather keep the driver finding as you have it.

Regards,
Simon

[U-Boot] [PATCH v2 2/5] rockchip: efuse: add (misc) driver for RK3399 non-secure efuse block

[Dr. Philipp Tomsich]

> On 03 May 2017, at 12:06, Simon Glass <sjg@chromium.org> wrote:
> 
> Hi Philipp,
> 
> On 29 April 2017 at 21:48, Simon Glass <sjg at chromium.org <mailto:sjg@chromium.org>> wrote:
>> 
>> Hi Philipp,
>> 
>> On 28 April 2017 at 09:11, Philipp Tomsich
>> <philipp.tomsich@theobroma-systems.com> wrote:
>>> This adds a simple driver for reading the efuse block of the RK3399.
>>> It should be easy enough to add drivers for other devices (e.g. the
>>> RK3328, RK3368, etc.) by passing the device details via driver_data.
>>> 
>>> Unlike the kernel driver (using the nvmem subsystem), we don't expose
>>> the efuse as multiple named cells, but rather as a linear memory that
>>> can be read using misc_read(...).
>>> 
>>> The primary use case (as of today) is the generation of a 'serial#'
>>> (and a 'cpuid#') environment variable for the RK3399-Q7 (Puma)
>>> system-on-module.
>>> 
>>> Note that this adds a debug-only (i.e. only if DEBUG is defined)
>>> command 'rk3399_dump_efuses' that dumps the efuse block's content.
>>> N.B.: The name 'rk3399_dump_efuses' was intentionally chosen to
>>>      include a SoC-name (together with a comment in the function) to
>>>      remind whoever adds support for additional SoCs that this
>>>      function currently makes assumptions regarding the size of the
>>>      fuse-box based on the RK3399. The hope is that the function is
>>>      adjusted to reflect any changes resulting from generalising the
>>>      driver for multiple SoCs and is then renamed.
>>> 
>>> Signed-off-by: Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>> Tested-by: Klaus Goger <klaus.goger@theobroma-systems.com>
>>> ---
>>> 
>>> Changes in v2: None
>>> 
>>> drivers/misc/Kconfig          |  14 ++++
>>> drivers/misc/Makefile         |   1 +
>>> drivers/misc/rockchip-efuse.c | 163 ++++++++++++++++++++++++++++++++++++++++++
>>> 3 files changed, 178 insertions(+)
>>> create mode 100644 drivers/misc/rockchip-efuse.c
>> 
>> Reviewed-by: Simon Glass <sjg@chromium.org>
>> 
>> But please see below.
>> 
>>> 
>>> diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
>>> index 1aae4bc..ed57414 100644
>>> --- a/drivers/misc/Kconfig
>>> +++ b/drivers/misc/Kconfig
>>> @@ -20,6 +20,19 @@ config ALTERA_SYSID
>>>          Select this to enable a sysid for Altera devices. Please find
>>>          details on the "Embedded Peripherals IP User Guide" of Altera.
>>> 
>>> +config ROCKCHIP_EFUSE
>>> +        bool "Rockchip e-fuse support"
>>> +       depends on MISC
>>> +       help
>>> +         Enable (read-only) access for the e-fuse block found in Rockchip
>>> +         SoCs: accesses can either be made using byte addressing and a length
>>> +         or through child-nodes that are generated based on the e-fuse map
>>> +         retrieved from the DTS.
>>> +
>>> +         This driver currently supports the RK3399 only, but can easily be
>>> +         extended (by porting the read function from the Linux kernel sources)
>>> +         to support other recent Rockchip devices.
>>> +
>>> config CMD_CROS_EC
>>>        bool "Enable crosec command"
>>>        depends on CROS_EC
>>> @@ -167,4 +180,5 @@ config I2C_EEPROM
>>>        depends on MISC
>>>        help
>>>          Enable a generic driver for EEPROMs attached via I2C.
>>> +
>>> endmenu
>>> diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
>>> index e3151ea..77196fd 100644
>>> --- a/drivers/misc/Makefile
>>> +++ b/drivers/misc/Makefile
>>> @@ -51,3 +51,4 @@ obj-$(CONFIG_PCA9551_LED) += pca9551_led.o
>>> obj-$(CONFIG_FSL_DEVICE_DISABLE) += fsl_devdis.o
>>> obj-$(CONFIG_WINBOND_W83627) += winbond_w83627.o
>>> obj-$(CONFIG_QFW) += qfw.o
>>> +obj-$(CONFIG_ROCKCHIP_EFUSE) += rockchip-efuse.o
>>> diff --git a/drivers/misc/rockchip-efuse.c b/drivers/misc/rockchip-efuse.c
>>> new file mode 100644
>>> index 0000000..6eb3616
>>> --- /dev/null
>>> +++ b/drivers/misc/rockchip-efuse.c
>>> @@ -0,0 +1,163 @@
>>> +/*
>>> + * eFuse driver for Rockchip devices
>>> + *
>>> + * Copyright 2017, Theobroma Systems Design und Consulting GmbH
>>> + * Written by Philipp Tomsich <philipp.tomsich@theobroma-systems.com>
>>> + *
>>> + * SPDX-License-Identifier:    GPL-2.0+
>>> + */
>>> +
>>> +#define DEBUG
>>> +
>>> +#include <common.h>
>>> +#include <asm/io.h>
>>> +#include <command.h>
>>> +#include <display_options.h>
>>> +#include <dm.h>
>>> +#include <linux/bitops.h>
>>> +#include <linux/delay.h>
>>> +#include <misc.h>
>>> +
>>> +#define RK3399_A_SHIFT          16
>>> +#define RK3399_A_MASK           0x3ff
>>> +#define RK3399_NFUSES           32
>>> +#define RK3399_BYTES_PER_FUSE   4
>>> +#define RK3399_STROBSFTSEL      BIT(9)
>>> +#define RK3399_RSB              BIT(7)
>>> +#define RK3399_PD               BIT(5)
>>> +#define RK3399_PGENB            BIT(3)
>>> +#define RK3399_LOAD             BIT(2)
>>> +#define RK3399_STROBE           BIT(1)
>>> +#define RK3399_CSB              BIT(0)
>>> +
>>> +struct rockchip_efuse_regs {
>>> +       u32 ctrl;      /* 0x00  efuse control register */
>>> +       u32 dout;      /* 0x04  efuse data out register */
>>> +       u32 rf;        /* 0x08  efuse redundancy bit used register */
>>> +       u32 _rsvd0;
>>> +       u32 jtag_pass; /* 0x10  JTAG password */
>>> +       u32 strobe_finish_ctrl;
>>> +                      /* 0x14  efuse strobe finish control register */
>>> +};
>>> +
>>> +struct rockchip_efuse_platdata {
>>> +       void __iomem *base;
>>> +       struct clk *clk;
>>> +};
>>> +
>>> +#if defined(DEBUG)
>>> +static int dump_efuses(cmd_tbl_t *cmdtp, int flag,
>>> +                      int argc, char * const argv[])
>>> +{
>>> +       /*
>>> +        * N.B.: This function is tailored towards the RK3399 and assumes that
>>> +        *       there's always 32 fuses x 32 bits (i.e. 128 bytes of data) to
>>> +        *       be read.
>>> +        */
>>> +
>>> +       struct udevice *dev;
>>> +       u8 fuses[128];
>>> +       int ret;
>>> +
>>> +       /* the first misc device will be used */
>>> +       ret = uclass_first_device_err(UCLASS_MISC, &dev);
>> 
>> This might pick up a different device. Can you use
>> uclass_get_device_by_driver() perhaps?
> 
> I've applied just the first patch in this series for now. Let me know
> if you would rather keep the driver finding as you have it.

I was just about to resubmit the new series.
I’ll rebase to you next-branch and then submit what’s missing.