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In-reply-to: <20180730081124.30698-4-enric.balletbo@collabora.com> X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFrrBJsWRmVeSWpSXmKPExsWy7bCmuW5nRWK0waariha9504yWbzavIfN 4srX92wWa24fYrT4/+g1q8XcSbUWPzacYrbYfK6H1eJs0xt2i02Pr7FafOy5x2pxedccNovP vUcYLT49+M9scfGUq8XtxhVsFq17j7BbHPzwhNXi37WNLBZ3N5xltHj58QSLg6jHmnlrGD3e 32hl95jdcJHFY8fdJYwem1Z1snls//aA1eN+93Emj81L6j3+ztrP4tG3ZRWjx/Zr85g9Pm+S C+CJSrXJSE1MSS1SSM1Lzk/JzEu3VfIOjneONzUzMNQ1tLQwV1LIS8xNtVVy8QnQdcvMAXpW SaEsMacUKBSQWFyspG9nU5RfWpKqkJFfXGKrFG1oaKRnaGCuZ2QEpI1jrYxMgUoSUjOmXG5h LlhjVPH49FvGBsaX6l2MnBwSAiYSiz4sZu5i5OIQEtjBKLFk42Mo5zujxPcDN5lhqm59esQI kdjAKHGkpxsswSsgKPFj8j2WLkYODmYBeYkjl7JBwswCmhJbd69nh6i/yyjx/MxHRoh6LYm5 M94xgdgsAqoSx96dBZvDBhTf/+IGG4jNL6AocfXHY7B6UYEIiZ3zv4ENEhHoZ5b43NnMBOIw C9xnkrgy4TxYh7BAgsSkqz/BOjgFnCQ2T/0M9oOEwFt2iQXtj6F+cJF4tm0KG4QtLPHq+BZ2 CFta4tmqjYwQDe2MEl9eNLNCOBMYJT6c2swEUWUs8WxhFxPEd3wSHYf/soM8LSHAK9HRJgRR 4iGxccl/FhBbSOAso8SCFrcJjLKzkIJpFiKYZiEF0wJG5lWMYqkFxbnpqcVGBcZ6xYm5xaV5 6XrJ+bmbGMGpWst9B+O2cz6HGAU4GJV4eAsqE6KFWBPLiitzDzFKcDArifDayMRHC/GmJFZW pRblxxeV5qQWH2I0BYbyRGYp0eR8YB7JK4k3NDUyNja2MDW3NDawVBLnrfILjhYSSE8sSc1O TS1ILYLpY+LglGpgbJkQcrX9MTfz78BNR5YsnD1n89m+MyfXZf/+nR/XdjTkjvC9ko7VfpPK P5Wt2L/rzWP33tXWHULnfJcq7k6TiZxi90nm+K4ezR0fZyy/VVS4ccJnazk5o+S2e1avEv9Y eCx4q5S7V+WNHfMD9pUcFW8qg69vE+Z6OIHtYLW5qHPbvNT780U2rVdiKc5INNRiLipOBAC4 YZu56wMAAA== X-Brightmail-Tracker: H4sIAAAAAAAAA+NgFjrGIsWRmVeSWpSXmKPExsVy+t9jQd3OisRog+XruCx6z51ksni1eQ+b xZWv79ks1tw+xGjx/9FrVou5k2otfmw4xWyx+VwPq8XZpjfsFpseX2O1+Nhzj9Xi8q45bBaf e48wWnx68J/Z4uIpV4vbjSvYLFr3HmG3OPjhCavFv2sbWSzubjjLaPHy4wkWB1GPNfPWMHq8 v9HK7jG74SKLx467Sxg9Nq3qZPPY/u0Bq8f97uNMHpuX1Hv8nbWfxaNvyypGj+3X5jF7fN4k F8ATxWWTkpqTWZZapG+XwJUx5XILc8Eao4rHp98yNjC+VO9i5OSQEDCRuPXpEWMXIxeHkMA6 RolTF+6wgiR4BQQlfky+x9LFyMHBLCAvceRSNkiYWUBdYtK8RcwQ9fcZJZ7OfwdVryUxd8Y7 JhCbRUBV4ti7s8wgNhtQfP+LG2wgNr+AosTVH48ZQWaKCkRIdJ+oBJkjItDPLDHt2hmwI5gF 7jNJXHq3jhGkQVggQWLS1Z9Q151llGhb/AJsEqeAk8TmqZ+ZJzAKzEJy7CyEY2chOXYBI/Mq RsnUguLc9NxiowKjvNRyveLE3OLSvHS95PzcTYzA2N12WKt/B+PjJfGHGAU4GJV4eE9UJ0QL sSaWFVfmHmKU4GBWEuG1kYmPFuJNSaysSi3Kjy8qzUktPsQozcGiJM7Ln38sUkggPbEkNTs1 tSC1CCbLxMEp1cDoJfDSduah5czWDD9dbDTbJ1+cHx87my1mmyOXYqvn5eL8yWbhdwoy9Bo2 ft5/U3Fxat91w6PqFQYPqo2FPa/8mbrXuak89gbTuuvsk89Nb3Ly/JlnriWhvCP+xZModqZr C9NfLexPLUydtJrdL2jjDkGGVI2Qs79qv86NT+v+PvP15+3diu1KLMUZiYZazEXFiQCcATBS 2QIAAA== X-CMS-MailID: 20180801090825epcas2p13dc666cf68c6fcb9e1ae133e6417f262 X-Msg-Generator: CA CMS-TYPE: 102P DLP-Filter: Pass X-CFilter-Loop: Reflected X-CMS-RootMailID: 20180730081238epcas5p1ee07f1c70f33018509b34f60736f4832 References: <20180730081124.30698-1-enric.balletbo@collabora.com> <20180730081124.30698-4-enric.balletbo@collabora.com> Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Enric, On 2018년 07월 30일 17:11, Enric Balletbo i Serra wrote: > Trusted Firmware-A (TF-A) for rk3399 implements a SiP call to get the > on-die termination (ODT) and auto power down parameters from kernel, > this patch adds the functionality to do this. Also, if DDR clock > frequency is lower than the on-die termination (ODT) disable frequency > this driver should disable the DDR ODT. > > Signed-off-by: Enric Balletbo i Serra Looks good to me. Reviewed-by: Chanwoo Choi > --- > > Changes in v1: > - [RFC 3/10] Add an explanation for platform SIP calls. > - [RFC 3/10] Change if statement for a switch. > - [RFC 3/10] Rename ddr_flag to odt_enable to be more clear. > > drivers/devfreq/rk3399_dmc.c | 74 ++++++++++++++++++++++++++++- > include/soc/rockchip/rockchip_sip.h | 1 + > 2 files changed, 74 insertions(+), 1 deletion(-) > > diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c > index e795ad2b3f6b..c619dc4ac620 100644 > --- a/drivers/devfreq/rk3399_dmc.c > +++ b/drivers/devfreq/rk3399_dmc.c > @@ -18,14 +18,17 @@ > #include > #include > #include > +#include > #include > #include > #include > #include > +#include > #include > #include > #include > > +#include > #include > > struct dram_timing { > @@ -69,8 +72,11 @@ struct rk3399_dmcfreq { > struct mutex lock; > struct dram_timing timing; > struct regulator *vdd_center; > + struct regmap *regmap_pmu; > unsigned long rate, target_rate; > unsigned long volt, target_volt; > + unsigned int odt_dis_freq; > + int odt_pd_arg0, odt_pd_arg1; > }; > > static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, > @@ -80,6 +86,8 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, > struct dev_pm_opp *opp; > unsigned long old_clk_rate = dmcfreq->rate; > unsigned long target_volt, target_rate; > + struct arm_smccc_res res; > + bool odt_enable = false; > int err; > > opp = devfreq_recommended_opp(dev, freq, flags); > @@ -95,6 +103,19 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, > > mutex_lock(&dmcfreq->lock); > > + if (target_rate >= dmcfreq->odt_dis_freq) > + odt_enable = true; > + > + /* > + * This makes a SMC call to the TF-A to set the DDR PD (power-down) > + * timings and to enable or disable the ODT (on-die termination) > + * resistors. > + */ > + arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, > + dmcfreq->odt_pd_arg1, > + ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, > + odt_enable, 0, 0, 0, &res); > + > /* > * If frequency scaling from low to high, adjust voltage first. > * If frequency scaling from high to low, adjust frequency first. > @@ -294,11 +315,13 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) > { > struct arm_smccc_res res; > struct device *dev = &pdev->dev; > - struct device_node *np = pdev->dev.of_node; > + struct device_node *np = pdev->dev.of_node, *node; > struct rk3399_dmcfreq *data; > int ret, index, size; > uint32_t *timing; > struct dev_pm_opp *opp; > + u32 ddr_type; > + u32 val; > > data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL); > if (!data) > @@ -334,6 +357,34 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) > return ret; > } > > + /* Try to find the optional reference to the pmu syscon */ > + node = of_parse_phandle(np, "rockchip,pmu", 0); > + if (node) { > + data->regmap_pmu = syscon_node_to_regmap(node); > + if (IS_ERR(data->regmap_pmu)) > + return PTR_ERR(data->regmap_pmu); > + } > + > + /* Get DDR type */ > + regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); > + ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & > + RK3399_PMUGRF_DDRTYPE_MASK; > + > + /* Get the odt_dis_freq parameter in function of the DDR type */ > + switch (ddr_type) { > + case RK3399_PMUGRF_DDRTYPE_DDR3: > + data->odt_dis_freq = data->timing.ddr3_odt_dis_freq; > + break; > + case RK3399_PMUGRF_DDRTYPE_LPDDR3: > + data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq; > + break; > + case RK3399_PMUGRF_DDRTYPE_LPDDR4: > + data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq; > + break; > + default: > + return -EINVAL; > + }; > + > /* > * Get dram timing and pass it to arm trust firmware, > * the dram drvier in arm trust firmware will get these > @@ -358,6 +409,27 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) > ROCKCHIP_SIP_CONFIG_DRAM_INIT, > 0, 0, 0, 0, &res); > > + /* > + * In TF-A there is a platform SIP call to set the PD (power-down) > + * timings and to enable or disable the ODT (on-die termination). > + * This call needs three arguments as follows: > + * > + * arg0: > + * bit[0-7] : sr_idle > + * bit[8-15] : sr_mc_gate_idle > + * bit[16-31] : standby idle > + * arg1: > + * bit[0-11] : pd_idle > + * bit[16-27] : srpd_lite_idle > + * arg2: > + * bit[0] : odt enable > + */ > + data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) | > + ((data->timing.sr_mc_gate_idle & 0xff) << 8) | > + ((data->timing.standby_idle & 0xffff) << 16); > + data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) | > + ((data->timing.srpd_lite_idle & 0xfff) << 16); > + > /* > * We add a devfreq driver to our parent since it has a device tree node > * with operating points. > diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h > index 7e28092c4d3d..ad9482c56797 100644 > --- a/include/soc/rockchip/rockchip_sip.h > +++ b/include/soc/rockchip/rockchip_sip.h > @@ -23,5 +23,6 @@ > #define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05 > #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 > #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 > +#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08 > > #endif > -- Best Regards, Chanwoo Choi Samsung Electronics From mboxrd@z Thu Jan 1 00:00:00 1970 From: cw00.choi@samsung.com (Chanwoo Choi) Date: Wed, 01 Aug 2018 18:08:20 +0900 Subject: [PATCH 3/8] devfreq: rk3399_dmc: Pass ODT and auto power down parameters to TF-A. In-Reply-To: <20180730081124.30698-4-enric.balletbo@collabora.com> References: <20180730081124.30698-1-enric.balletbo@collabora.com> <20180730081124.30698-4-enric.balletbo@collabora.com> Message-ID: <5B617884.5070600@samsung.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Enric, On 2018? 07? 30? 17:11, Enric Balletbo i Serra wrote: > Trusted Firmware-A (TF-A) for rk3399 implements a SiP call to get the > on-die termination (ODT) and auto power down parameters from kernel, > this patch adds the functionality to do this. Also, if DDR clock > frequency is lower than the on-die termination (ODT) disable frequency > this driver should disable the DDR ODT. > > Signed-off-by: Enric Balletbo i Serra Looks good to me. Reviewed-by: Chanwoo Choi > --- > > Changes in v1: > - [RFC 3/10] Add an explanation for platform SIP calls. > - [RFC 3/10] Change if statement for a switch. > - [RFC 3/10] Rename ddr_flag to odt_enable to be more clear. > > drivers/devfreq/rk3399_dmc.c | 74 ++++++++++++++++++++++++++++- > include/soc/rockchip/rockchip_sip.h | 1 + > 2 files changed, 74 insertions(+), 1 deletion(-) > > diff --git a/drivers/devfreq/rk3399_dmc.c b/drivers/devfreq/rk3399_dmc.c > index e795ad2b3f6b..c619dc4ac620 100644 > --- a/drivers/devfreq/rk3399_dmc.c > +++ b/drivers/devfreq/rk3399_dmc.c > @@ -18,14 +18,17 @@ > #include > #include > #include > +#include > #include > #include > #include > #include > +#include > #include > #include > #include > > +#include > #include > > struct dram_timing { > @@ -69,8 +72,11 @@ struct rk3399_dmcfreq { > struct mutex lock; > struct dram_timing timing; > struct regulator *vdd_center; > + struct regmap *regmap_pmu; > unsigned long rate, target_rate; > unsigned long volt, target_volt; > + unsigned int odt_dis_freq; > + int odt_pd_arg0, odt_pd_arg1; > }; > > static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, > @@ -80,6 +86,8 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, > struct dev_pm_opp *opp; > unsigned long old_clk_rate = dmcfreq->rate; > unsigned long target_volt, target_rate; > + struct arm_smccc_res res; > + bool odt_enable = false; > int err; > > opp = devfreq_recommended_opp(dev, freq, flags); > @@ -95,6 +103,19 @@ static int rk3399_dmcfreq_target(struct device *dev, unsigned long *freq, > > mutex_lock(&dmcfreq->lock); > > + if (target_rate >= dmcfreq->odt_dis_freq) > + odt_enable = true; > + > + /* > + * This makes a SMC call to the TF-A to set the DDR PD (power-down) > + * timings and to enable or disable the ODT (on-die termination) > + * resistors. > + */ > + arm_smccc_smc(ROCKCHIP_SIP_DRAM_FREQ, dmcfreq->odt_pd_arg0, > + dmcfreq->odt_pd_arg1, > + ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD, > + odt_enable, 0, 0, 0, &res); > + > /* > * If frequency scaling from low to high, adjust voltage first. > * If frequency scaling from high to low, adjust frequency first. > @@ -294,11 +315,13 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) > { > struct arm_smccc_res res; > struct device *dev = &pdev->dev; > - struct device_node *np = pdev->dev.of_node; > + struct device_node *np = pdev->dev.of_node, *node; > struct rk3399_dmcfreq *data; > int ret, index, size; > uint32_t *timing; > struct dev_pm_opp *opp; > + u32 ddr_type; > + u32 val; > > data = devm_kzalloc(dev, sizeof(struct rk3399_dmcfreq), GFP_KERNEL); > if (!data) > @@ -334,6 +357,34 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) > return ret; > } > > + /* Try to find the optional reference to the pmu syscon */ > + node = of_parse_phandle(np, "rockchip,pmu", 0); > + if (node) { > + data->regmap_pmu = syscon_node_to_regmap(node); > + if (IS_ERR(data->regmap_pmu)) > + return PTR_ERR(data->regmap_pmu); > + } > + > + /* Get DDR type */ > + regmap_read(data->regmap_pmu, RK3399_PMUGRF_OS_REG2, &val); > + ddr_type = (val >> RK3399_PMUGRF_DDRTYPE_SHIFT) & > + RK3399_PMUGRF_DDRTYPE_MASK; > + > + /* Get the odt_dis_freq parameter in function of the DDR type */ > + switch (ddr_type) { > + case RK3399_PMUGRF_DDRTYPE_DDR3: > + data->odt_dis_freq = data->timing.ddr3_odt_dis_freq; > + break; > + case RK3399_PMUGRF_DDRTYPE_LPDDR3: > + data->odt_dis_freq = data->timing.lpddr3_odt_dis_freq; > + break; > + case RK3399_PMUGRF_DDRTYPE_LPDDR4: > + data->odt_dis_freq = data->timing.lpddr4_odt_dis_freq; > + break; > + default: > + return -EINVAL; > + }; > + > /* > * Get dram timing and pass it to arm trust firmware, > * the dram drvier in arm trust firmware will get these > @@ -358,6 +409,27 @@ static int rk3399_dmcfreq_probe(struct platform_device *pdev) > ROCKCHIP_SIP_CONFIG_DRAM_INIT, > 0, 0, 0, 0, &res); > > + /* > + * In TF-A there is a platform SIP call to set the PD (power-down) > + * timings and to enable or disable the ODT (on-die termination). > + * This call needs three arguments as follows: > + * > + * arg0: > + * bit[0-7] : sr_idle > + * bit[8-15] : sr_mc_gate_idle > + * bit[16-31] : standby idle > + * arg1: > + * bit[0-11] : pd_idle > + * bit[16-27] : srpd_lite_idle > + * arg2: > + * bit[0] : odt enable > + */ > + data->odt_pd_arg0 = (data->timing.sr_idle & 0xff) | > + ((data->timing.sr_mc_gate_idle & 0xff) << 8) | > + ((data->timing.standby_idle & 0xffff) << 16); > + data->odt_pd_arg1 = (data->timing.pd_idle & 0xfff) | > + ((data->timing.srpd_lite_idle & 0xfff) << 16); > + > /* > * We add a devfreq driver to our parent since it has a device tree node > * with operating points. > diff --git a/include/soc/rockchip/rockchip_sip.h b/include/soc/rockchip/rockchip_sip.h > index 7e28092c4d3d..ad9482c56797 100644 > --- a/include/soc/rockchip/rockchip_sip.h > +++ b/include/soc/rockchip/rockchip_sip.h > @@ -23,5 +23,6 @@ > #define ROCKCHIP_SIP_CONFIG_DRAM_GET_RATE 0x05 > #define ROCKCHIP_SIP_CONFIG_DRAM_CLR_IRQ 0x06 > #define ROCKCHIP_SIP_CONFIG_DRAM_SET_PARAM 0x07 > +#define ROCKCHIP_SIP_CONFIG_DRAM_SET_ODT_PD 0x08 > > #endif > -- Best Regards, Chanwoo Choi Samsung Electronics