From: "Jan Beulich" <JBeulich@suse.com>
To: Kevin Tian <kevin.tian@intel.com>
Cc: Wei Liu <wei.liu2@citrix.com>,
George Dunlap <George.Dunlap@eu.citrix.com>,
Andrew Cooper <andrew.cooper3@citrix.com>,
Paul Durrant <paul.durrant@citrix.com>,
Jun Nakajima <jun.nakajima@intel.com>,
xen-devel <xen-devel@lists.xenproject.org>
Subject: Re: [PATCH v2 4/4] x86/HVM: prefill cache with PDPTEs when possible
Date: Fri, 14 Sep 2018 02:12:04 -0600 [thread overview]
Message-ID: <5B9B6D5402000078001E885C@prv1-mh.provo.novell.com> (raw)
In-Reply-To: <AADFC41AFE54684AB9EE6CBC0274A5D19130315F@SHSMSX101.ccr.corp.intel.com>
>>> On 14.09.18 at 04:18, <kevin.tian@intel.com> wrote:
>> From: Jan Beulich [mailto:JBeulich@suse.com]
>> Sent: Thursday, September 13, 2018 4:55 PM
>>
>> >>> On 13.09.18 at 08:30, <kevin.tian@intel.com> wrote:
>> >> From: Jan Beulich [mailto:JBeulich@suse.com]
>> >> Sent: Tuesday, September 11, 2018 9:16 PM
>> >>
>> >> Since strictly speaking it is incorrect for guest_walk_tables() to read
>> >> L3 entries during PAE page walks, try to overcome this where possible by
>> >
>> > can you elaborate? why it's incorrect to read L3 entries?
>>
>> Architectural behavior: In PAE mode they get read upon CR3 loads,
>> not during page walks.
>
> ah yes. can you add "CR3 load" in description which reminds
> people easily?
Extended text:
Since strictly speaking it is incorrect for guest_walk_tables() to read
L3 entries during PAE page walks (they get loaded from memory only upon
CR3 loads and certain TLB flushes), try to overcome this where possible
by pre-loading the values from hardware into the cache. Sadly the
information is available in the EPT case only. On the positive side for
NPT the spec spells out that L3 entries are actually read on walks, so
us reading them is consistent with hardware behavior in that case.
>> >> pre-loading the values from hardware into the cache. Sadly the
>> >> information is available in the EPT case only. On the positive side for
>> >> NPT the spec spells out that L3 entries are actually read on walks, so
>> >> us reading them is consistent with hardware behavior in that case.
>> >
>> > I'm a little bit confused about the description here. you change
>> > VMX code but using NPT spec as the reference?
>>
>> I'm trying to explain why there not being a way to do the same on
>> NPT is not only not a problem, but in line with hardware behavior.
>>
>
> Reviewed-by: Kevin Tian <kevin.tian@intel.com>
Thanks.
Jan
_______________________________________________
Xen-devel mailing list
Xen-devel@lists.xenproject.org
https://lists.xenproject.org/mailman/listinfo/xen-devel
next prev parent reply other threads:[~2018-09-14 8:12 UTC|newest]
Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-09-11 13:10 [PATCH v2 0/4] x86/HVM: implement memory read caching Jan Beulich
2018-09-11 13:13 ` [PATCH v2 1/4] x86/mm: add optional cache to GLA->GFN translation Jan Beulich
2018-09-11 13:40 ` Razvan Cojocaru
2018-09-19 15:09 ` Wei Liu
2018-09-11 13:14 ` [PATCH v2 2/4] x86/mm: use optional cache in guest_walk_tables() Jan Beulich
2018-09-11 16:17 ` Paul Durrant
2018-09-12 8:30 ` Jan Beulich
2018-09-19 15:50 ` Wei Liu
2018-09-11 13:15 ` [PATCH v2 3/4] x86/HVM: implement memory read caching Jan Beulich
2018-09-11 16:20 ` Paul Durrant
2018-09-12 8:38 ` Jan Beulich
2018-09-12 8:49 ` Paul Durrant
2018-09-19 15:57 ` Wei Liu
2018-09-20 6:39 ` Jan Beulich
2018-09-20 15:42 ` Wei Liu
2018-09-11 13:16 ` [PATCH v2 4/4] x86/HVM: prefill cache with PDPTEs when possible Jan Beulich
2018-09-13 6:30 ` Tian, Kevin
2018-09-13 8:55 ` Jan Beulich
2018-09-14 2:18 ` Tian, Kevin
2018-09-14 8:12 ` Jan Beulich [this message]
2018-09-25 14:14 ` [PATCH v3 0/4] x86/HVM: implement memory read caching Jan Beulich
2018-09-25 14:23 ` [PATCH v3 1/4] x86/mm: add optional cache to GLA->GFN translation Jan Beulich
2018-09-25 14:24 ` [PATCH v3 2/4] x86/mm: use optional cache in guest_walk_tables() Jan Beulich
2018-09-25 14:25 ` [PATCH v3 3/4] x86/HVM: implement memory read caching Jan Beulich
2018-09-26 11:05 ` Wei Liu
2018-10-02 10:39 ` Ping: " Jan Beulich
2018-10-02 13:53 ` Boris Ostrovsky
2018-10-09 5:19 ` Tian, Kevin
2018-09-25 14:26 ` [PATCH v3 4/4] x86/HVM: prefill cache with PDPTEs when possible Jan Beulich
2018-09-25 14:38 ` Paul Durrant
2018-10-02 10:36 ` Ping: [PATCH v3 0/4] x86/HVM: implement memory read caching Jan Beulich
2018-10-02 10:51 ` Andrew Cooper
2018-10-02 12:47 ` Jan Beulich
2018-10-11 15:54 ` George Dunlap
2018-10-11 16:15 ` Jan Beulich
2018-10-11 16:33 ` George Dunlap
2018-10-12 6:32 ` Jan Beulich
2018-10-11 6:51 ` Jan Beulich
2018-10-11 17:36 ` George Dunlap
2018-10-12 13:55 ` [PATCH v2 " Andrew Cooper
2018-10-12 14:19 ` Jan Beulich
2018-10-18 15:20 ` George Dunlap
2019-05-07 16:22 ` George Dunlap
2019-05-07 16:22 ` [Xen-devel] " George Dunlap
2019-05-07 16:26 ` Jan Beulich
2019-05-07 16:26 ` [Xen-devel] " Jan Beulich
2018-11-09 10:17 ` Jan Beulich
2019-02-14 15:14 ` Jan Beulich
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=5B9B6D5402000078001E885C@prv1-mh.provo.novell.com \
--to=jbeulich@suse.com \
--cc=George.Dunlap@eu.citrix.com \
--cc=andrew.cooper3@citrix.com \
--cc=jun.nakajima@intel.com \
--cc=kevin.tian@intel.com \
--cc=paul.durrant@citrix.com \
--cc=wei.liu2@citrix.com \
--cc=xen-devel@lists.xenproject.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.