From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shameerali Kolothum Thodi Subject: RE: [PATCH v9 2/4] iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers Date: Tue, 7 Nov 2017 09:37:35 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA83845828E@FRAEML521-MBX.china.huawei.com> References: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> <20171006140450.89652-3-shameerali.kolothum.thodi@huawei.com> <20171013192350.GA32130@arm.com> <5FC3163CFD30C246ABAA99954A238FA83844672A@FRAEML521-MBX.china.huawei.com> <1d49243a-4746-f189-7c5d-4b98937115fb@arm.com> <5FC3163CFD30C246ABAA99954A238FA83844FE04@FRAEML521-MBX.china.huawei.com> <20171103113503.GB29434@red-moon> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: Received: from lhrrgout.huawei.com ([194.213.3.17]:39770 "EHLO lhrrgout.huawei.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755706AbdKGJiI (ORCPT ); Tue, 7 Nov 2017 04:38:08 -0500 In-Reply-To: <20171103113503.GB29434@red-moon> Content-Language: en-US Sender: linux-acpi-owner@vger.kernel.org List-Id: linux-acpi@vger.kernel.org To: Lorenzo Pieralisi Cc: Robin Murphy , Will Deacon , Gabriele Paoloni , "marc.zyngier@arm.com" , "linux-pci@vger.kernel.org" , "joro@8bytes.org" , John Garry , "Guohanjun (Hanjun Guo)" , Linuxarm , "linux-acpi@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "Wangzhou (B)" , "sudeep.holla@arm.com" , "bhelgaas@google.com" , "linux-arm-kernel@lists.infradead.org" , "devel@acpica.org" DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogTG9yZW56byBQaWVyYWxp c2kgW21haWx0bzpsb3JlbnpvLnBpZXJhbGlzaUBhcm0uY29tXQ0KPiBTZW50OiBGcmlkYXksIE5v dmVtYmVyIDAzLCAyMDE3IDExOjM1IEFNDQo+IFRvOiBTaGFtZWVyYWxpIEtvbG90aHVtIFRob2Rp IDxzaGFtZWVyYWxpLmtvbG90aHVtLnRob2RpQGh1YXdlaS5jb20+DQo+IENjOiBSb2JpbiBNdXJw aHkgPHJvYmluLm11cnBoeUBhcm0uY29tPjsgV2lsbCBEZWFjb24NCj4gPHdpbGwuZGVhY29uQGFy bS5jb20+OyBHYWJyaWVsZSBQYW9sb25pIDxnYWJyaWVsZS5wYW9sb25pQGh1YXdlaS5jb20+Ow0K PiBtYXJjLnp5bmdpZXJAYXJtLmNvbTsgbGludXgtcGNpQHZnZXIua2VybmVsLm9yZzsgam9yb0A4 Ynl0ZXMub3JnOyBKb2huDQo+IEdhcnJ5IDxqb2huLmdhcnJ5QGh1YXdlaS5jb20+OyBHdW9oYW5q dW4gKEhhbmp1biBHdW8pDQo+IDxndW9oYW5qdW5AaHVhd2VpLmNvbT47IExpbnV4YXJtIDxsaW51 eGFybUBodWF3ZWkuY29tPjsgbGludXgtDQo+IGFjcGlAdmdlci5rZXJuZWwub3JnOyBpb21tdUBs aXN0cy5saW51eC1mb3VuZGF0aW9uLm9yZzsgV2FuZ3pob3UgKEIpDQo+IDx3YW5nemhvdTFAaGlz aWxpY29uLmNvbT47IHN1ZGVlcC5ob2xsYUBhcm0uY29tOyBiaGVsZ2Fhc0Bnb29nbGUuY29tOw0K PiBsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmc7IGRldmVsQGFjcGljYS5vcmcN Cj4gU3ViamVjdDogUmU6IFtQQVRDSCB2OSAyLzRdIGlvbW11L2RtYTogQWRkIGEgaGVscGVyIGZ1 bmN0aW9uIHRvIHJlc2VydmUgSFcNCj4gTVNJIGFkZHJlc3MgcmVnaW9ucyBmb3IgSU9NTVUgZHJp dmVycw0KPiANCj4gT24gVGh1LCBPY3QgMjYsIDIwMTcgYXQgMTA6MTE6NThBTSArMDAwMCwgU2hh bWVlcmFsaSBLb2xvdGh1bSBUaG9kaSB3cm90ZToNCj4gDQpbLi5dDQoNCj4gPg0KPiA+IEFzIHdl IHN0aWxsIGRvbuKAmXQgaGF2ZSBhIGNsZWFyIHJlc29sdXRpb24gb24gaG93IHRvIGludm9rZSB0 aGUNCj4gPiBpb3J0X2lvbW11X21zaV9nZXRfcmVzdl9yZWdpb25zKCksIEkgaGF2ZSBnb25lIGJh Y2sgYW5kIGF0dGVtcHRlZCB0bw0KPiA+IG1vdmUgdGhlIHNtbXUgbW9kZWwgY2hlY2sgaW5zaWRl IHRoZSBpb3J0IGNvZGUuIFRoaXMgbWVhbnMgdGhlDQo+ID4gZnVuY3Rpb24gd2lsbCBzZWxlY3Rp dmVseSBhcHBseSBIVyBNU0kgcmVzZXJ2YXRpb24gYmFzZWQgb24gdGhlDQo+ID4gcGxhdGZvcm0g YW5kIGFsc28gdGhlIGZ1bmN0aW9uIGNhbiBiZSBpbnZva2VkIGZyb20gdGhlDQo+IGlvbW11X2Rt YV9nZXRfcmVzdl9yZWdpb25zKCkgZGlyZWN0bHkuDQo+ID4NCj4gPiBDb3VsZCB5b3UgcGxlYXNl IHRha2UgYSBsb29rIGF0IHRoZSBiZWxvdyBzbmlwcGV0IGFuZCBsZXQgbWUga25vdyB5b3VyDQo+ IGZlZWRiYWNrLg0KPiA+IEhvcGUgd2UgY2FuIG1ha2Ugc29tZSBwcm9ncmVzcyBvbiB0aGlzIHNl cmllcy4NCj4gPg0KPiA+IFRoYW5rcywNCj4gPiBTaGFtZWVyDQo+ID4NCj4gPiAtLT44LS0NCj4g PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9hY3BpL2FybTY0L2lvcnQuYyBiL2RyaXZlcnMvYWNwaS9h cm02NC9pb3J0LmMNCj4gPiBpbmRleCA4NzZjMGUxLi5hMjcyMzNkIDEwMDY0NA0KPiA+IC0tLSBh L2RyaXZlcnMvYWNwaS9hcm02NC9pb3J0LmMNCj4gPiArKysgYi9kcml2ZXJzL2FjcGkvYXJtNjQv aW9ydC5jDQo+ID4gQEAgLTYxOSw2ICs2MTksMzkgQEAgc3RhdGljIGludCBfX21heWJlX3VudXNl ZCBfX2dldF9wY2lfcmlkKHN0cnVjdA0KPiBwY2lfZGV2ICpwZGV2LCB1MTYgYWxpYXMsDQo+ID4g IAlyZXR1cm4gMDsNCj4gPiAgfQ0KPiA+DQo+ID4gK3N0YXRpYyBib29sIF9fbWF5YmVfdW51c2Vk IGlvcnRfaHdfbXNpX3Jlc3ZfZW5hYmxlKHN0cnVjdCBkZXZpY2UgKmRldiwNCj4gPiArCQkJCQlz dHJ1Y3QgYWNwaV9pb3J0X25vZGUgKm5vZGUpDQo+ID4gK3sNCj4gPiArCXN0cnVjdCBhY3BpX2lv cnRfbm9kZSAqaW9tbXUgPSBOVUxMOw0KPiA+ICsJaW50IGk7DQo+ID4gKw0KPiA+ICsJaWYgKGRl dl9pc19wY2koZGV2KSkgew0KPiA+ICsJCXUzMiByaWQ7DQo+ID4gKw0KPiA+ICsJCXBjaV9mb3Jf ZWFjaF9kbWFfYWxpYXModG9fcGNpX2RldihkZXYpLCBfX2dldF9wY2lfcmlkLCAmcmlkKTsNCj4g PiArCQlpb21tdSA9IGlvcnRfbm9kZV9tYXBfaWQobm9kZSwgcmlkLCBOVUxMLA0KPiBJT1JUX0lP TU1VX1RZUEUpOw0KPiA+ICsJfSBlbHNlIHsNCj4gPiArCQlmb3IgKGkgPSAwOyBpIDwgbm9kZS0+ bWFwcGluZ19jb3VudDsgaSsrKSB7DQo+ID4gKwkJCWlvbW11ID0gaW9ydF9ub2RlX21hcF9wbGF0 Zm9ybV9pZChub2RlLCBOVUxMLA0KPiA+ICsJCQkJCQkJSU9SVF9JT01NVV9UWVBFLA0KPiBpKTsN Cj4gPiArCQkJaWYgKGlvbW11KQ0KPiA+ICsJCQkJYnJlYWs7DQo+ID4gKwkJfQ0KPiA+ICsJfQ0K PiANCj4gWW91IGRvIG5vdCBuZWVkIChhbmQgSSBkbyBub3Qgd2FudCB0aGlzIGNvZGUpIHRvIGRv IHRoZSBtYXBwaW5nIGFnYWluLg0KPiANCj4gWW91IGhhdmUgdGhlIGZ3bm9kZSAoaWUgZGV2LT5p b21tdV9md3NwZWMpIGNvcnJlc3BvbmRpbmcgdG8gdGhlIElPTU1VLA0KPiB5b3UgY2FuIHJldHJp ZXZlIHRoZSBTTU1VIElPUlQgbm9kZSBieSBhIHNpbXBsZSBsb29rLXVwIGFuZCBjYXJyeSBvdXQg dGhlDQo+IGNoZWNrIGJlbG93Lg0KDQpPay4gVW5kZXJzdG9vZC4gSSB3aWxsIHJld29yayB0aGlz IHBhcnQgdGhlbi4NCg0KPiBJdCB3b3VsZCBiZSBzaW1wbGVyIHRvIHNldCBhbiBvcHRpb24gaW4g dGhlIFNNTVV2MyBkcml2ZXIgYnV0IHRoZW4geW91IGdvIGJhY2sNCj4gdG8gc3F1YXJlIG9uZSB3 aXRoIERUL0FDUEkgU01NVXYzIGRyaXZlciBhd2FyZW5lc3Mgc28sIGlmLCB3aXRoIHRoZSBjaGFu Z2UNCj4gYWJvdmUgdGhpcyBjYW4gbWFrZSB0aGUgZ2VuZXJpYyBhcHByb2FjaCB3b3JrIChpZSBS b2JpbiBpcyBoYXBweSB3aXRoIGl0KSBJIGFtDQo+IGZpbmUgd2l0aCB0aGlzIElPUlQgdXBkYXRl IGFzIHdlbGwuDQoNClRoYW5rcyBMb3JlbnpvLiBJIHdpbGwgcmViYXNlIG9uIHRvcCBvZiByYzEg YW5kIHByZXBhcmUgdjEwIHdpdGggdGhlc2UgY2hhbmdlcw0KYW5kIHNlbnQgaXQgb3V0Lg0KDQpT aGFtZWVyIA0KDQo+ID4gKw0KPiA+ICsJaWYgKGlvbW11ICYmIChpb21tdS0+dHlwZSA9PSBBQ1BJ X0lPUlRfTk9ERV9TTU1VX1YzKSkgew0KPiA+ICsJCXN0cnVjdCBhY3BpX2lvcnRfc21tdV92MyAq c21tdTsNCj4gPiArDQo+ID4gKwkJc21tdSA9IChzdHJ1Y3QgYWNwaV9pb3J0X3NtbXVfdjMgKilp b21tdS0+bm9kZV9kYXRhOw0KPiA+ICsJCWlmIChzbW11LT5tb2RlbCA9PQ0KPiBBQ1BJX0lPUlRf U01NVV9WM19ISVNJTElDT05fSEkxNjFYKSB7DQo+ID4gKwkJCWRldl9ub3RpY2UoZGV2LCAiRW5h YmxpbmcgSGlTaWxpY29uIGVycmF0dW0NCj4gMTYxMDEwODAxXG4iKTsNCj4gPiArCQkJcmV0dXJu IHRydWU7DQo+ID4gKwkJfQ0KPiA+ICsJfQ0KPiA+ICsNCj4gPiArCXJldHVybiBmYWxzZTsNCj4g PiArfQ0KPiA+ICsNCj4gPiAgc3RhdGljIGludCBhcm1fc21tdV9pb3J0X3hsYXRlKHN0cnVjdCBk ZXZpY2UgKmRldiwgdTMyIHN0cmVhbWlkLA0KPiA+ICAJCQkgICAgICAgc3RydWN0IGZ3bm9kZV9o YW5kbGUgKmZ3bm9kZSwNCj4gPiAgCQkJICAgICAgIGNvbnN0IHN0cnVjdCBpb21tdV9vcHMgKm9w cykgQEAgLTY4Miw2ICs3MTUsOQ0KPiBAQCBpbnQNCj4gPiBpb3J0X2lvbW11X21zaV9nZXRfcmVz dl9yZWdpb25zKHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IGxpc3RfaGVhZA0KPiAqaGVhZCkN Cj4gPiAgCWlmICghbm9kZSkNCj4gPiAgCQlyZXR1cm4gLUVOT0RFVjsNCj4gPg0KPiA+ICsJaWYg KCFpb3J0X2h3X21zaV9yZXN2X2VuYWJsZShkZXYsIG5vZGUpKQ0KPiA+ICsJCXJldHVybiAwOw0K PiA+ICsNCj4gPiAgCS8qDQo+ID4gIAkgKiBDdXJyZW50IGxvZ2ljIHRvIHJlc2VydmUgSVRTIHJl Z2lvbnMgcmVsaWVzIG9uIEhXIHRvcG9sb2dpZXMNCj4gPiAgCSAqIHdoZXJlIGEgZ2l2ZW4gUENJ IG9yIG5hbWVkIGNvbXBvbmVudCBtYXBzIGl0cyBJRHMgdG8gb25seSBvbmUNCj4gPiBkaWZmIC0t Z2l0IGEvZHJpdmVycy9pb21tdS9kbWEtaW9tbXUuYyBiL2RyaXZlcnMvaW9tbXUvZG1hLWlvbW11 LmMNCj4gPiBpbmRleCA5ZDFjZWJlLi42N2M2ZTMwIDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMv aW9tbXUvZG1hLWlvbW11LmMNCj4gPiArKysgYi9kcml2ZXJzL2lvbW11L2RtYS1pb21tdS5jDQo+ ID4gQEAgLTE5LDYgKzE5LDcgQEANCj4gPiAgICogYWxvbmcgd2l0aCB0aGlzIHByb2dyYW0uICBJ ZiBub3QsIHNlZSA8aHR0cDovL3d3dy5nbnUub3JnL2xpY2Vuc2VzLz4uDQo+ID4gICAqLw0KPiA+ DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9hY3BpX2lvcnQuaD4NCj4gPiAgI2luY2x1ZGUgPGxpbnV4 L2RldmljZS5oPg0KPiA+ICAjaW5jbHVkZSA8bGludXgvZG1hLWlvbW11Lmg+DQo+ID4gICNpbmNs dWRlIDxsaW51eC9nZnAuaD4NCj4gPiBAQCAtMTc0LDYgKzE3NSwxMCBAQCB2b2lkIGlvbW11X2Rt YV9nZXRfcmVzdl9yZWdpb25zKHN0cnVjdCBkZXZpY2UNCj4gKmRldiwgc3RydWN0IGxpc3RfaGVh ZCAqbGlzdCkNCj4gPiAgCXN0cnVjdCBwY2lfaG9zdF9icmlkZ2UgKmJyaWRnZTsNCj4gPiAgCXN0 cnVjdCByZXNvdXJjZV9lbnRyeSAqd2luZG93Ow0KPiA+DQo+ID4gKwlpZiAoIWlzX29mX25vZGUo ZGV2LT5pb21tdV9md3NwZWMtPmlvbW11X2Z3bm9kZSkgJiYNCj4gPiArCQlpb3J0X2lvbW11X21z aV9nZXRfcmVzdl9yZWdpb25zKGRldiwgbGlzdCkgPCAwKQ0KPiA+ICsJCXJldHVybjsNCj4gPiAr DQo+ID4gIAlpZiAoIWRldl9pc19wY2koZGV2KSkNCj4gPiAgCQlyZXR1cm47DQo+ID4NCj4gPiBk aWZmIC0tZ2l0IGEvaW5jbHVkZS9saW51eC9hY3BpX2lvcnQuaCBiL2luY2x1ZGUvbGludXgvYWNw aV9pb3J0LmgNCj4gPiBpbmRleCAxODJhNTc3Li44OGYxN2M5IDEwMDY0NA0KPiA+IC0tLSBhL2lu Y2x1ZGUvbGludXgvYWNwaV9pb3J0LmgNCj4gPiArKysgYi9pbmNsdWRlL2xpbnV4L2FjcGlfaW9y dC5oDQo+ID4gQEAgLTU2LDcgKzU2LDcgQEAgY29uc3Qgc3RydWN0IGlvbW11X29wcyAqaW9ydF9p b21tdV9jb25maWd1cmUoc3RydWN0DQo+ID4gZGV2aWNlICpkZXYpICB7IHJldHVybiBOVUxMOyB9 ICBzdGF0aWMgaW5saW5lICBpbnQNCj4gPiBpb3J0X2lvbW11X21zaV9nZXRfcmVzdl9yZWdpb25z KHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IGxpc3RfaGVhZA0KPiA+ICpoZWFkKSAteyByZXR1 cm4gLUVOT0RFVjsgfQ0KPiA+ICt7IHJldHVybiAwOyB9DQo+ID4gICNlbmRpZg0KPiA+DQo+ID4g ICNlbmRpZiAvKiBfX0FDUElfSU9SVF9IX18gKi8NCj4gPg0KPiA+IC0tPjgtLQ0KPiA+DQo+ID4N Cj4gPg0K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Return-Path: From: Shameerali Kolothum Thodi To: Lorenzo Pieralisi Subject: RE: [PATCH v9 2/4] iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers Date: Tue, 7 Nov 2017 09:37:35 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA83845828E@FRAEML521-MBX.china.huawei.com> References: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> <20171006140450.89652-3-shameerali.kolothum.thodi@huawei.com> <20171013192350.GA32130@arm.com> <5FC3163CFD30C246ABAA99954A238FA83844672A@FRAEML521-MBX.china.huawei.com> <1d49243a-4746-f189-7c5d-4b98937115fb@arm.com> <5FC3163CFD30C246ABAA99954A238FA83844FE04@FRAEML521-MBX.china.huawei.com> <20171103113503.GB29434@red-moon> In-Reply-To: <20171103113503.GB29434@red-moon> MIME-Version: 1.0 List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "sudeep.holla@arm.com" , Gabriele Paoloni , "marc.zyngier@arm.com" , "linux-pci@vger.kernel.org" , "joro@8bytes.org" , John Garry , Will Deacon , Linuxarm , "linux-acpi@vger.kernel.org" , "iommu@lists.linux-foundation.org" , "Wangzhou \(B\)" , "Guohanjun \(Hanjun Guo\)" , "bhelgaas@google.com" , Robin Murphy , "linux-arm-kernel@lists.infradead.org" , "devel@acpica.org" Content-Type: text/plain; charset="utf-8" Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+bjorn=helgaas.com@lists.infradead.org List-ID: DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogTG9yZW56byBQaWVyYWxp c2kgW21haWx0bzpsb3JlbnpvLnBpZXJhbGlzaUBhcm0uY29tXQ0KPiBTZW50OiBGcmlkYXksIE5v dmVtYmVyIDAzLCAyMDE3IDExOjM1IEFNDQo+IFRvOiBTaGFtZWVyYWxpIEtvbG90aHVtIFRob2Rp IDxzaGFtZWVyYWxpLmtvbG90aHVtLnRob2RpQGh1YXdlaS5jb20+DQo+IENjOiBSb2JpbiBNdXJw aHkgPHJvYmluLm11cnBoeUBhcm0uY29tPjsgV2lsbCBEZWFjb24NCj4gPHdpbGwuZGVhY29uQGFy bS5jb20+OyBHYWJyaWVsZSBQYW9sb25pIDxnYWJyaWVsZS5wYW9sb25pQGh1YXdlaS5jb20+Ow0K PiBtYXJjLnp5bmdpZXJAYXJtLmNvbTsgbGludXgtcGNpQHZnZXIua2VybmVsLm9yZzsgam9yb0A4 Ynl0ZXMub3JnOyBKb2huDQo+IEdhcnJ5IDxqb2huLmdhcnJ5QGh1YXdlaS5jb20+OyBHdW9oYW5q dW4gKEhhbmp1biBHdW8pDQo+IDxndW9oYW5qdW5AaHVhd2VpLmNvbT47IExpbnV4YXJtIDxsaW51 eGFybUBodWF3ZWkuY29tPjsgbGludXgtDQo+IGFjcGlAdmdlci5rZXJuZWwub3JnOyBpb21tdUBs aXN0cy5saW51eC1mb3VuZGF0aW9uLm9yZzsgV2FuZ3pob3UgKEIpDQo+IDx3YW5nemhvdTFAaGlz aWxpY29uLmNvbT47IHN1ZGVlcC5ob2xsYUBhcm0uY29tOyBiaGVsZ2Fhc0Bnb29nbGUuY29tOw0K PiBsaW51eC1hcm0ta2VybmVsQGxpc3RzLmluZnJhZGVhZC5vcmc7IGRldmVsQGFjcGljYS5vcmcN Cj4gU3ViamVjdDogUmU6IFtQQVRDSCB2OSAyLzRdIGlvbW11L2RtYTogQWRkIGEgaGVscGVyIGZ1 bmN0aW9uIHRvIHJlc2VydmUgSFcNCj4gTVNJIGFkZHJlc3MgcmVnaW9ucyBmb3IgSU9NTVUgZHJp dmVycw0KPiANCj4gT24gVGh1LCBPY3QgMjYsIDIwMTcgYXQgMTA6MTE6NThBTSArMDAwMCwgU2hh bWVlcmFsaSBLb2xvdGh1bSBUaG9kaSB3cm90ZToNCj4gDQpbLi5dDQoNCj4gPg0KPiA+IEFzIHdl IHN0aWxsIGRvbuKAmXQgaGF2ZSBhIGNsZWFyIHJlc29sdXRpb24gb24gaG93IHRvIGludm9rZSB0 aGUNCj4gPiBpb3J0X2lvbW11X21zaV9nZXRfcmVzdl9yZWdpb25zKCksIEkgaGF2ZSBnb25lIGJh Y2sgYW5kIGF0dGVtcHRlZCB0bw0KPiA+IG1vdmUgdGhlIHNtbXUgbW9kZWwgY2hlY2sgaW5zaWRl IHRoZSBpb3J0IGNvZGUuIFRoaXMgbWVhbnMgdGhlDQo+ID4gZnVuY3Rpb24gd2lsbCBzZWxlY3Rp dmVseSBhcHBseSBIVyBNU0kgcmVzZXJ2YXRpb24gYmFzZWQgb24gdGhlDQo+ID4gcGxhdGZvcm0g YW5kIGFsc28gdGhlIGZ1bmN0aW9uIGNhbiBiZSBpbnZva2VkIGZyb20gdGhlDQo+IGlvbW11X2Rt YV9nZXRfcmVzdl9yZWdpb25zKCkgZGlyZWN0bHkuDQo+ID4NCj4gPiBDb3VsZCB5b3UgcGxlYXNl IHRha2UgYSBsb29rIGF0IHRoZSBiZWxvdyBzbmlwcGV0IGFuZCBsZXQgbWUga25vdyB5b3VyDQo+ IGZlZWRiYWNrLg0KPiA+IEhvcGUgd2UgY2FuIG1ha2Ugc29tZSBwcm9ncmVzcyBvbiB0aGlzIHNl cmllcy4NCj4gPg0KPiA+IFRoYW5rcywNCj4gPiBTaGFtZWVyDQo+ID4NCj4gPiAtLT44LS0NCj4g PiBkaWZmIC0tZ2l0IGEvZHJpdmVycy9hY3BpL2FybTY0L2lvcnQuYyBiL2RyaXZlcnMvYWNwaS9h cm02NC9pb3J0LmMNCj4gPiBpbmRleCA4NzZjMGUxLi5hMjcyMzNkIDEwMDY0NA0KPiA+IC0tLSBh L2RyaXZlcnMvYWNwaS9hcm02NC9pb3J0LmMNCj4gPiArKysgYi9kcml2ZXJzL2FjcGkvYXJtNjQv aW9ydC5jDQo+ID4gQEAgLTYxOSw2ICs2MTksMzkgQEAgc3RhdGljIGludCBfX21heWJlX3VudXNl ZCBfX2dldF9wY2lfcmlkKHN0cnVjdA0KPiBwY2lfZGV2ICpwZGV2LCB1MTYgYWxpYXMsDQo+ID4g IAlyZXR1cm4gMDsNCj4gPiAgfQ0KPiA+DQo+ID4gK3N0YXRpYyBib29sIF9fbWF5YmVfdW51c2Vk IGlvcnRfaHdfbXNpX3Jlc3ZfZW5hYmxlKHN0cnVjdCBkZXZpY2UgKmRldiwNCj4gPiArCQkJCQlz dHJ1Y3QgYWNwaV9pb3J0X25vZGUgKm5vZGUpDQo+ID4gK3sNCj4gPiArCXN0cnVjdCBhY3BpX2lv cnRfbm9kZSAqaW9tbXUgPSBOVUxMOw0KPiA+ICsJaW50IGk7DQo+ID4gKw0KPiA+ICsJaWYgKGRl dl9pc19wY2koZGV2KSkgew0KPiA+ICsJCXUzMiByaWQ7DQo+ID4gKw0KPiA+ICsJCXBjaV9mb3Jf ZWFjaF9kbWFfYWxpYXModG9fcGNpX2RldihkZXYpLCBfX2dldF9wY2lfcmlkLCAmcmlkKTsNCj4g PiArCQlpb21tdSA9IGlvcnRfbm9kZV9tYXBfaWQobm9kZSwgcmlkLCBOVUxMLA0KPiBJT1JUX0lP TU1VX1RZUEUpOw0KPiA+ICsJfSBlbHNlIHsNCj4gPiArCQlmb3IgKGkgPSAwOyBpIDwgbm9kZS0+ bWFwcGluZ19jb3VudDsgaSsrKSB7DQo+ID4gKwkJCWlvbW11ID0gaW9ydF9ub2RlX21hcF9wbGF0 Zm9ybV9pZChub2RlLCBOVUxMLA0KPiA+ICsJCQkJCQkJSU9SVF9JT01NVV9UWVBFLA0KPiBpKTsN Cj4gPiArCQkJaWYgKGlvbW11KQ0KPiA+ICsJCQkJYnJlYWs7DQo+ID4gKwkJfQ0KPiA+ICsJfQ0K PiANCj4gWW91IGRvIG5vdCBuZWVkIChhbmQgSSBkbyBub3Qgd2FudCB0aGlzIGNvZGUpIHRvIGRv IHRoZSBtYXBwaW5nIGFnYWluLg0KPiANCj4gWW91IGhhdmUgdGhlIGZ3bm9kZSAoaWUgZGV2LT5p b21tdV9md3NwZWMpIGNvcnJlc3BvbmRpbmcgdG8gdGhlIElPTU1VLA0KPiB5b3UgY2FuIHJldHJp ZXZlIHRoZSBTTU1VIElPUlQgbm9kZSBieSBhIHNpbXBsZSBsb29rLXVwIGFuZCBjYXJyeSBvdXQg dGhlDQo+IGNoZWNrIGJlbG93Lg0KDQpPay4gVW5kZXJzdG9vZC4gSSB3aWxsIHJld29yayB0aGlz IHBhcnQgdGhlbi4NCg0KPiBJdCB3b3VsZCBiZSBzaW1wbGVyIHRvIHNldCBhbiBvcHRpb24gaW4g dGhlIFNNTVV2MyBkcml2ZXIgYnV0IHRoZW4geW91IGdvIGJhY2sNCj4gdG8gc3F1YXJlIG9uZSB3 aXRoIERUL0FDUEkgU01NVXYzIGRyaXZlciBhd2FyZW5lc3Mgc28sIGlmLCB3aXRoIHRoZSBjaGFu Z2UNCj4gYWJvdmUgdGhpcyBjYW4gbWFrZSB0aGUgZ2VuZXJpYyBhcHByb2FjaCB3b3JrIChpZSBS b2JpbiBpcyBoYXBweSB3aXRoIGl0KSBJIGFtDQo+IGZpbmUgd2l0aCB0aGlzIElPUlQgdXBkYXRl IGFzIHdlbGwuDQoNClRoYW5rcyBMb3JlbnpvLiBJIHdpbGwgcmViYXNlIG9uIHRvcCBvZiByYzEg YW5kIHByZXBhcmUgdjEwIHdpdGggdGhlc2UgY2hhbmdlcw0KYW5kIHNlbnQgaXQgb3V0Lg0KDQpT aGFtZWVyIA0KDQo+ID4gKw0KPiA+ICsJaWYgKGlvbW11ICYmIChpb21tdS0+dHlwZSA9PSBBQ1BJ X0lPUlRfTk9ERV9TTU1VX1YzKSkgew0KPiA+ICsJCXN0cnVjdCBhY3BpX2lvcnRfc21tdV92MyAq c21tdTsNCj4gPiArDQo+ID4gKwkJc21tdSA9IChzdHJ1Y3QgYWNwaV9pb3J0X3NtbXVfdjMgKilp b21tdS0+bm9kZV9kYXRhOw0KPiA+ICsJCWlmIChzbW11LT5tb2RlbCA9PQ0KPiBBQ1BJX0lPUlRf U01NVV9WM19ISVNJTElDT05fSEkxNjFYKSB7DQo+ID4gKwkJCWRldl9ub3RpY2UoZGV2LCAiRW5h YmxpbmcgSGlTaWxpY29uIGVycmF0dW0NCj4gMTYxMDEwODAxXG4iKTsNCj4gPiArCQkJcmV0dXJu IHRydWU7DQo+ID4gKwkJfQ0KPiA+ICsJfQ0KPiA+ICsNCj4gPiArCXJldHVybiBmYWxzZTsNCj4g PiArfQ0KPiA+ICsNCj4gPiAgc3RhdGljIGludCBhcm1fc21tdV9pb3J0X3hsYXRlKHN0cnVjdCBk ZXZpY2UgKmRldiwgdTMyIHN0cmVhbWlkLA0KPiA+ICAJCQkgICAgICAgc3RydWN0IGZ3bm9kZV9o YW5kbGUgKmZ3bm9kZSwNCj4gPiAgCQkJICAgICAgIGNvbnN0IHN0cnVjdCBpb21tdV9vcHMgKm9w cykgQEAgLTY4Miw2ICs3MTUsOQ0KPiBAQCBpbnQNCj4gPiBpb3J0X2lvbW11X21zaV9nZXRfcmVz dl9yZWdpb25zKHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IGxpc3RfaGVhZA0KPiAqaGVhZCkN Cj4gPiAgCWlmICghbm9kZSkNCj4gPiAgCQlyZXR1cm4gLUVOT0RFVjsNCj4gPg0KPiA+ICsJaWYg KCFpb3J0X2h3X21zaV9yZXN2X2VuYWJsZShkZXYsIG5vZGUpKQ0KPiA+ICsJCXJldHVybiAwOw0K PiA+ICsNCj4gPiAgCS8qDQo+ID4gIAkgKiBDdXJyZW50IGxvZ2ljIHRvIHJlc2VydmUgSVRTIHJl Z2lvbnMgcmVsaWVzIG9uIEhXIHRvcG9sb2dpZXMNCj4gPiAgCSAqIHdoZXJlIGEgZ2l2ZW4gUENJ IG9yIG5hbWVkIGNvbXBvbmVudCBtYXBzIGl0cyBJRHMgdG8gb25seSBvbmUNCj4gPiBkaWZmIC0t Z2l0IGEvZHJpdmVycy9pb21tdS9kbWEtaW9tbXUuYyBiL2RyaXZlcnMvaW9tbXUvZG1hLWlvbW11 LmMNCj4gPiBpbmRleCA5ZDFjZWJlLi42N2M2ZTMwIDEwMDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMv aW9tbXUvZG1hLWlvbW11LmMNCj4gPiArKysgYi9kcml2ZXJzL2lvbW11L2RtYS1pb21tdS5jDQo+ ID4gQEAgLTE5LDYgKzE5LDcgQEANCj4gPiAgICogYWxvbmcgd2l0aCB0aGlzIHByb2dyYW0uICBJ ZiBub3QsIHNlZSA8aHR0cDovL3d3dy5nbnUub3JnL2xpY2Vuc2VzLz4uDQo+ID4gICAqLw0KPiA+ DQo+ID4gKyNpbmNsdWRlIDxsaW51eC9hY3BpX2lvcnQuaD4NCj4gPiAgI2luY2x1ZGUgPGxpbnV4 L2RldmljZS5oPg0KPiA+ICAjaW5jbHVkZSA8bGludXgvZG1hLWlvbW11Lmg+DQo+ID4gICNpbmNs dWRlIDxsaW51eC9nZnAuaD4NCj4gPiBAQCAtMTc0LDYgKzE3NSwxMCBAQCB2b2lkIGlvbW11X2Rt YV9nZXRfcmVzdl9yZWdpb25zKHN0cnVjdCBkZXZpY2UNCj4gKmRldiwgc3RydWN0IGxpc3RfaGVh ZCAqbGlzdCkNCj4gPiAgCXN0cnVjdCBwY2lfaG9zdF9icmlkZ2UgKmJyaWRnZTsNCj4gPiAgCXN0 cnVjdCByZXNvdXJjZV9lbnRyeSAqd2luZG93Ow0KPiA+DQo+ID4gKwlpZiAoIWlzX29mX25vZGUo ZGV2LT5pb21tdV9md3NwZWMtPmlvbW11X2Z3bm9kZSkgJiYNCj4gPiArCQlpb3J0X2lvbW11X21z aV9nZXRfcmVzdl9yZWdpb25zKGRldiwgbGlzdCkgPCAwKQ0KPiA+ICsJCXJldHVybjsNCj4gPiAr DQo+ID4gIAlpZiAoIWRldl9pc19wY2koZGV2KSkNCj4gPiAgCQlyZXR1cm47DQo+ID4NCj4gPiBk aWZmIC0tZ2l0IGEvaW5jbHVkZS9saW51eC9hY3BpX2lvcnQuaCBiL2luY2x1ZGUvbGludXgvYWNw aV9pb3J0LmgNCj4gPiBpbmRleCAxODJhNTc3Li44OGYxN2M5IDEwMDY0NA0KPiA+IC0tLSBhL2lu Y2x1ZGUvbGludXgvYWNwaV9pb3J0LmgNCj4gPiArKysgYi9pbmNsdWRlL2xpbnV4L2FjcGlfaW9y dC5oDQo+ID4gQEAgLTU2LDcgKzU2LDcgQEAgY29uc3Qgc3RydWN0IGlvbW11X29wcyAqaW9ydF9p b21tdV9jb25maWd1cmUoc3RydWN0DQo+ID4gZGV2aWNlICpkZXYpICB7IHJldHVybiBOVUxMOyB9 ICBzdGF0aWMgaW5saW5lICBpbnQNCj4gPiBpb3J0X2lvbW11X21zaV9nZXRfcmVzdl9yZWdpb25z KHN0cnVjdCBkZXZpY2UgKmRldiwgc3RydWN0IGxpc3RfaGVhZA0KPiA+ICpoZWFkKSAteyByZXR1 cm4gLUVOT0RFVjsgfQ0KPiA+ICt7IHJldHVybiAwOyB9DQo+ID4gICNlbmRpZg0KPiA+DQo+ID4g ICNlbmRpZiAvKiBfX0FDUElfSU9SVF9IX18gKi8NCj4gPg0KPiA+IC0tPjgtLQ0KPiA+DQo+ID4N Cj4gPg0KX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX18KbGlu dXgtYXJtLWtlcm5lbCBtYWlsaW5nIGxpc3QKbGludXgtYXJtLWtlcm5lbEBsaXN0cy5pbmZyYWRl YWQub3JnCmh0dHA6Ly9saXN0cy5pbmZyYWRlYWQub3JnL21haWxtYW4vbGlzdGluZm8vbGludXgt YXJtLWtlcm5lbAo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: shameerali.kolothum.thodi@huawei.com (Shameerali Kolothum Thodi) Date: Tue, 7 Nov 2017 09:37:35 +0000 Subject: [PATCH v9 2/4] iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers In-Reply-To: <20171103113503.GB29434@red-moon> References: <20171006140450.89652-1-shameerali.kolothum.thodi@huawei.com> <20171006140450.89652-3-shameerali.kolothum.thodi@huawei.com> <20171013192350.GA32130@arm.com> <5FC3163CFD30C246ABAA99954A238FA83844672A@FRAEML521-MBX.china.huawei.com> <1d49243a-4746-f189-7c5d-4b98937115fb@arm.com> <5FC3163CFD30C246ABAA99954A238FA83844FE04@FRAEML521-MBX.china.huawei.com> <20171103113503.GB29434@red-moon> Message-ID: <5FC3163CFD30C246ABAA99954A238FA83845828E@FRAEML521-MBX.china.huawei.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > -----Original Message----- > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi at arm.com] > Sent: Friday, November 03, 2017 11:35 AM > To: Shameerali Kolothum Thodi > Cc: Robin Murphy ; Will Deacon > ; Gabriele Paoloni ; > marc.zyngier at arm.com; linux-pci at vger.kernel.org; joro at 8bytes.org; John > Garry ; Guohanjun (Hanjun Guo) > ; Linuxarm ; linux- > acpi at vger.kernel.org; iommu at lists.linux-foundation.org; Wangzhou (B) > ; sudeep.holla at arm.com; bhelgaas at google.com; > linux-arm-kernel at lists.infradead.org; devel at acpica.org > Subject: Re: [PATCH v9 2/4] iommu/dma: Add a helper function to reserve HW > MSI address regions for IOMMU drivers > > On Thu, Oct 26, 2017 at 10:11:58AM +0000, Shameerali Kolothum Thodi wrote: > [..] > > > > As we still don?t have a clear resolution on how to invoke the > > iort_iommu_msi_get_resv_regions(), I have gone back and attempted to > > move the smmu model check inside the iort code. This means the > > function will selectively apply HW MSI reservation based on the > > platform and also the function can be invoked from the > iommu_dma_get_resv_regions() directly. > > > > Could you please take a look at the below snippet and let me know your > feedback. > > Hope we can make some progress on this series. > > > > Thanks, > > Shameer > > > > -->8-- > > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c > > index 876c0e1..a27233d 100644 > > --- a/drivers/acpi/arm64/iort.c > > +++ b/drivers/acpi/arm64/iort.c > > @@ -619,6 +619,39 @@ static int __maybe_unused __get_pci_rid(struct > pci_dev *pdev, u16 alias, > > return 0; > > } > > > > +static bool __maybe_unused iort_hw_msi_resv_enable(struct device *dev, > > + struct acpi_iort_node *node) > > +{ > > + struct acpi_iort_node *iommu = NULL; > > + int i; > > + > > + if (dev_is_pci(dev)) { > > + u32 rid; > > + > > + pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid, &rid); > > + iommu = iort_node_map_id(node, rid, NULL, > IORT_IOMMU_TYPE); > > + } else { > > + for (i = 0; i < node->mapping_count; i++) { > > + iommu = iort_node_map_platform_id(node, NULL, > > + IORT_IOMMU_TYPE, > i); > > + if (iommu) > > + break; > > + } > > + } > > You do not need (and I do not want this code) to do the mapping again. > > You have the fwnode (ie dev->iommu_fwspec) corresponding to the IOMMU, > you can retrieve the SMMU IORT node by a simple look-up and carry out the > check below. Ok. Understood. I will rework this part then. > It would be simpler to set an option in the SMMUv3 driver but then you go back > to square one with DT/ACPI SMMUv3 driver awareness so, if, with the change > above this can make the generic approach work (ie Robin is happy with it) I am > fine with this IORT update as well. Thanks Lorenzo. I will rebase on top of rc1 and prepare v10 with these changes and sent it out. Shameer > > + > > + if (iommu && (iommu->type == ACPI_IORT_NODE_SMMU_V3)) { > > + struct acpi_iort_smmu_v3 *smmu; > > + > > + smmu = (struct acpi_iort_smmu_v3 *)iommu->node_data; > > + if (smmu->model == > ACPI_IORT_SMMU_V3_HISILICON_HI161X) { > > + dev_notice(dev, "Enabling HiSilicon erratum > 161010801\n"); > > + return true; > > + } > > + } > > + > > + return false; > > +} > > + > > static int arm_smmu_iort_xlate(struct device *dev, u32 streamid, > > struct fwnode_handle *fwnode, > > const struct iommu_ops *ops) @@ -682,6 +715,9 > @@ int > > iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head > *head) > > if (!node) > > return -ENODEV; > > > > + if (!iort_hw_msi_resv_enable(dev, node)) > > + return 0; > > + > > /* > > * Current logic to reserve ITS regions relies on HW topologies > > * where a given PCI or named component maps its IDs to only one > > diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c > > index 9d1cebe..67c6e30 100644 > > --- a/drivers/iommu/dma-iommu.c > > +++ b/drivers/iommu/dma-iommu.c > > @@ -19,6 +19,7 @@ > > * along with this program. If not, see . > > */ > > > > +#include > > #include > > #include > > #include > > @@ -174,6 +175,10 @@ void iommu_dma_get_resv_regions(struct device > *dev, struct list_head *list) > > struct pci_host_bridge *bridge; > > struct resource_entry *window; > > > > + if (!is_of_node(dev->iommu_fwspec->iommu_fwnode) && > > + iort_iommu_msi_get_resv_regions(dev, list) < 0) > > + return; > > + > > if (!dev_is_pci(dev)) > > return; > > > > diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h > > index 182a577..88f17c9 100644 > > --- a/include/linux/acpi_iort.h > > +++ b/include/linux/acpi_iort.h > > @@ -56,7 +56,7 @@ const struct iommu_ops *iort_iommu_configure(struct > > device *dev) { return NULL; } static inline int > > iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head > > *head) -{ return -ENODEV; } > > +{ return 0; } > > #endif > > > > #endif /* __ACPI_IORT_H__ */ > > > > -->8-- > > > > > > From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: multipart/mixed; boundary="===============6680869222410442831==" MIME-Version: 1.0 From: Shameerali Kolothum Thodi Subject: Re: [Devel] [PATCH v9 2/4] iommu/dma: Add a helper function to reserve HW MSI address regions for IOMMU drivers Date: Tue, 07 Nov 2017 09:37:35 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA83845828E@FRAEML521-MBX.china.huawei.com> In-Reply-To: 20171103113503.GB29434@red-moon List-ID: To: devel@acpica.org --===============6680869222410442831== Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: quoted-printable > -----Original Message----- > From: Lorenzo Pieralisi [mailto:lorenzo.pieralisi(a)arm.com] > Sent: Friday, November 03, 2017 11:35 AM > To: Shameerali Kolothum Thodi > Cc: Robin Murphy ; Will Deacon > ; Gabriele Paoloni ; > marc.zyngier(a)arm.com; linux-pci(a)vger.kernel.org; joro(a)8bytes.org; J= ohn > Garry ; Guohanjun (Hanjun Guo) > ; Linuxarm ; linux- > acpi(a)vger.kernel.org; iommu(a)lists.linux-foundation.org; Wangzhou (B) > ; sudeep.holla(a)arm.com; bhelgaas(a)google.co= m; > linux-arm-kernel(a)lists.infradead.org; devel(a)acpica.org > Subject: Re: [PATCH v9 2/4] iommu/dma: Add a helper function to reserve HW > MSI address regions for IOMMU drivers > = > On Thu, Oct 26, 2017 at 10:11:58AM +0000, Shameerali Kolothum Thodi wrote: > = [..] > > > > As we still don=E2=80=99t have a clear resolution on how to invoke the > > iort_iommu_msi_get_resv_regions(), I have gone back and attempted to > > move the smmu model check inside the iort code. This means the > > function will selectively apply HW MSI reservation based on the > > platform and also the function can be invoked from the > iommu_dma_get_resv_regions() directly. > > > > Could you please take a look at the below snippet and let me know your > feedback. > > Hope we can make some progress on this series. > > > > Thanks, > > Shameer > > > > -->8-- > > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c > > index 876c0e1..a27233d 100644 > > --- a/drivers/acpi/arm64/iort.c > > +++ b/drivers/acpi/arm64/iort.c > > @@ -619,6 +619,39 @@ static int __maybe_unused __get_pci_rid(struct > pci_dev *pdev, u16 alias, > > return 0; > > } > > > > +static bool __maybe_unused iort_hw_msi_resv_enable(struct device *dev, > > + struct acpi_iort_node *node) > > +{ > > + struct acpi_iort_node *iommu =3D NULL; > > + int i; > > + > > + if (dev_is_pci(dev)) { > > + u32 rid; > > + > > + pci_for_each_dma_alias(to_pci_dev(dev), __get_pci_rid, &rid); > > + iommu =3D iort_node_map_id(node, rid, NULL, > IORT_IOMMU_TYPE); > > + } else { > > + for (i =3D 0; i < node->mapping_count; i++) { > > + iommu =3D iort_node_map_platform_id(node, NULL, > > + IORT_IOMMU_TYPE, > i); > > + if (iommu) > > + break; > > + } > > + } > = > You do not need (and I do not want this code) to do the mapping again. > = > You have the fwnode (ie dev->iommu_fwspec) corresponding to the IOMMU, > you can retrieve the SMMU IORT node by a simple look-up and carry out the > check below. Ok. Understood. I will rework this part then. > It would be simpler to set an option in the SMMUv3 driver but then you go= back > to square one with DT/ACPI SMMUv3 driver awareness so, if, with the change > above this can make the generic approach work (ie Robin is happy with it)= I am > fine with this IORT update as well. Thanks Lorenzo. I will rebase on top of rc1 and prepare v10 with these chan= ges and sent it out. Shameer = > > + > > + if (iommu && (iommu->type =3D=3D ACPI_IORT_NODE_SMMU_V3)) { > > + struct acpi_iort_smmu_v3 *smmu; > > + > > + smmu =3D (struct acpi_iort_smmu_v3 *)iommu->node_data; > > + if (smmu->model =3D=3D > ACPI_IORT_SMMU_V3_HISILICON_HI161X) { > > + dev_notice(dev, "Enabling HiSilicon erratum > 161010801\n"); > > + return true; > > + } > > + } > > + > > + return false; > > +} > > + > > static int arm_smmu_iort_xlate(struct device *dev, u32 streamid, > > struct fwnode_handle *fwnode, > > const struct iommu_ops *ops) @@ -682,6 +715,9 > @@ int > > iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head > *head) > > if (!node) > > return -ENODEV; > > > > + if (!iort_hw_msi_resv_enable(dev, node)) > > + return 0; > > + > > /* > > * Current logic to reserve ITS regions relies on HW topologies > > * where a given PCI or named component maps its IDs to only one > > diff --git a/drivers/iommu/dma-iommu.c b/drivers/iommu/dma-iommu.c > > index 9d1cebe..67c6e30 100644 > > --- a/drivers/iommu/dma-iommu.c > > +++ b/drivers/iommu/dma-iommu.c > > @@ -19,6 +19,7 @@ > > * along with this program. If not, see . > > */ > > > > +#include > > #include > > #include > > #include > > @@ -174,6 +175,10 @@ void iommu_dma_get_resv_regions(struct device > *dev, struct list_head *list) > > struct pci_host_bridge *bridge; > > struct resource_entry *window; > > > > + if (!is_of_node(dev->iommu_fwspec->iommu_fwnode) && > > + iort_iommu_msi_get_resv_regions(dev, list) < 0) > > + return; > > + > > if (!dev_is_pci(dev)) > > return; > > > > diff --git a/include/linux/acpi_iort.h b/include/linux/acpi_iort.h > > index 182a577..88f17c9 100644 > > --- a/include/linux/acpi_iort.h > > +++ b/include/linux/acpi_iort.h > > @@ -56,7 +56,7 @@ const struct iommu_ops *iort_iommu_configure(struct > > device *dev) { return NULL; } static inline int > > iort_iommu_msi_get_resv_regions(struct device *dev, struct list_head > > *head) -{ return -ENODEV; } > > +{ return 0; } > > #endif > > > > #endif /* __ACPI_IORT_H__ */ > > > > -->8-- > > > > > > --===============6680869222410442831==--