From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shameerali Kolothum Thodi Subject: RE: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk Date: Fri, 9 Nov 2018 16:50:40 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA8387C64F2@FRAEML521-MBX.china.huawei.com> References: <20181016124920.24708-1-shameerali.kolothum.thodi@huawei.com> <20181016124920.24708-5-shameerali.kolothum.thodi@huawei.com> <0d7a984e-5814-a986-cd48-ef0651079e32@arm.com> <5FC3163CFD30C246ABAA99954A238FA8387A0342@FRAEML521-MBX.china.huawei.com> <5FC3163CFD30C246ABAA99954A238FA8387A0575@FRAEML521-MBX.china.huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: <5FC3163CFD30C246ABAA99954A238FA8387A0575@FRAEML521-MBX.china.huawei.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Robin Murphy , "lorenzo.pieralisi@arm.com" , "jean-philippe.brucker@arm.com" Cc: "mark.rutland@arm.com" , "vkilari@codeaurora.org" , "neil.m.leeder@gmail.com" , "pabba@codeaurora.org" , "will.deacon@arm.com" , "rruigrok@codeaurora.org" , Linuxarm , "linux-acpi@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" List-Id: linux-acpi@vger.kernel.org SGkgUm9iaW4sDQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogTGludXhh cm0gW21haWx0bzpsaW51eGFybS1ib3VuY2VzQGh1YXdlaS5jb21dIE9uIEJlaGFsZiBPZg0KPiBT aGFtZWVyYWxpIEtvbG90aHVtIFRob2RpDQo+IFNlbnQ6IDE4IE9jdG9iZXIgMjAxOCAxNjoyNw0K PiBUbzogUm9iaW4gTXVycGh5IDxyb2Jpbi5tdXJwaHlAYXJtLmNvbT47IGxvcmVuem8ucGllcmFs aXNpQGFybS5jb207DQo+IGplYW4tcGhpbGlwcGUuYnJ1Y2tlckBhcm0uY29tDQo+IENjOiBtYXJr LnJ1dGxhbmRAYXJtLmNvbTsgdmtpbGFyaUBjb2RlYXVyb3JhLm9yZzsNCj4gbmVpbC5tLmxlZWRl ckBnbWFpbC5jb207IHBhYmJhQGNvZGVhdXJvcmEub3JnOyB3aWxsLmRlYWNvbkBhcm0uY29tOw0K PiBycnVpZ3Jva0Bjb2RlYXVyb3JhLm9yZzsgTGludXhhcm0gPGxpbnV4YXJtQGh1YXdlaS5jb20+ OyBsaW51eC0NCj4gYWNwaUB2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4LWFybS1rZXJuZWxAbGlzdHMu aW5mcmFkZWFkLm9yZzsgbGludXgtDQo+IGtlcm5lbEB2Z2VyLmtlcm5lbC5vcmcNCj4gU3ViamVj dDogUkU6IFtQQVRDSCB2NCA0LzRdIHBlcmYvc21tdXYzX3BtdTogRW5hYmxlIEhpU2lsaWNvbiBF cnJhdHVtDQo+IDE2MjAwMTgwMCBxdWlyaw0KIA0KWy4uLl0NCg0KPiANCj4gPiA+ID4gK3N0YXRp YyBjb25zdCBzdHJ1Y3Qgc21tdV9wbXVfZXJyYXR1bV93YSBzbW11X3BtdV93YVtdID0gew0KPiA+ ID4gPiArCXsNCj4gPiA+ID4gKwkJLm1hdGNoX3R5cGUgPSBzZV9tYXRjaF9hY3BpX29lbSwNCj4g PiA+ID4gKwkJLmlkID0gaGlzaV8xNjIwMDE4MDBfb2VtX2luZm8sDQo+ID4gPiA+ICsJCS5kZXNj X3N0ciA9ICJIaVNpbGljb24gZXJyYXR1bSAxNjIwMDE4MDAiLA0KPiA+ID4gPiArCQkuZW5hYmxl ID0gaGlzaV9lcnJhdHVtX2V2Y250cl9yZG9ubHksDQo+ID4gPiA+ICsJfSwNCj4gPiA+ID4gK307 DQo+ID4gPiA+ICsNCj4gPiA+DQo+ID4gPiBUaGVyZSdzIGFuIGF3ZnVsIGxvdCBvZiByYXcgQUNQ SSBpbnRlcm5hbHMgc3BsYXNoZWQgYWJvdXQgaGVyZSAtDQo+ID4gPiBjb3VsZG4ndCBhdCBsZWFz dCBzb21lIG9mIGl0IGJlIGFic3RyYWN0ZWQgYmVoaW5kIHRoZSBJT1JUIGNvZGU/IEluDQo+ID4g PiBmYWN0LCBjYW4ndCBJT1JUIGp1c3Qgc2V0IGFsbCB0aGlzIHN0dWZmIHVwIGluIGFkdmFuY2Ug bGlrZSBpdCBkb2VzIGZvcg0KPiA+ID4gU01NVXM/DQo+ID4NCj4gPiBIbW1tLi4gU29ycnksIG5v dCBjbGVhciB0byBtZS4gWW91IG1lYW4gdG8gc2F5IGFzc29jaWF0ZSB0aGUgSU9SVCBub2RlDQo+ ID4gd2l0aCBwbGF0Zm9ybSBkZXZpY2UgYW5kIHJldHJpZXZlIGl0IGluIGRyaXZlciBqdXN0IGxp a2Ugc21tdSBkb2VzIGZvcg0KPiA+ICJtb2RlbCIgY2hlY2tzPyBOb3Qgc3VyZSB0aGF0IHdvcmtz IGhlcmUgaWYgdGhhdOKAmXMgd2hhdCB0aGUgYWJvdmUgbWVhbnQuDQo+ID4NCj4gPiA+ID4gICAj ZGVmaW5lIHRvX3NtbXVfcG11KHApIChjb250YWluZXJfb2YocCwgc3RydWN0IHNtbXVfcG11LCBw bXUpKQ0KPiA+ID4gPg0KPiA+ID4gPiAgICNkZWZpbmUgU01NVV9QTVVfRVZFTlRfQVRUUl9FWFRS QUNUT1IoX25hbWUsIF9jb25maWcsIF9zdGFydCwNCj4gPiA+IF9lbmQpICAgICAgICBcDQo+ID4g PiA+IEBAIC0yMjQsMTUgKzI3MSwyMCBAQCBzdGF0aWMgdm9pZCBzbW11X3BtdV9zZXRfcGVyaW9k KHN0cnVjdA0KPiA+ID4gc21tdV9wbXUgKnNtbXVfcG11LA0KPiA+ID4gPiAgIAl1MzIgaWR4ID0g aHdjLT5pZHg7DQo+ID4gPiA+ICAgCXU2NCBuZXc7DQo+ID4gPiA+DQo+ID4gPiA+IC0JLyoNCj4g PiA+ID4gLQkgKiBXZSBsaW1pdCB0aGUgbWF4IHBlcmlvZCB0byBoYWxmIHRoZSBtYXggY291bnRl ciB2YWx1ZSBvZiB0aGUNCj4gPiA+IGNvdW50ZXINCj4gPiA+ID4gLQkgKiBzaXplLCBzbyB0aGF0 IGV2ZW4gaW4gdGhlIGNhc2Ugb2YgZXh0cmVtZSBpbnRlcnJ1cHQgbGF0ZW5jeSB0aGUNCj4gPiA+ ID4gLQkgKiBjb3VudGVyIHdpbGwgKGhvcGVmdWxseSkgbm90IHdyYXAgcGFzdCBpdHMgaW5pdGlh bCB2YWx1ZS4NCj4gPiA+ID4gLQkgKi8NCj4gPiA+ID4gLQluZXcgPSBzbW11X3BtdS0+Y291bnRl cl9tYXNrID4+IDE7DQo+ID4gPiA+ICsJaWYgKHNtbXVfcG11LT5vcHRpb25zICYgU01NVV9QTVVf T1BUX0VWQ05UUl9SRE9OTFkpIHsNCj4gPiA+ID4gKwkJbmV3ID0gc21tdV9wbXVfY291bnRlcl9n ZXRfdmFsdWUoc21tdV9wbXUsIGlkeCk7DQo+ID4gPg0KPiA+ID4gU29tZXRoaW5nJ3MgY2xlYXJs eSBtaXNzaW5nLCBiZWNhdXNlIGlmIHRoaXMgaGFwcGVucyB0byBzdGFydCBhdCAwLCB0aGUNCj4g PiA+IGN1cnJlbnQgb3ZlcmZsb3cgaGFuZGxpbmcgY29kZSBjYW5ub3QgcG9zc2libHkgZ2l2ZSB0 aGUgY29ycmVjdCBjb3VudC4NCj4gPiA+IE11Y2ggYXMgSSBoYXRlIHRoZSByZXNldC10by1oYWxm LXBlcmlvZCBpZGlvbSBmb3IgYmVpbmcgaW1wb3NzaWJsZSB0bw0KPiA+ID4gbWFrZSBzZW5zZSBv ZiwgaXQgZG9lcyBtYWtlIHZhcmlvdXMgYXNwZWN0cyBhcHBlYXIgYSBsb3Qgc2ltcGxlciB0aGFu DQo+ID4gPiB0aGV5IHJlYWxseSBhcmUuIFdhaXQsIG1heWJlIHRoYXQncyB5ZXQgYW5vdGhlciBy ZWFzb24gdG8gaGF0ZSBpdC4uLg0KPiA+DQo+ID4gWWVzLCAgaWYgdGhlIGNvdW50ZXIgc3RhcnRz IGF0IDAgYW5kIG92ZXJmbG93IGhhcHBlbnMsIGl0IHdvbid0IHBvc3NpYmx5IGdpdmUNCj4gPiB0 aGUgY29ycmVjdCBjb3VudCBjb21wYXJlZCB0byB0aGUgcmVzZXQtdG8taGFsZi1wZXJpb2QgbG9n aWMuIFNpbmNlIHRoaXMgaXMgYQ0KPiA+IDY0IGJpdCBjb3VudGVyLCBqdXN0IGhvcGUgdGhhdCwg aXQgd29uJ3QgbmVjZXNzYXJpbHkgaGFwcGVuIHRoYXQgb2Z0ZW4uDQo+IA0KPiBbLi4uXQ0KPiAN Cj4gPiA+ID4gK3N0YXRpYyB2b2lkIHNtbXVfcG11X2VuYWJsZV9lcnJhdGEoc3RydWN0IHNtbXVf cG11ICpzbW11X3BtdSwNCj4gPiA+ID4gKwkJCQllbnVtIHNtbXVfcG11X2VycmF0dW1fbWF0Y2hf dHlwZSB0eXBlLA0KPiA+ID4gPiArCQkJCXNlX21hdGNoX2ZuX3QgbWF0Y2hfZm4sDQo+ID4gPiA+ ICsJCQkJdm9pZCAqYXJnKQ0KPiA+ID4gPiArew0KPiA+ID4gPiArCWNvbnN0IHN0cnVjdCBzbW11 X3BtdV9lcnJhdHVtX3dhICp3YSA9IHNtbXVfcG11X3dhOw0KPiA+ID4gPiArDQo+ID4gPiA+ICsJ Zm9yICg7IHdhLT5kZXNjX3N0cjsgd2ErKykgew0KPiA+ID4gPiArCQlpZiAod2EtPm1hdGNoX3R5 cGUgIT0gdHlwZSkNCj4gPiA+ID4gKwkJCWNvbnRpbnVlOw0KPiA+ID4gPiArDQo+ID4gPiA+ICsJ CWlmIChtYXRjaF9mbih3YSwgYXJnKSkgew0KPiA+ID4gPiArCQkJaWYgKHdhLT5lbmFibGUpIHsN Cj4gPiA+ID4gKwkJCQl3YS0+ZW5hYmxlKHNtbXVfcG11KTsNCj4gPiA+ID4gKwkJCQlkZXZfaW5m byhzbW11X3BtdS0+ZGV2LA0KPiA+ID4gPiArCQkJCQkiRW5hYmxpbmcgd29ya2Fyb3VuZCBmb3Ig JXNcbiIsDQo+ID4gPiA+ICsJCQkJCSB3YS0+ZGVzY19zdHIpOw0KPiA+ID4gPiArCQkJfQ0KPiA+ ID4NCj4gPiA+IEp1c3QgaG93IG1hbnkga2luZHMgb2YgYnJva2VuIGFyZSB3ZSBleHBlY3Rpbmcg aGVyZT8gSXMgdGhpcyBsaWZ0ZWQgZnJvbQ0KPiA+ID4gdGhlIGFybTY0IGNwdWZlYXR1cmUgZnJh bWV3b3JrLCBiZWNhdXNlIGl0IHNlZW1zIGxpa2UgYWJzb2x1dGUgb3ZlcmtpbGwNCj4gPiA+IGZv ciBhIHNpbXBsZSBQTVUgZHJpdmVyIHdoaWNoIGluIGFsbCByZWFsaXR5IGlzIG9ubHkgZXZlciBn b2luZyB0bw0KPiA+ID4gd2lnZ2xlIGEgZmV3IGZsYWdzIGluIHNvbWUgZGF0YSBzdHJ1Y3R1cmUu DQo+ID4NCj4gPiBZZXMsIHRoaXMgZXJyYXR1bSBmcmFtZXdvcmsgaXMgYmFzZWQgb24gdGhlIGFy bV9hcmNoX3RpbWVyIGNvZGUuIEFncmVlDQo+IHRoYXQNCj4gPiB0aGlzIGlzIGFuIG92ZXJraWxs IGlmIGl0IGlzIGp1c3QgdG8gc3VwcG9ydCB0aGlzIGhhcmR3YXJlLiBJIGFtIG5vdCBzdXJlIHRo aXMgY2FuDQo+IGJlDQo+ID4gZXh0ZW5kZWQgdG8gYWRkIHRoZSBJTVBMRU1FTlRBVElPTiBERUZJ TkVEIGV2ZW50cyBpbiBmdXR1cmUoSSBoYXZlbid0DQo+ID4gbG9va2VkIGludG8gdGhhdCBub3cp LiBJZiB0aGlzIGlzIG5vdCB0aGF0IHVzZWZ1bCBpbiB0aGUgbmVhciBmdXR1cmUsIEkgd2lsbCBy ZW1vdmUNCj4gPiB0aGUNCj4gPiBmcmFtZXdvcmsgcGFydCBhbmQgdXNlIHRoZSBPRU0gaW5mbyBk aXJlY3RseSB0byBzZXQgdGhlIGZsYWcuIFBsZWFzZSBsZXQgbWUNCj4gPiBrbm93DQo+ID4geW91 ciB0aG91Z2h0cy4uDQo+IA0KPiBCZWxvdyBpcyBhbm90aGVyIHRha2Ugb24gdGhpcyBwYXRjaC4g UGxlYXNlIGxldCBtZSBrbm93IGlmIHRoaXMgbWFrZXMgYW55DQo+IHNlbnNlLi4NCg0KQ291bGQg eW91IHBsZWFzZSBsZXQgbWUga25vdyB3aGV0aGVyIHRoZSBiZWxvdyAic2ltcGxpZmllZCIgdmVy c2lvbiBvZg0KZXJyYXR1bSBsb29rcyBhbnkgYmV0dGVyIG9yIG5vdD8gIEFuZCBhcHByZWNpYXRl IGFueSBvdGhlciBjb21tZW50cyBvbg0KdGhlIHJlc3Qgb2YgdGhlIHNlcmllcyBhcyB3ZWxsIHNv IHRoYXQgSSBjYW4gd29yayBvbiB0aGlzIGFuZCByZXNwaW4uDQoNClRoYW5rcywNClNoYW1lZXIN Cg0KPiBUaGFua3MsDQo+IFNoYW1lZXINCj4gDQo+IC0tLS04LS0tLQ0KPiBkaWZmIC0tZ2l0IGEv ZHJpdmVycy9wZXJmL2FybV9zbW11djNfcG11LmMNCj4gYi9kcml2ZXJzL3BlcmYvYXJtX3NtbXV2 M19wbXUuYw0KPiBpbmRleCBlZjk0YjkwLi42ZjgxYjk0IDEwMDY0NA0KPiAtLS0gYS9kcml2ZXJz L3BlcmYvYXJtX3NtbXV2M19wbXUuYw0KPiArKysgYi9kcml2ZXJzL3BlcmYvYXJtX3NtbXV2M19w bXUuYw0KPiBAQCAtOTYsNiArOTYsOCBAQA0KPiANCj4gICNkZWZpbmUgU01NVV9QQV9TSElGVCAg ICAgICAgICAgICAgICAgICAxMg0KPiANCj4gKyNkZWZpbmUgU01NVV9QTVVfT1BUX0VWQ05UUl9S RE9OTFkJKDEgPDwgMCkNCj4gKw0KPiAgc3RhdGljIGludCBjcHVocF9zdGF0ZV9udW07DQo+IA0K PiAgc3RydWN0IHNtbXVfcG11IHsNCj4gQEAgLTExMSwxMCArMTEzLDM4IEBAIHN0cnVjdCBzbW11 X3BtdSB7DQo+ICAJc3RydWN0IGRldmljZSAqZGV2Ow0KPiAgCXZvaWQgX19pb21lbSAqcmVnX2Jh c2U7DQo+ICAJdm9pZCBfX2lvbWVtICpyZWxvY19iYXNlOw0KPiArCXUzMiBvcHRpb25zOw0KPiAg CXU2NCBjb3VudGVyX3ByZXNlbnRfbWFzazsNCj4gIAl1NjQgY291bnRlcl9tYXNrOw0KPiAgfTsN Cj4gDQo+ICtzdHJ1Y3QgZXJyYXR1bV9hY3BpX29lbV9pbmZvIHsNCj4gKwljaGFyIG9lbV9pZFtB Q1BJX09FTV9JRF9TSVpFICsgMV07DQo+ICsJY2hhciBvZW1fdGFibGVfaWRbQUNQSV9PRU1fVEFC TEVfSURfU0laRSArIDFdOw0KPiArCXUzMiBvZW1fcmV2aXNpb247DQo+ICsJdm9pZCAoKmVuYWJs ZSkoc3RydWN0IHNtbXVfcG11ICpzbW11X3BtdSk7DQo+ICt9Ow0KPiArDQo+ICt2b2lkIGhpc2lf ZXJyYXR1bV9ldmNudHJfcmRvbmx5KHN0cnVjdCBzbW11X3BtdSAqc21tdV9wbXUpDQo+ICt7DQo+ ICsJc21tdV9wbXUtPm9wdGlvbnMgfD0gU01NVV9QTVVfT1BUX0VWQ05UUl9SRE9OTFk7DQo+ICsJ ZGV2X2luZm8oc21tdV9wbXUtPmRldiwgIkVuYWJsaW5nIEhpU2lsaWNvbiBlcnJhdHVtDQo+IDE2 MjAwMTgwMFxuIik7DQo+ICt9DQo+ICsNCj4gK3N0YXRpYyBzdHJ1Y3QgZXJyYXR1bV9hY3BpX29l bV9pbmZvIGFjcGlfb2VtX2luZm9bXSA9IHsNCj4gKwkvKg0KPiArCSAqIE5vdGUgdGhhdCB0cmFp bGluZyBzcGFjZXMgYXJlIHJlcXVpcmVkIHRvIHByb3Blcmx5IG1hdGNoDQo+ICsJICogdGhlIE9F TSB0YWJsZSBpbmZvcm1hdGlvbi4NCj4gKwkgKi8NCj4gKwl7DQo+ICsJCS5vZW1faWQgICAgICAg ICA9ICJISVNJICAiLA0KPiArCQkub2VtX3RhYmxlX2lkICAgPSAiSElQMDggICAiLA0KPiArCQku b2VtX3JldmlzaW9uICAgPSAwLA0KPiArCQkuZW5hYmxlID0gaGlzaV9lcnJhdHVtX2V2Y250cl9y ZG9ubHksDQo+ICsJfSwNCj4gKwl7IC8qIFNlbnRpbmVsIGluZGljYXRpbmcgdGhlIGVuZCBvZiB0 aGUgT0VNIGFycmF5ICovIH0sDQo+ICt9Ow0KPiArDQo+ICAjZGVmaW5lIHRvX3NtbXVfcG11KHAp IChjb250YWluZXJfb2YocCwgc3RydWN0IHNtbXVfcG11LCBwbXUpKQ0KPiANCj4gICNkZWZpbmUg U01NVV9QTVVfRVZFTlRfQVRUUl9FWFRSQUNUT1IoX25hbWUsIF9jb25maWcsIF9zdGFydCwgX2Vu ZCkNCj4gXA0KPiBAQCAtMjI0LDE1ICsyNTQsMjAgQEAgc3RhdGljIHZvaWQgc21tdV9wbXVfc2V0 X3BlcmlvZChzdHJ1Y3QNCj4gc21tdV9wbXUgKnNtbXVfcG11LA0KPiAgCXUzMiBpZHggPSBod2Mt PmlkeDsNCj4gIAl1NjQgbmV3Ow0KPiANCj4gLQkvKg0KPiAtCSAqIFdlIGxpbWl0IHRoZSBtYXgg cGVyaW9kIHRvIGhhbGYgdGhlIG1heCBjb3VudGVyIHZhbHVlIG9mIHRoZQ0KPiBjb3VudGVyDQo+ IC0JICogc2l6ZSwgc28gdGhhdCBldmVuIGluIHRoZSBjYXNlIG9mIGV4dHJlbWUgaW50ZXJydXB0 IGxhdGVuY3kgdGhlDQo+IC0JICogY291bnRlciB3aWxsIChob3BlZnVsbHkpIG5vdCB3cmFwIHBh c3QgaXRzIGluaXRpYWwgdmFsdWUuDQo+IC0JICovDQo+IC0JbmV3ID0gc21tdV9wbXUtPmNvdW50 ZXJfbWFzayA+PiAxOw0KPiArCWlmIChzbW11X3BtdS0+b3B0aW9ucyAmIFNNTVVfUE1VX09QVF9F VkNOVFJfUkRPTkxZKSB7DQo+ICsJCW5ldyA9IHNtbXVfcG11X2NvdW50ZXJfZ2V0X3ZhbHVlKHNt bXVfcG11LCBpZHgpOw0KPiArCX0gZWxzZSB7DQo+ICsJCS8qDQo+ICsJCSAqIFdlIGxpbWl0IHRo ZSBtYXggcGVyaW9kIHRvIGhhbGYgdGhlIG1heCBjb3VudGVyIHZhbHVlDQo+ICsJCSAqIG9mIHRo ZSBjb3VudGVyIHNpemUsIHNvIHRoYXQgZXZlbiBpbiB0aGUgY2FzZSBvZiBleHRyZW1lDQo+ICsJ CSAqIGludGVycnVwdCBsYXRlbmN5IHRoZSBjb3VudGVyIHdpbGwgKGhvcGVmdWxseSkgbm90IHdy YXANCj4gKwkJICogcGFzdCBpdHMgaW5pdGlhbCB2YWx1ZS4NCj4gKwkJICovDQo+ICsJCW5ldyA9 IHNtbXVfcG11LT5jb3VudGVyX21hc2sgPj4gMTsNCj4gKwkJc21tdV9wbXVfY291bnRlcl9zZXRf dmFsdWUoc21tdV9wbXUsIGlkeCwgbmV3KTsNCj4gKwl9DQo+IA0KPiAgCWxvY2FsNjRfc2V0KCZo d2MtPnByZXZfY291bnQsIG5ldyk7DQo+IC0Jc21tdV9wbXVfY291bnRlcl9zZXRfdmFsdWUoc21t dV9wbXUsIGlkeCwgbmV3KTsNCj4gIH0NCj4gDQo+ICBzdGF0aWMgdm9pZCBzbW11X3BtdV9nZXRf ZXZlbnRfZmlsdGVyKHN0cnVjdCBwZXJmX2V2ZW50ICpldmVudCwgdTMyICpzcGFuLA0KPiBAQCAt NjcwLDYgKzcwNSwyOCBAQCBzdGF0aWMgdm9pZCBzbW11X3BtdV9yZXNldChzdHJ1Y3Qgc21tdV9w bXUNCj4gKnNtbXVfcG11KQ0KPiAgCQkgICAgICAgc21tdV9wbXUtPnJlbG9jX2Jhc2UgKyBTTU1V X1BNQ0dfT1ZTQ0xSMCk7DQo+ICB9DQo+IA0KPiArc3RhdGljIHZvaWQgc21tdV9wbXVfY2hlY2tf YWNwaV93b3JrYXJvdW5kcyhzdHJ1Y3Qgc21tdV9wbXUNCj4gKnNtbXVfcG11KQ0KPiArew0KPiAr CXN0YXRpYyBjb25zdCBzdHJ1Y3QgZXJyYXR1bV9hY3BpX29lbV9pbmZvIGVtcHR5X29lbV9pbmZv ID0ge307DQo+ICsJY29uc3Qgc3RydWN0IGVycmF0dW1fYWNwaV9vZW1faW5mbyAqaW5mbyA9IGFj cGlfb2VtX2luZm87DQo+ICsJc3RydWN0IGFjcGlfdGFibGVfaGVhZGVyICpoZHI7DQo+ICsNCj4g KwlpZiAoQUNQSV9GQUlMVVJFKGFjcGlfZ2V0X3RhYmxlKEFDUElfU0lHX0lPUlQsIDAsICZoZHIp KSkgew0KPiArCQlkZXZfZXJyKHNtbXVfcG11LT5kZXYsICJmYWlsZWQgdG8gZ2V0IElPUlRcbiIp Ow0KPiArCQlyZXR1cm47DQo+ICsJfQ0KPiArDQo+ICsJLyogSXRlcmF0ZSBvdmVyIHRoZSBBQ1BJ IE9FTSBpbmZvIGFycmF5LCBsb29raW5nIGZvciBhIG1hdGNoICovDQo+ICsJd2hpbGUgKG1lbWNt cChpbmZvLCAmZW1wdHlfb2VtX2luZm8sIHNpemVvZigqaW5mbykpKSB7DQo+ICsJCWlmICghbWVt Y21wKGluZm8tPm9lbV9pZCwgaGRyLT5vZW1faWQsIEFDUElfT0VNX0lEX1NJWkUpDQo+ICYmDQo+ ICsJCSAgICAhbWVtY21wKGluZm8tPm9lbV90YWJsZV9pZCwgaGRyLT5vZW1fdGFibGVfaWQsDQo+ IEFDUElfT0VNX1RBQkxFX0lEX1NJWkUpICYmDQo+ICsJCQlpbmZvLT5vZW1fcmV2aXNpb24gPT0g aGRyLT5vZW1fcmV2aXNpb24pDQo+ICsJCQlpbmZvLT5lbmFibGUoc21tdV9wbXUpOw0KPiArDQo+ ICsJCWluZm8rKzsNCj4gKwl9DQo+ICt9DQo+ICsNCj4gIHN0YXRpYyBpbnQgc21tdV9wbXVfcHJv YmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikNCj4gIHsNCj4gIAlzdHJ1Y3Qgc21tdV9w bXUgKnNtbXVfcG11Ow0KPiBAQCAtNzQ5LDYgKzgwNiw4IEBAIHN0YXRpYyBpbnQgc21tdV9wbXVf cHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZQ0KPiAqcGRldikNCj4gIAkJcmV0dXJuIC1FSU5W QUw7DQo+ICAJfQ0KPiANCj4gKwlzbW11X3BtdV9jaGVja19hY3BpX3dvcmthcm91bmRzKHNtbXVf cG11KTsNCj4gKw0KPiAgCS8qIFBpY2sgb25lIENQVSB0byBiZSB0aGUgcHJlZmVycmVkIG9uZSB0 byB1c2UgKi8NCj4gIAlzbW11X3BtdS0+b25fY3B1ID0gZ2V0X2NwdSgpOw0KPiAgCVdBUk5fT04o aXJxX3NldF9hZmZpbml0eShzbW11X3BtdS0+aXJxLCBjcHVtYXNrX29mKHNtbXVfcG11LQ0KPiA+ b25fY3B1KSkpOw0KPiANCj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18NCj4gTGludXhhcm0gbWFpbGluZyBsaXN0DQo+IExpbnV4YXJtQGh1YXdlaS5jb20N Cj4gaHR0cDovL2h1bGsuaHVhd2VpLmNvbS9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4YXJtDQo= From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8E4FFC43441 for ; Fri, 9 Nov 2018 16:50:54 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 54EAF20818 for ; Fri, 9 Nov 2018 16:50:54 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 54EAF20818 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728469AbeKJCcP (ORCPT ); Fri, 9 Nov 2018 21:32:15 -0500 Received: from lhrrgout.huawei.com ([185.176.76.210]:32729 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727955AbeKJCcP (ORCPT ); Fri, 9 Nov 2018 21:32:15 -0500 Received: from lhreml706-cah.china.huawei.com (unknown [172.18.7.107]) by Forcepoint Email with ESMTP id 58157DB0B40BA; Fri, 9 Nov 2018 16:50:48 +0000 (GMT) Received: from FRAEML701-CAH.china.huawei.com (10.206.14.32) by lhreml706-cah.china.huawei.com (10.201.108.47) with Microsoft SMTP Server (TLS) id 14.3.408.0; Fri, 9 Nov 2018 16:50:50 +0000 Received: from FRAEML521-MBX.china.huawei.com ([169.254.1.244]) by FRAEML701-CAH.china.huawei.com ([10.206.14.32]) with mapi id 14.03.0415.000; Fri, 9 Nov 2018 17:50:40 +0100 From: Shameerali Kolothum Thodi To: Robin Murphy , "lorenzo.pieralisi@arm.com" , "jean-philippe.brucker@arm.com" CC: "mark.rutland@arm.com" , "vkilari@codeaurora.org" , "neil.m.leeder@gmail.com" , "pabba@codeaurora.org" , "will.deacon@arm.com" , "rruigrok@codeaurora.org" , Linuxarm , "linux-acpi@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk Thread-Topic: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk Thread-Index: AQHUZvc2reJJPnp8kkCLDnIcfLvBeaVHyQog Date: Fri, 9 Nov 2018 16:50:40 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA8387C64F2@FRAEML521-MBX.china.huawei.com> References: <20181016124920.24708-1-shameerali.kolothum.thodi@huawei.com> <20181016124920.24708-5-shameerali.kolothum.thodi@huawei.com> <0d7a984e-5814-a986-cd48-ef0651079e32@arm.com> <5FC3163CFD30C246ABAA99954A238FA8387A0342@FRAEML521-MBX.china.huawei.com> <5FC3163CFD30C246ABAA99954A238FA8387A0575@FRAEML521-MBX.china.huawei.com> In-Reply-To: <5FC3163CFD30C246ABAA99954A238FA8387A0575@FRAEML521-MBX.china.huawei.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.237] Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org SGkgUm9iaW4sDQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogTGludXhh cm0gW21haWx0bzpsaW51eGFybS1ib3VuY2VzQGh1YXdlaS5jb21dIE9uIEJlaGFsZiBPZg0KPiBT aGFtZWVyYWxpIEtvbG90aHVtIFRob2RpDQo+IFNlbnQ6IDE4IE9jdG9iZXIgMjAxOCAxNjoyNw0K PiBUbzogUm9iaW4gTXVycGh5IDxyb2Jpbi5tdXJwaHlAYXJtLmNvbT47IGxvcmVuem8ucGllcmFs aXNpQGFybS5jb207DQo+IGplYW4tcGhpbGlwcGUuYnJ1Y2tlckBhcm0uY29tDQo+IENjOiBtYXJr LnJ1dGxhbmRAYXJtLmNvbTsgdmtpbGFyaUBjb2RlYXVyb3JhLm9yZzsNCj4gbmVpbC5tLmxlZWRl ckBnbWFpbC5jb207IHBhYmJhQGNvZGVhdXJvcmEub3JnOyB3aWxsLmRlYWNvbkBhcm0uY29tOw0K PiBycnVpZ3Jva0Bjb2RlYXVyb3JhLm9yZzsgTGludXhhcm0gPGxpbnV4YXJtQGh1YXdlaS5jb20+ OyBsaW51eC0NCj4gYWNwaUB2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4LWFybS1rZXJuZWxAbGlzdHMu aW5mcmFkZWFkLm9yZzsgbGludXgtDQo+IGtlcm5lbEB2Z2VyLmtlcm5lbC5vcmcNCj4gU3ViamVj dDogUkU6IFtQQVRDSCB2NCA0LzRdIHBlcmYvc21tdXYzX3BtdTogRW5hYmxlIEhpU2lsaWNvbiBF cnJhdHVtDQo+IDE2MjAwMTgwMCBxdWlyaw0KIA0KWy4uLl0NCg0KPiANCj4gPiA+ID4gK3N0YXRp YyBjb25zdCBzdHJ1Y3Qgc21tdV9wbXVfZXJyYXR1bV93YSBzbW11X3BtdV93YVtdID0gew0KPiA+ ID4gPiArCXsNCj4gPiA+ID4gKwkJLm1hdGNoX3R5cGUgPSBzZV9tYXRjaF9hY3BpX29lbSwNCj4g PiA+ID4gKwkJLmlkID0gaGlzaV8xNjIwMDE4MDBfb2VtX2luZm8sDQo+ID4gPiA+ICsJCS5kZXNj X3N0ciA9ICJIaVNpbGljb24gZXJyYXR1bSAxNjIwMDE4MDAiLA0KPiA+ID4gPiArCQkuZW5hYmxl ID0gaGlzaV9lcnJhdHVtX2V2Y250cl9yZG9ubHksDQo+ID4gPiA+ICsJfSwNCj4gPiA+ID4gK307 DQo+ID4gPiA+ICsNCj4gPiA+DQo+ID4gPiBUaGVyZSdzIGFuIGF3ZnVsIGxvdCBvZiByYXcgQUNQ SSBpbnRlcm5hbHMgc3BsYXNoZWQgYWJvdXQgaGVyZSAtDQo+ID4gPiBjb3VsZG4ndCBhdCBsZWFz dCBzb21lIG9mIGl0IGJlIGFic3RyYWN0ZWQgYmVoaW5kIHRoZSBJT1JUIGNvZGU/IEluDQo+ID4g PiBmYWN0LCBjYW4ndCBJT1JUIGp1c3Qgc2V0IGFsbCB0aGlzIHN0dWZmIHVwIGluIGFkdmFuY2Ug bGlrZSBpdCBkb2VzIGZvcg0KPiA+ID4gU01NVXM/DQo+ID4NCj4gPiBIbW1tLi4gU29ycnksIG5v dCBjbGVhciB0byBtZS4gWW91IG1lYW4gdG8gc2F5IGFzc29jaWF0ZSB0aGUgSU9SVCBub2RlDQo+ ID4gd2l0aCBwbGF0Zm9ybSBkZXZpY2UgYW5kIHJldHJpZXZlIGl0IGluIGRyaXZlciBqdXN0IGxp a2Ugc21tdSBkb2VzIGZvcg0KPiA+ICJtb2RlbCIgY2hlY2tzPyBOb3Qgc3VyZSB0aGF0IHdvcmtz IGhlcmUgaWYgdGhhdOKAmXMgd2hhdCB0aGUgYWJvdmUgbWVhbnQuDQo+ID4NCj4gPiA+ID4gICAj ZGVmaW5lIHRvX3NtbXVfcG11KHApIChjb250YWluZXJfb2YocCwgc3RydWN0IHNtbXVfcG11LCBw bXUpKQ0KPiA+ID4gPg0KPiA+ID4gPiAgICNkZWZpbmUgU01NVV9QTVVfRVZFTlRfQVRUUl9FWFRS QUNUT1IoX25hbWUsIF9jb25maWcsIF9zdGFydCwNCj4gPiA+IF9lbmQpICAgICAgICBcDQo+ID4g PiA+IEBAIC0yMjQsMTUgKzI3MSwyMCBAQCBzdGF0aWMgdm9pZCBzbW11X3BtdV9zZXRfcGVyaW9k KHN0cnVjdA0KPiA+ID4gc21tdV9wbXUgKnNtbXVfcG11LA0KPiA+ID4gPiAgIAl1MzIgaWR4ID0g aHdjLT5pZHg7DQo+ID4gPiA+ICAgCXU2NCBuZXc7DQo+ID4gPiA+DQo+ID4gPiA+IC0JLyoNCj4g PiA+ID4gLQkgKiBXZSBsaW1pdCB0aGUgbWF4IHBlcmlvZCB0byBoYWxmIHRoZSBtYXggY291bnRl ciB2YWx1ZSBvZiB0aGUNCj4gPiA+IGNvdW50ZXINCj4gPiA+ID4gLQkgKiBzaXplLCBzbyB0aGF0 IGV2ZW4gaW4gdGhlIGNhc2Ugb2YgZXh0cmVtZSBpbnRlcnJ1cHQgbGF0ZW5jeSB0aGUNCj4gPiA+ ID4gLQkgKiBjb3VudGVyIHdpbGwgKGhvcGVmdWxseSkgbm90IHdyYXAgcGFzdCBpdHMgaW5pdGlh bCB2YWx1ZS4NCj4gPiA+ID4gLQkgKi8NCj4gPiA+ID4gLQluZXcgPSBzbW11X3BtdS0+Y291bnRl cl9tYXNrID4+IDE7DQo+ID4gPiA+ICsJaWYgKHNtbXVfcG11LT5vcHRpb25zICYgU01NVV9QTVVf T1BUX0VWQ05UUl9SRE9OTFkpIHsNCj4gPiA+ID4gKwkJbmV3ID0gc21tdV9wbXVfY291bnRlcl9n ZXRfdmFsdWUoc21tdV9wbXUsIGlkeCk7DQo+ID4gPg0KPiA+ID4gU29tZXRoaW5nJ3MgY2xlYXJs eSBtaXNzaW5nLCBiZWNhdXNlIGlmIHRoaXMgaGFwcGVucyB0byBzdGFydCBhdCAwLCB0aGUNCj4g PiA+IGN1cnJlbnQgb3ZlcmZsb3cgaGFuZGxpbmcgY29kZSBjYW5ub3QgcG9zc2libHkgZ2l2ZSB0 aGUgY29ycmVjdCBjb3VudC4NCj4gPiA+IE11Y2ggYXMgSSBoYXRlIHRoZSByZXNldC10by1oYWxm LXBlcmlvZCBpZGlvbSBmb3IgYmVpbmcgaW1wb3NzaWJsZSB0bw0KPiA+ID4gbWFrZSBzZW5zZSBv ZiwgaXQgZG9lcyBtYWtlIHZhcmlvdXMgYXNwZWN0cyBhcHBlYXIgYSBsb3Qgc2ltcGxlciB0aGFu DQo+ID4gPiB0aGV5IHJlYWxseSBhcmUuIFdhaXQsIG1heWJlIHRoYXQncyB5ZXQgYW5vdGhlciBy ZWFzb24gdG8gaGF0ZSBpdC4uLg0KPiA+DQo+ID4gWWVzLCAgaWYgdGhlIGNvdW50ZXIgc3RhcnRz IGF0IDAgYW5kIG92ZXJmbG93IGhhcHBlbnMsIGl0IHdvbid0IHBvc3NpYmx5IGdpdmUNCj4gPiB0 aGUgY29ycmVjdCBjb3VudCBjb21wYXJlZCB0byB0aGUgcmVzZXQtdG8taGFsZi1wZXJpb2QgbG9n aWMuIFNpbmNlIHRoaXMgaXMgYQ0KPiA+IDY0IGJpdCBjb3VudGVyLCBqdXN0IGhvcGUgdGhhdCwg aXQgd29uJ3QgbmVjZXNzYXJpbHkgaGFwcGVuIHRoYXQgb2Z0ZW4uDQo+IA0KPiBbLi4uXQ0KPiAN Cj4gPiA+ID4gK3N0YXRpYyB2b2lkIHNtbXVfcG11X2VuYWJsZV9lcnJhdGEoc3RydWN0IHNtbXVf cG11ICpzbW11X3BtdSwNCj4gPiA+ID4gKwkJCQllbnVtIHNtbXVfcG11X2VycmF0dW1fbWF0Y2hf dHlwZSB0eXBlLA0KPiA+ID4gPiArCQkJCXNlX21hdGNoX2ZuX3QgbWF0Y2hfZm4sDQo+ID4gPiA+ ICsJCQkJdm9pZCAqYXJnKQ0KPiA+ID4gPiArew0KPiA+ID4gPiArCWNvbnN0IHN0cnVjdCBzbW11 X3BtdV9lcnJhdHVtX3dhICp3YSA9IHNtbXVfcG11X3dhOw0KPiA+ID4gPiArDQo+ID4gPiA+ICsJ Zm9yICg7IHdhLT5kZXNjX3N0cjsgd2ErKykgew0KPiA+ID4gPiArCQlpZiAod2EtPm1hdGNoX3R5 cGUgIT0gdHlwZSkNCj4gPiA+ID4gKwkJCWNvbnRpbnVlOw0KPiA+ID4gPiArDQo+ID4gPiA+ICsJ CWlmIChtYXRjaF9mbih3YSwgYXJnKSkgew0KPiA+ID4gPiArCQkJaWYgKHdhLT5lbmFibGUpIHsN Cj4gPiA+ID4gKwkJCQl3YS0+ZW5hYmxlKHNtbXVfcG11KTsNCj4gPiA+ID4gKwkJCQlkZXZfaW5m byhzbW11X3BtdS0+ZGV2LA0KPiA+ID4gPiArCQkJCQkiRW5hYmxpbmcgd29ya2Fyb3VuZCBmb3Ig JXNcbiIsDQo+ID4gPiA+ICsJCQkJCSB3YS0+ZGVzY19zdHIpOw0KPiA+ID4gPiArCQkJfQ0KPiA+ ID4NCj4gPiA+IEp1c3QgaG93IG1hbnkga2luZHMgb2YgYnJva2VuIGFyZSB3ZSBleHBlY3Rpbmcg aGVyZT8gSXMgdGhpcyBsaWZ0ZWQgZnJvbQ0KPiA+ID4gdGhlIGFybTY0IGNwdWZlYXR1cmUgZnJh bWV3b3JrLCBiZWNhdXNlIGl0IHNlZW1zIGxpa2UgYWJzb2x1dGUgb3ZlcmtpbGwNCj4gPiA+IGZv ciBhIHNpbXBsZSBQTVUgZHJpdmVyIHdoaWNoIGluIGFsbCByZWFsaXR5IGlzIG9ubHkgZXZlciBn b2luZyB0bw0KPiA+ID4gd2lnZ2xlIGEgZmV3IGZsYWdzIGluIHNvbWUgZGF0YSBzdHJ1Y3R1cmUu DQo+ID4NCj4gPiBZZXMsIHRoaXMgZXJyYXR1bSBmcmFtZXdvcmsgaXMgYmFzZWQgb24gdGhlIGFy bV9hcmNoX3RpbWVyIGNvZGUuIEFncmVlDQo+IHRoYXQNCj4gPiB0aGlzIGlzIGFuIG92ZXJraWxs IGlmIGl0IGlzIGp1c3QgdG8gc3VwcG9ydCB0aGlzIGhhcmR3YXJlLiBJIGFtIG5vdCBzdXJlIHRo aXMgY2FuDQo+IGJlDQo+ID4gZXh0ZW5kZWQgdG8gYWRkIHRoZSBJTVBMRU1FTlRBVElPTiBERUZJ TkVEIGV2ZW50cyBpbiBmdXR1cmUoSSBoYXZlbid0DQo+ID4gbG9va2VkIGludG8gdGhhdCBub3cp LiBJZiB0aGlzIGlzIG5vdCB0aGF0IHVzZWZ1bCBpbiB0aGUgbmVhciBmdXR1cmUsIEkgd2lsbCBy ZW1vdmUNCj4gPiB0aGUNCj4gPiBmcmFtZXdvcmsgcGFydCBhbmQgdXNlIHRoZSBPRU0gaW5mbyBk aXJlY3RseSB0byBzZXQgdGhlIGZsYWcuIFBsZWFzZSBsZXQgbWUNCj4gPiBrbm93DQo+ID4geW91 ciB0aG91Z2h0cy4uDQo+IA0KPiBCZWxvdyBpcyBhbm90aGVyIHRha2Ugb24gdGhpcyBwYXRjaC4g UGxlYXNlIGxldCBtZSBrbm93IGlmIHRoaXMgbWFrZXMgYW55DQo+IHNlbnNlLi4NCg0KQ291bGQg eW91IHBsZWFzZSBsZXQgbWUga25vdyB3aGV0aGVyIHRoZSBiZWxvdyAic2ltcGxpZmllZCIgdmVy c2lvbiBvZg0KZXJyYXR1bSBsb29rcyBhbnkgYmV0dGVyIG9yIG5vdD8gIEFuZCBhcHByZWNpYXRl IGFueSBvdGhlciBjb21tZW50cyBvbg0KdGhlIHJlc3Qgb2YgdGhlIHNlcmllcyBhcyB3ZWxsIHNv IHRoYXQgSSBjYW4gd29yayBvbiB0aGlzIGFuZCByZXNwaW4uDQoNClRoYW5rcywNClNoYW1lZXIN Cg0KPiBUaGFua3MsDQo+IFNoYW1lZXINCj4gDQo+IC0tLS04LS0tLQ0KPiBkaWZmIC0tZ2l0IGEv ZHJpdmVycy9wZXJmL2FybV9zbW11djNfcG11LmMNCj4gYi9kcml2ZXJzL3BlcmYvYXJtX3NtbXV2 M19wbXUuYw0KPiBpbmRleCBlZjk0YjkwLi42ZjgxYjk0IDEwMDY0NA0KPiAtLS0gYS9kcml2ZXJz L3BlcmYvYXJtX3NtbXV2M19wbXUuYw0KPiArKysgYi9kcml2ZXJzL3BlcmYvYXJtX3NtbXV2M19w bXUuYw0KPiBAQCAtOTYsNiArOTYsOCBAQA0KPiANCj4gICNkZWZpbmUgU01NVV9QQV9TSElGVCAg ICAgICAgICAgICAgICAgICAxMg0KPiANCj4gKyNkZWZpbmUgU01NVV9QTVVfT1BUX0VWQ05UUl9S RE9OTFkJKDEgPDwgMCkNCj4gKw0KPiAgc3RhdGljIGludCBjcHVocF9zdGF0ZV9udW07DQo+IA0K PiAgc3RydWN0IHNtbXVfcG11IHsNCj4gQEAgLTExMSwxMCArMTEzLDM4IEBAIHN0cnVjdCBzbW11 X3BtdSB7DQo+ICAJc3RydWN0IGRldmljZSAqZGV2Ow0KPiAgCXZvaWQgX19pb21lbSAqcmVnX2Jh c2U7DQo+ICAJdm9pZCBfX2lvbWVtICpyZWxvY19iYXNlOw0KPiArCXUzMiBvcHRpb25zOw0KPiAg CXU2NCBjb3VudGVyX3ByZXNlbnRfbWFzazsNCj4gIAl1NjQgY291bnRlcl9tYXNrOw0KPiAgfTsN Cj4gDQo+ICtzdHJ1Y3QgZXJyYXR1bV9hY3BpX29lbV9pbmZvIHsNCj4gKwljaGFyIG9lbV9pZFtB Q1BJX09FTV9JRF9TSVpFICsgMV07DQo+ICsJY2hhciBvZW1fdGFibGVfaWRbQUNQSV9PRU1fVEFC TEVfSURfU0laRSArIDFdOw0KPiArCXUzMiBvZW1fcmV2aXNpb247DQo+ICsJdm9pZCAoKmVuYWJs ZSkoc3RydWN0IHNtbXVfcG11ICpzbW11X3BtdSk7DQo+ICt9Ow0KPiArDQo+ICt2b2lkIGhpc2lf ZXJyYXR1bV9ldmNudHJfcmRvbmx5KHN0cnVjdCBzbW11X3BtdSAqc21tdV9wbXUpDQo+ICt7DQo+ ICsJc21tdV9wbXUtPm9wdGlvbnMgfD0gU01NVV9QTVVfT1BUX0VWQ05UUl9SRE9OTFk7DQo+ICsJ ZGV2X2luZm8oc21tdV9wbXUtPmRldiwgIkVuYWJsaW5nIEhpU2lsaWNvbiBlcnJhdHVtDQo+IDE2 MjAwMTgwMFxuIik7DQo+ICt9DQo+ICsNCj4gK3N0YXRpYyBzdHJ1Y3QgZXJyYXR1bV9hY3BpX29l bV9pbmZvIGFjcGlfb2VtX2luZm9bXSA9IHsNCj4gKwkvKg0KPiArCSAqIE5vdGUgdGhhdCB0cmFp bGluZyBzcGFjZXMgYXJlIHJlcXVpcmVkIHRvIHByb3Blcmx5IG1hdGNoDQo+ICsJICogdGhlIE9F TSB0YWJsZSBpbmZvcm1hdGlvbi4NCj4gKwkgKi8NCj4gKwl7DQo+ICsJCS5vZW1faWQgICAgICAg ICA9ICJISVNJICAiLA0KPiArCQkub2VtX3RhYmxlX2lkICAgPSAiSElQMDggICAiLA0KPiArCQku b2VtX3JldmlzaW9uICAgPSAwLA0KPiArCQkuZW5hYmxlID0gaGlzaV9lcnJhdHVtX2V2Y250cl9y ZG9ubHksDQo+ICsJfSwNCj4gKwl7IC8qIFNlbnRpbmVsIGluZGljYXRpbmcgdGhlIGVuZCBvZiB0 aGUgT0VNIGFycmF5ICovIH0sDQo+ICt9Ow0KPiArDQo+ICAjZGVmaW5lIHRvX3NtbXVfcG11KHAp IChjb250YWluZXJfb2YocCwgc3RydWN0IHNtbXVfcG11LCBwbXUpKQ0KPiANCj4gICNkZWZpbmUg U01NVV9QTVVfRVZFTlRfQVRUUl9FWFRSQUNUT1IoX25hbWUsIF9jb25maWcsIF9zdGFydCwgX2Vu ZCkNCj4gXA0KPiBAQCAtMjI0LDE1ICsyNTQsMjAgQEAgc3RhdGljIHZvaWQgc21tdV9wbXVfc2V0 X3BlcmlvZChzdHJ1Y3QNCj4gc21tdV9wbXUgKnNtbXVfcG11LA0KPiAgCXUzMiBpZHggPSBod2Mt PmlkeDsNCj4gIAl1NjQgbmV3Ow0KPiANCj4gLQkvKg0KPiAtCSAqIFdlIGxpbWl0IHRoZSBtYXgg cGVyaW9kIHRvIGhhbGYgdGhlIG1heCBjb3VudGVyIHZhbHVlIG9mIHRoZQ0KPiBjb3VudGVyDQo+ IC0JICogc2l6ZSwgc28gdGhhdCBldmVuIGluIHRoZSBjYXNlIG9mIGV4dHJlbWUgaW50ZXJydXB0 IGxhdGVuY3kgdGhlDQo+IC0JICogY291bnRlciB3aWxsIChob3BlZnVsbHkpIG5vdCB3cmFwIHBh c3QgaXRzIGluaXRpYWwgdmFsdWUuDQo+IC0JICovDQo+IC0JbmV3ID0gc21tdV9wbXUtPmNvdW50 ZXJfbWFzayA+PiAxOw0KPiArCWlmIChzbW11X3BtdS0+b3B0aW9ucyAmIFNNTVVfUE1VX09QVF9F VkNOVFJfUkRPTkxZKSB7DQo+ICsJCW5ldyA9IHNtbXVfcG11X2NvdW50ZXJfZ2V0X3ZhbHVlKHNt bXVfcG11LCBpZHgpOw0KPiArCX0gZWxzZSB7DQo+ICsJCS8qDQo+ICsJCSAqIFdlIGxpbWl0IHRo ZSBtYXggcGVyaW9kIHRvIGhhbGYgdGhlIG1heCBjb3VudGVyIHZhbHVlDQo+ICsJCSAqIG9mIHRo ZSBjb3VudGVyIHNpemUsIHNvIHRoYXQgZXZlbiBpbiB0aGUgY2FzZSBvZiBleHRyZW1lDQo+ICsJ CSAqIGludGVycnVwdCBsYXRlbmN5IHRoZSBjb3VudGVyIHdpbGwgKGhvcGVmdWxseSkgbm90IHdy YXANCj4gKwkJICogcGFzdCBpdHMgaW5pdGlhbCB2YWx1ZS4NCj4gKwkJICovDQo+ICsJCW5ldyA9 IHNtbXVfcG11LT5jb3VudGVyX21hc2sgPj4gMTsNCj4gKwkJc21tdV9wbXVfY291bnRlcl9zZXRf dmFsdWUoc21tdV9wbXUsIGlkeCwgbmV3KTsNCj4gKwl9DQo+IA0KPiAgCWxvY2FsNjRfc2V0KCZo d2MtPnByZXZfY291bnQsIG5ldyk7DQo+IC0Jc21tdV9wbXVfY291bnRlcl9zZXRfdmFsdWUoc21t dV9wbXUsIGlkeCwgbmV3KTsNCj4gIH0NCj4gDQo+ICBzdGF0aWMgdm9pZCBzbW11X3BtdV9nZXRf ZXZlbnRfZmlsdGVyKHN0cnVjdCBwZXJmX2V2ZW50ICpldmVudCwgdTMyICpzcGFuLA0KPiBAQCAt NjcwLDYgKzcwNSwyOCBAQCBzdGF0aWMgdm9pZCBzbW11X3BtdV9yZXNldChzdHJ1Y3Qgc21tdV9w bXUNCj4gKnNtbXVfcG11KQ0KPiAgCQkgICAgICAgc21tdV9wbXUtPnJlbG9jX2Jhc2UgKyBTTU1V X1BNQ0dfT1ZTQ0xSMCk7DQo+ICB9DQo+IA0KPiArc3RhdGljIHZvaWQgc21tdV9wbXVfY2hlY2tf YWNwaV93b3JrYXJvdW5kcyhzdHJ1Y3Qgc21tdV9wbXUNCj4gKnNtbXVfcG11KQ0KPiArew0KPiAr CXN0YXRpYyBjb25zdCBzdHJ1Y3QgZXJyYXR1bV9hY3BpX29lbV9pbmZvIGVtcHR5X29lbV9pbmZv ID0ge307DQo+ICsJY29uc3Qgc3RydWN0IGVycmF0dW1fYWNwaV9vZW1faW5mbyAqaW5mbyA9IGFj cGlfb2VtX2luZm87DQo+ICsJc3RydWN0IGFjcGlfdGFibGVfaGVhZGVyICpoZHI7DQo+ICsNCj4g KwlpZiAoQUNQSV9GQUlMVVJFKGFjcGlfZ2V0X3RhYmxlKEFDUElfU0lHX0lPUlQsIDAsICZoZHIp KSkgew0KPiArCQlkZXZfZXJyKHNtbXVfcG11LT5kZXYsICJmYWlsZWQgdG8gZ2V0IElPUlRcbiIp Ow0KPiArCQlyZXR1cm47DQo+ICsJfQ0KPiArDQo+ICsJLyogSXRlcmF0ZSBvdmVyIHRoZSBBQ1BJ IE9FTSBpbmZvIGFycmF5LCBsb29raW5nIGZvciBhIG1hdGNoICovDQo+ICsJd2hpbGUgKG1lbWNt cChpbmZvLCAmZW1wdHlfb2VtX2luZm8sIHNpemVvZigqaW5mbykpKSB7DQo+ICsJCWlmICghbWVt Y21wKGluZm8tPm9lbV9pZCwgaGRyLT5vZW1faWQsIEFDUElfT0VNX0lEX1NJWkUpDQo+ICYmDQo+ ICsJCSAgICAhbWVtY21wKGluZm8tPm9lbV90YWJsZV9pZCwgaGRyLT5vZW1fdGFibGVfaWQsDQo+ IEFDUElfT0VNX1RBQkxFX0lEX1NJWkUpICYmDQo+ICsJCQlpbmZvLT5vZW1fcmV2aXNpb24gPT0g aGRyLT5vZW1fcmV2aXNpb24pDQo+ICsJCQlpbmZvLT5lbmFibGUoc21tdV9wbXUpOw0KPiArDQo+ ICsJCWluZm8rKzsNCj4gKwl9DQo+ICt9DQo+ICsNCj4gIHN0YXRpYyBpbnQgc21tdV9wbXVfcHJv YmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRldikNCj4gIHsNCj4gIAlzdHJ1Y3Qgc21tdV9w bXUgKnNtbXVfcG11Ow0KPiBAQCAtNzQ5LDYgKzgwNiw4IEBAIHN0YXRpYyBpbnQgc21tdV9wbXVf cHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZQ0KPiAqcGRldikNCj4gIAkJcmV0dXJuIC1FSU5W QUw7DQo+ICAJfQ0KPiANCj4gKwlzbW11X3BtdV9jaGVja19hY3BpX3dvcmthcm91bmRzKHNtbXVf cG11KTsNCj4gKw0KPiAgCS8qIFBpY2sgb25lIENQVSB0byBiZSB0aGUgcHJlZmVycmVkIG9uZSB0 byB1c2UgKi8NCj4gIAlzbW11X3BtdS0+b25fY3B1ID0gZ2V0X2NwdSgpOw0KPiAgCVdBUk5fT04o aXJxX3NldF9hZmZpbml0eShzbW11X3BtdS0+aXJxLCBjcHVtYXNrX29mKHNtbXVfcG11LQ0KPiA+ b25fY3B1KSkpOw0KPiANCj4gX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19fX19f X19fX19fX18NCj4gTGludXhhcm0gbWFpbGluZyBsaXN0DQo+IExpbnV4YXJtQGh1YXdlaS5jb20N Cj4gaHR0cDovL2h1bGsuaHVhd2VpLmNvbS9tYWlsbWFuL2xpc3RpbmZvL2xpbnV4YXJtDQo= From mboxrd@z Thu Jan 1 00:00:00 1970 From: shameerali.kolothum.thodi@huawei.com (Shameerali Kolothum Thodi) Date: Fri, 9 Nov 2018 16:50:40 +0000 Subject: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk In-Reply-To: <5FC3163CFD30C246ABAA99954A238FA8387A0575@FRAEML521-MBX.china.huawei.com> References: <20181016124920.24708-1-shameerali.kolothum.thodi@huawei.com> <20181016124920.24708-5-shameerali.kolothum.thodi@huawei.com> <0d7a984e-5814-a986-cd48-ef0651079e32@arm.com> <5FC3163CFD30C246ABAA99954A238FA8387A0342@FRAEML521-MBX.china.huawei.com> <5FC3163CFD30C246ABAA99954A238FA8387A0575@FRAEML521-MBX.china.huawei.com> Message-ID: <5FC3163CFD30C246ABAA99954A238FA8387C64F2@FRAEML521-MBX.china.huawei.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi Robin, > -----Original Message----- > From: Linuxarm [mailto:linuxarm-bounces at huawei.com] On Behalf Of > Shameerali Kolothum Thodi > Sent: 18 October 2018 16:27 > To: Robin Murphy ; lorenzo.pieralisi at arm.com; > jean-philippe.brucker at arm.com > Cc: mark.rutland at arm.com; vkilari at codeaurora.org; > neil.m.leeder at gmail.com; pabba at codeaurora.org; will.deacon at arm.com; > rruigrok at codeaurora.org; Linuxarm ; linux- > acpi at vger.kernel.org; linux-arm-kernel at lists.infradead.org; linux- > kernel at vger.kernel.org > Subject: RE: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum > 162001800 quirk [...] > > > > > +static const struct smmu_pmu_erratum_wa smmu_pmu_wa[] = { > > > > + { > > > > + .match_type = se_match_acpi_oem, > > > > + .id = hisi_162001800_oem_info, > > > > + .desc_str = "HiSilicon erratum 162001800", > > > > + .enable = hisi_erratum_evcntr_rdonly, > > > > + }, > > > > +}; > > > > + > > > > > > There's an awful lot of raw ACPI internals splashed about here - > > > couldn't at least some of it be abstracted behind the IORT code? In > > > fact, can't IORT just set all this stuff up in advance like it does for > > > SMMUs? > > > > Hmmm.. Sorry, not clear to me. You mean to say associate the IORT node > > with platform device and retrieve it in driver just like smmu does for > > "model" checks? Not sure that works here if that?s what the above meant. > > > > > > #define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu)) > > > > > > > > #define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, > > > _end) \ > > > > @@ -224,15 +271,20 @@ static void smmu_pmu_set_period(struct > > > smmu_pmu *smmu_pmu, > > > > u32 idx = hwc->idx; > > > > u64 new; > > > > > > > > - /* > > > > - * We limit the max period to half the max counter value of the > > > counter > > > > - * size, so that even in the case of extreme interrupt latency the > > > > - * counter will (hopefully) not wrap past its initial value. > > > > - */ > > > > - new = smmu_pmu->counter_mask >> 1; > > > > + if (smmu_pmu->options & SMMU_PMU_OPT_EVCNTR_RDONLY) { > > > > + new = smmu_pmu_counter_get_value(smmu_pmu, idx); > > > > > > Something's clearly missing, because if this happens to start at 0, the > > > current overflow handling code cannot possibly give the correct count. > > > Much as I hate the reset-to-half-period idiom for being impossible to > > > make sense of, it does make various aspects appear a lot simpler than > > > they really are. Wait, maybe that's yet another reason to hate it... > > > > Yes, if the counter starts at 0 and overflow happens, it won't possibly give > > the correct count compared to the reset-to-half-period logic. Since this is a > > 64 bit counter, just hope that, it won't necessarily happen that often. > > [...] > > > > > +static void smmu_pmu_enable_errata(struct smmu_pmu *smmu_pmu, > > > > + enum smmu_pmu_erratum_match_type type, > > > > + se_match_fn_t match_fn, > > > > + void *arg) > > > > +{ > > > > + const struct smmu_pmu_erratum_wa *wa = smmu_pmu_wa; > > > > + > > > > + for (; wa->desc_str; wa++) { > > > > + if (wa->match_type != type) > > > > + continue; > > > > + > > > > + if (match_fn(wa, arg)) { > > > > + if (wa->enable) { > > > > + wa->enable(smmu_pmu); > > > > + dev_info(smmu_pmu->dev, > > > > + "Enabling workaround for %s\n", > > > > + wa->desc_str); > > > > + } > > > > > > Just how many kinds of broken are we expecting here? Is this lifted from > > > the arm64 cpufeature framework, because it seems like absolute overkill > > > for a simple PMU driver which in all reality is only ever going to > > > wiggle a few flags in some data structure. > > > > Yes, this erratum framework is based on the arm_arch_timer code. Agree > that > > this is an overkill if it is just to support this hardware. I am not sure this can > be > > extended to add the IMPLEMENTATION DEFINED events in future(I haven't > > looked into that now). If this is not that useful in the near future, I will remove > > the > > framework part and use the OEM info directly to set the flag. Please let me > > know > > your thoughts.. > > Below is another take on this patch. Please let me know if this makes any > sense.. Could you please let me know whether the below "simplified" version of erratum looks any better or not? And appreciate any other comments on the rest of the series as well so that I can work on this and respin. Thanks, Shameer > Thanks, > Shameer > > ----8---- > diff --git a/drivers/perf/arm_smmuv3_pmu.c > b/drivers/perf/arm_smmuv3_pmu.c > index ef94b90..6f81b94 100644 > --- a/drivers/perf/arm_smmuv3_pmu.c > +++ b/drivers/perf/arm_smmuv3_pmu.c > @@ -96,6 +96,8 @@ > > #define SMMU_PA_SHIFT 12 > > +#define SMMU_PMU_OPT_EVCNTR_RDONLY (1 << 0) > + > static int cpuhp_state_num; > > struct smmu_pmu { > @@ -111,10 +113,38 @@ struct smmu_pmu { > struct device *dev; > void __iomem *reg_base; > void __iomem *reloc_base; > + u32 options; > u64 counter_present_mask; > u64 counter_mask; > }; > > +struct erratum_acpi_oem_info { > + char oem_id[ACPI_OEM_ID_SIZE + 1]; > + char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; > + u32 oem_revision; > + void (*enable)(struct smmu_pmu *smmu_pmu); > +}; > + > +void hisi_erratum_evcntr_rdonly(struct smmu_pmu *smmu_pmu) > +{ > + smmu_pmu->options |= SMMU_PMU_OPT_EVCNTR_RDONLY; > + dev_info(smmu_pmu->dev, "Enabling HiSilicon erratum > 162001800\n"); > +} > + > +static struct erratum_acpi_oem_info acpi_oem_info[] = { > + /* > + * Note that trailing spaces are required to properly match > + * the OEM table information. > + */ > + { > + .oem_id = "HISI ", > + .oem_table_id = "HIP08 ", > + .oem_revision = 0, > + .enable = hisi_erratum_evcntr_rdonly, > + }, > + { /* Sentinel indicating the end of the OEM array */ }, > +}; > + > #define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu)) > > #define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, _end) > \ > @@ -224,15 +254,20 @@ static void smmu_pmu_set_period(struct > smmu_pmu *smmu_pmu, > u32 idx = hwc->idx; > u64 new; > > - /* > - * We limit the max period to half the max counter value of the > counter > - * size, so that even in the case of extreme interrupt latency the > - * counter will (hopefully) not wrap past its initial value. > - */ > - new = smmu_pmu->counter_mask >> 1; > + if (smmu_pmu->options & SMMU_PMU_OPT_EVCNTR_RDONLY) { > + new = smmu_pmu_counter_get_value(smmu_pmu, idx); > + } else { > + /* > + * We limit the max period to half the max counter value > + * of the counter size, so that even in the case of extreme > + * interrupt latency the counter will (hopefully) not wrap > + * past its initial value. > + */ > + new = smmu_pmu->counter_mask >> 1; > + smmu_pmu_counter_set_value(smmu_pmu, idx, new); > + } > > local64_set(&hwc->prev_count, new); > - smmu_pmu_counter_set_value(smmu_pmu, idx, new); > } > > static void smmu_pmu_get_event_filter(struct perf_event *event, u32 *span, > @@ -670,6 +705,28 @@ static void smmu_pmu_reset(struct smmu_pmu > *smmu_pmu) > smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0); > } > > +static void smmu_pmu_check_acpi_workarounds(struct smmu_pmu > *smmu_pmu) > +{ > + static const struct erratum_acpi_oem_info empty_oem_info = {}; > + const struct erratum_acpi_oem_info *info = acpi_oem_info; > + struct acpi_table_header *hdr; > + > + if (ACPI_FAILURE(acpi_get_table(ACPI_SIG_IORT, 0, &hdr))) { > + dev_err(smmu_pmu->dev, "failed to get IORT\n"); > + return; > + } > + > + /* Iterate over the ACPI OEM info array, looking for a match */ > + while (memcmp(info, &empty_oem_info, sizeof(*info))) { > + if (!memcmp(info->oem_id, hdr->oem_id, ACPI_OEM_ID_SIZE) > && > + !memcmp(info->oem_table_id, hdr->oem_table_id, > ACPI_OEM_TABLE_ID_SIZE) && > + info->oem_revision == hdr->oem_revision) > + info->enable(smmu_pmu); > + > + info++; > + } > +} > + > static int smmu_pmu_probe(struct platform_device *pdev) > { > struct smmu_pmu *smmu_pmu; > @@ -749,6 +806,8 @@ static int smmu_pmu_probe(struct platform_device > *pdev) > return -EINVAL; > } > > + smmu_pmu_check_acpi_workarounds(smmu_pmu); > + > /* Pick one CPU to be the preferred one to use */ > smmu_pmu->on_cpu = get_cpu(); > WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu- > >on_cpu))); > > _______________________________________________ > Linuxarm mailing list > Linuxarm at huawei.com > http://hulk.huawei.com/mailman/listinfo/linuxarm