From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shameerali Kolothum Thodi Subject: RE: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk Date: Tue, 27 Nov 2018 13:23:16 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA83885EDA7@FRAEML521-MBB.china.huawei.com> References: <20181016124920.24708-1-shameerali.kolothum.thodi@huawei.com> <20181016124920.24708-5-shameerali.kolothum.thodi@huawei.com> <0d7a984e-5814-a986-cd48-ef0651079e32@arm.com> <5FC3163CFD30C246ABAA99954A238FA8387A0342@FRAEML521-MBX.china.huawei.com> <5FC3163CFD30C246ABAA99954A238FA8387A0575@FRAEML521-MBX.china.huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 Return-path: In-Reply-To: Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Robin Murphy , "lorenzo.pieralisi@arm.com" , "jean-philippe.brucker@arm.com" Cc: "mark.rutland@arm.com" , "vkilari@codeaurora.org" , "neil.m.leeder@gmail.com" , "pabba@codeaurora.org" , "will.deacon@arm.com" , "rruigrok@codeaurora.org" , Linuxarm , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" List-Id: linux-acpi@vger.kernel.org DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogUm9iaW4gTXVycGh5IFtt YWlsdG86cm9iaW4ubXVycGh5QGFybS5jb21dDQo+IFNlbnQ6IDI2IE5vdmVtYmVyIDIwMTggMTg6 NDUNCj4gVG86IFNoYW1lZXJhbGkgS29sb3RodW0gVGhvZGkgPHNoYW1lZXJhbGkua29sb3RodW0u dGhvZGlAaHVhd2VpLmNvbT47DQo+IGxvcmVuem8ucGllcmFsaXNpQGFybS5jb207IGplYW4tcGhp bGlwcGUuYnJ1Y2tlckBhcm0uY29tDQo+IENjOiBtYXJrLnJ1dGxhbmRAYXJtLmNvbTsgdmtpbGFy aUBjb2RlYXVyb3JhLm9yZzsNCj4gbmVpbC5tLmxlZWRlckBnbWFpbC5jb207IHBhYmJhQGNvZGVh dXJvcmEub3JnOyB3aWxsLmRlYWNvbkBhcm0uY29tOw0KPiBycnVpZ3Jva0Bjb2RlYXVyb3JhLm9y ZzsgTGludXhhcm0gPGxpbnV4YXJtQGh1YXdlaS5jb20+OyBsaW51eC0NCj4ga2VybmVsQHZnZXIu a2VybmVsLm9yZzsgbGludXgtYWNwaUB2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4LWFybS0NCj4ga2Vy bmVsQGxpc3RzLmluZnJhZGVhZC5vcmcNCj4gU3ViamVjdDogUmU6IFtQQVRDSCB2NCA0LzRdIHBl cmYvc21tdXYzX3BtdTogRW5hYmxlIEhpU2lsaWNvbiBFcnJhdHVtDQo+IDE2MjAwMTgwMCBxdWly aw0KPiANCj4gSGkgU2hhbWVlciwNCj4gDQo+IFNvcnJ5IGZvciB0aGUgZGVsYXkuLi4NCj4gDQo+ IE9uIDE4LzEwLzIwMTggMTY6MjcsIFNoYW1lZXJhbGkgS29sb3RodW0gVGhvZGkgd3JvdGU6DQo+ ID4NCj4gPg0KPiA+PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+PiBGcm9tOiBMaW51 eGFybSBbbWFpbHRvOmxpbnV4YXJtLWJvdW5jZXNAaHVhd2VpLmNvbV0gT24gQmVoYWxmIE9mDQo+ ID4+IFNoYW1lZXJhbGkgS29sb3RodW0gVGhvZGkNCj4gPj4gU2VudDogMTggT2N0b2JlciAyMDE4 IDE0OjM0DQo+ID4+IFRvOiBSb2JpbiBNdXJwaHkgPHJvYmluLm11cnBoeUBhcm0uY29tPjsgbG9y ZW56by5waWVyYWxpc2lAYXJtLmNvbTsNCj4gPj4gamVhbi1waGlsaXBwZS5icnVja2VyQGFybS5j b20NCj4gPj4gQ2M6IG1hcmsucnV0bGFuZEBhcm0uY29tOyB2a2lsYXJpQGNvZGVhdXJvcmEub3Jn Ow0KPiA+PiBuZWlsLm0ubGVlZGVyQGdtYWlsLmNvbTsgcGFiYmFAY29kZWF1cm9yYS5vcmc7IHdp bGwuZGVhY29uQGFybS5jb207DQo+ID4+IHJydWlncm9rQGNvZGVhdXJvcmEub3JnOyBMaW51eGFy bSA8bGludXhhcm1AaHVhd2VpLmNvbT47IGxpbnV4LQ0KPiA+PiBrZXJuZWxAdmdlci5rZXJuZWwu b3JnOyBsaW51eC1hY3BpQHZnZXIua2VybmVsLm9yZzsgbGludXgtYXJtLQ0KPiA+PiBrZXJuZWxA bGlzdHMuaW5mcmFkZWFkLm9yZw0KPiA+PiBTdWJqZWN0OiBSRTogW1BBVENIIHY0IDQvNF0gcGVy Zi9zbW11djNfcG11OiBFbmFibGUgSGlTaWxpY29uIEVycmF0dW0NCj4gPj4gMTYyMDAxODAwIHF1 aXJrDQo+ID4+DQo+ID4+IEhpIFJvYmluLA0KPiA+Pg0KPiA+Pj4gLS0tLS1PcmlnaW5hbCBNZXNz YWdlLS0tLS0NCj4gPj4+IEZyb206IFJvYmluIE11cnBoeSBbbWFpbHRvOnJvYmluLm11cnBoeUBh cm0uY29tXQ0KPiA+Pj4gU2VudDogMTggT2N0b2JlciAyMDE4IDEyOjQ0DQo+ID4+PiBUbzogU2hh bWVlcmFsaSBLb2xvdGh1bSBUaG9kaQ0KPiA8c2hhbWVlcmFsaS5rb2xvdGh1bS50aG9kaUBodWF3 ZWkuY29tPjsNCj4gPj4+IGxvcmVuem8ucGllcmFsaXNpQGFybS5jb207IGplYW4tcGhpbGlwcGUu YnJ1Y2tlckBhcm0uY29tDQo+ID4+PiBDYzogd2lsbC5kZWFjb25AYXJtLmNvbTsgbWFyay5ydXRs YW5kQGFybS5jb207IEd1b2hhbmp1biAoSGFuanVuDQo+IEd1bykNCj4gPj4+IDxndW9oYW5qdW5A aHVhd2VpLmNvbT47IEpvaG4gR2FycnkgPGpvaG4uZ2FycnlAaHVhd2VpLmNvbT47DQo+ID4+PiBw YWJiYUBjb2RlYXVyb3JhLm9yZzsgdmtpbGFyaUBjb2RlYXVyb3JhLm9yZzsNCj4gcnJ1aWdyb2tA Y29kZWF1cm9yYS5vcmc7DQo+ID4+PiBsaW51eC1hY3BpQHZnZXIua2VybmVsLm9yZzsgbGludXgt a2VybmVsQHZnZXIua2VybmVsLm9yZzsgbGludXgtYXJtLQ0KPiA+Pj4ga2VybmVsQGxpc3RzLmlu ZnJhZGVhZC5vcmc7IExpbnV4YXJtIDxsaW51eGFybUBodWF3ZWkuY29tPjsNCj4gPj4+IG5laWwu bS5sZWVkZXJAZ21haWwuY29tDQo+ID4+PiBTdWJqZWN0OiBSZTogW1BBVENIIHY0IDQvNF0gcGVy Zi9zbW11djNfcG11OiBFbmFibGUgSGlTaWxpY29uIEVycmF0dW0NCj4gPj4+IDE2MjAwMTgwMCBx dWlyaw0KPiA+DQo+ID4gWy4uLl0NCj4gPg0KPiA+Pj4+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHNt bXVfcG11X2VycmF0dW1fd2Egc21tdV9wbXVfd2FbXSA9IHsNCj4gPj4+PiArCXsNCj4gPj4+PiAr CQkubWF0Y2hfdHlwZSA9IHNlX21hdGNoX2FjcGlfb2VtLA0KPiA+Pj4+ICsJCS5pZCA9IGhpc2lf MTYyMDAxODAwX29lbV9pbmZvLA0KPiA+Pj4+ICsJCS5kZXNjX3N0ciA9ICJIaVNpbGljb24gZXJy YXR1bSAxNjIwMDE4MDAiLA0KPiA+Pj4+ICsJCS5lbmFibGUgPSBoaXNpX2VycmF0dW1fZXZjbnRy X3Jkb25seSwNCj4gPj4+PiArCX0sDQo+ID4+Pj4gK307DQo+ID4+Pj4gKw0KPiA+Pj4NCj4gPj4+ IFRoZXJlJ3MgYW4gYXdmdWwgbG90IG9mIHJhdyBBQ1BJIGludGVybmFscyBzcGxhc2hlZCBhYm91 dCBoZXJlIC0NCj4gPj4+IGNvdWxkbid0IGF0IGxlYXN0IHNvbWUgb2YgaXQgYmUgYWJzdHJhY3Rl ZCBiZWhpbmQgdGhlIElPUlQgY29kZT8gSW4NCj4gPj4+IGZhY3QsIGNhbid0IElPUlQganVzdCBz ZXQgYWxsIHRoaXMgc3R1ZmYgdXAgaW4gYWR2YW5jZSBsaWtlIGl0IGRvZXMgZm9yDQo+ID4+PiBT TU1Vcz8NCj4gPj4NCj4gPj4gSG1tbS4uIFNvcnJ5LCBub3QgY2xlYXIgdG8gbWUuIFlvdSBtZWFu IHRvIHNheSBhc3NvY2lhdGUgdGhlIElPUlQgbm9kZQ0KPiA+PiB3aXRoIHBsYXRmb3JtIGRldmlj ZSBhbmQgcmV0cmlldmUgaXQgaW4gZHJpdmVyIGp1c3QgbGlrZSBzbW11IGRvZXMgZm9yDQo+ID4+ ICJtb2RlbCIgY2hlY2tzPyBOb3Qgc3VyZSB0aGF0IHdvcmtzIGhlcmUgaWYgdGhhdOKAmXMgd2hh dCB0aGUgYWJvdmUgbWVhbnQuDQo+IA0KPiBJIGRvbid0IHRoaW5rIHRoZXJlJ3MgbXVjaCBvZiBp bnRlcmVzdCBpbiB0aGUgYWN0dWFsIElPUlQgbm9kZSBpdHNlbGYsDQo+IGJ1dCBJIGNhbid0IHNl ZSB0aGF0IHRoZXJlIHdvdWxkIGJlIGFueSBwYXJ0aWN1bGFyIHByb2JsZW0gd2l0aCBwYXNzaW5n DQo+IGVpdGhlciBzb21lIGltcGxlbWVudGF0aW9uIGlkZW50aWZpZXIgb3IganVzdCBhIHJlYWR5 LW1hZGUgc2V0IG9mIHF1aXJrDQo+IGZsYWdzIHRvIHRoZSBQTUNHIGRyaXZlciB2aWEgcGxhdGRh dGEuDQoNCk9rLg0KDQo+ID4+Pj4gICAgI2RlZmluZSB0b19zbW11X3BtdShwKSAoY29udGFpbmVy X29mKHAsIHN0cnVjdCBzbW11X3BtdSwgcG11KSkNCj4gPj4+Pg0KPiA+Pj4+ICAgICNkZWZpbmUg U01NVV9QTVVfRVZFTlRfQVRUUl9FWFRSQUNUT1IoX25hbWUsIF9jb25maWcsDQo+IF9zdGFydCwN Cj4gPj4+IF9lbmQpICAgICAgICBcDQo+ID4+Pj4gQEAgLTIyNCwxNSArMjcxLDIwIEBAIHN0YXRp YyB2b2lkIHNtbXVfcG11X3NldF9wZXJpb2Qoc3RydWN0DQo+ID4+PiBzbW11X3BtdSAqc21tdV9w bXUsDQo+ID4+Pj4gICAgCXUzMiBpZHggPSBod2MtPmlkeDsNCj4gPj4+PiAgICAJdTY0IG5ldzsN Cj4gPj4+Pg0KPiA+Pj4+IC0JLyoNCj4gPj4+PiAtCSAqIFdlIGxpbWl0IHRoZSBtYXggcGVyaW9k IHRvIGhhbGYgdGhlIG1heCBjb3VudGVyIHZhbHVlIG9mIHRoZQ0KPiA+Pj4gY291bnRlcg0KPiA+ Pj4+IC0JICogc2l6ZSwgc28gdGhhdCBldmVuIGluIHRoZSBjYXNlIG9mIGV4dHJlbWUgaW50ZXJy dXB0IGxhdGVuY3kgdGhlDQo+ID4+Pj4gLQkgKiBjb3VudGVyIHdpbGwgKGhvcGVmdWxseSkgbm90 IHdyYXAgcGFzdCBpdHMgaW5pdGlhbCB2YWx1ZS4NCj4gPj4+PiAtCSAqLw0KPiA+Pj4+IC0JbmV3 ID0gc21tdV9wbXUtPmNvdW50ZXJfbWFzayA+PiAxOw0KPiA+Pj4+ICsJaWYgKHNtbXVfcG11LT5v cHRpb25zICYgU01NVV9QTVVfT1BUX0VWQ05UUl9SRE9OTFkpIHsNCj4gPj4+PiArCQluZXcgPSBz bW11X3BtdV9jb3VudGVyX2dldF92YWx1ZShzbW11X3BtdSwgaWR4KTsNCj4gPj4+DQo+ID4+PiBT b21ldGhpbmcncyBjbGVhcmx5IG1pc3NpbmcsIGJlY2F1c2UgaWYgdGhpcyBoYXBwZW5zIHRvIHN0 YXJ0IGF0IDAsIHRoZQ0KPiA+Pj4gY3VycmVudCBvdmVyZmxvdyBoYW5kbGluZyBjb2RlIGNhbm5v dCBwb3NzaWJseSBnaXZlIHRoZSBjb3JyZWN0IGNvdW50Lg0KPiA+Pj4gTXVjaCBhcyBJIGhhdGUg dGhlIHJlc2V0LXRvLWhhbGYtcGVyaW9kIGlkaW9tIGZvciBiZWluZyBpbXBvc3NpYmxlIHRvDQo+ ID4+PiBtYWtlIHNlbnNlIG9mLCBpdCBkb2VzIG1ha2UgdmFyaW91cyBhc3BlY3RzIGFwcGVhciBh IGxvdCBzaW1wbGVyIHRoYW4NCj4gPj4+IHRoZXkgcmVhbGx5IGFyZS4gV2FpdCwgbWF5YmUgdGhh dCdzIHlldCBhbm90aGVyIHJlYXNvbiB0byBoYXRlIGl0Li4uDQo+ID4+DQo+ID4+IFllcywgIGlm IHRoZSBjb3VudGVyIHN0YXJ0cyBhdCAwIGFuZCBvdmVyZmxvdyBoYXBwZW5zLCBpdCB3b24ndCBw b3NzaWJseSBnaXZlDQo+ID4+IHRoZSBjb3JyZWN0IGNvdW50IGNvbXBhcmVkIHRvIHRoZSByZXNl dC10by1oYWxmLXBlcmlvZCBsb2dpYy4gU2luY2UgdGhpcyBpcyBhDQo+ID4+IDY0IGJpdCBjb3Vu dGVyLCBqdXN0IGhvcGUgdGhhdCwgaXQgd29uJ3QgbmVjZXNzYXJpbHkgaGFwcGVuIHRoYXQgb2Z0 ZW4uDQo+IA0KPiBPSywgaWYgdGhlIGZ1bGwgNjQgY291bnRlciBiaXRzIGFyZSBpbXBsZW1lbnRl ZCwgdGhlbiBJIHN1cHBvc2Ugd2UncmUNCj4gcHJvYmFibHkgT0sgdG8gYXNzdW1lIG5vYm9keSdz IGdvaW5nIHRvIHJ1biBhIHNpbmdsZSBwcm9maWxpbmcgc2Vzc2lvbg0KPiBvdmVyIDQrIHllYXJz IG9yIHNvLiBJdCBtaWdodCBiZSB3b3J0aCBhIGNvbW1lbnQganVzdCB0byByZW1pbmQNCj4gb3Vy c2VsdmVzIHRoYXQgd2UncmUgKGN1cnJlbnRseSkgcmVseWluZyBvbiB0aGUgY291bnRlciBzaXpl IHRvIG1vc3RseQ0KPiBtaXRpZ2F0ZSBvdmVyZmxvdy1yZWxhdGVkIGlzc3VlcyBpbiB0aGlzIGNh c2UuDQoNClN1cmUsIEkgd2lsbCBhZGQgYSBjb21tZW50IHRvIG1ha2UgaXQgY2xlYXIuDQogDQo+ ID4NCj4gPiBbLi4uXQ0KPiA+DQo+ID4+Pj4gK3N0YXRpYyB2b2lkIHNtbXVfcG11X2VuYWJsZV9l cnJhdGEoc3RydWN0IHNtbXVfcG11ICpzbW11X3BtdSwNCj4gPj4+PiArCQkJCWVudW0gc21tdV9w bXVfZXJyYXR1bV9tYXRjaF90eXBlIHR5cGUsDQo+ID4+Pj4gKwkJCQlzZV9tYXRjaF9mbl90IG1h dGNoX2ZuLA0KPiA+Pj4+ICsJCQkJdm9pZCAqYXJnKQ0KPiA+Pj4+ICt7DQo+ID4+Pj4gKwljb25z dCBzdHJ1Y3Qgc21tdV9wbXVfZXJyYXR1bV93YSAqd2EgPSBzbW11X3BtdV93YTsNCj4gPj4+PiAr DQo+ID4+Pj4gKwlmb3IgKDsgd2EtPmRlc2Nfc3RyOyB3YSsrKSB7DQo+ID4+Pj4gKwkJaWYgKHdh LT5tYXRjaF90eXBlICE9IHR5cGUpDQo+ID4+Pj4gKwkJCWNvbnRpbnVlOw0KPiA+Pj4+ICsNCj4g Pj4+PiArCQlpZiAobWF0Y2hfZm4od2EsIGFyZykpIHsNCj4gPj4+PiArCQkJaWYgKHdhLT5lbmFi bGUpIHsNCj4gPj4+PiArCQkJCXdhLT5lbmFibGUoc21tdV9wbXUpOw0KPiA+Pj4+ICsJCQkJZGV2 X2luZm8oc21tdV9wbXUtPmRldiwNCj4gPj4+PiArCQkJCQkiRW5hYmxpbmcgd29ya2Fyb3VuZCBm b3IgJXNcbiIsDQo+ID4+Pj4gKwkJCQkJIHdhLT5kZXNjX3N0cik7DQo+ID4+Pj4gKwkJCX0NCj4g Pj4+DQo+ID4+PiBKdXN0IGhvdyBtYW55IGtpbmRzIG9mIGJyb2tlbiBhcmUgd2UgZXhwZWN0aW5n IGhlcmU/IElzIHRoaXMgbGlmdGVkIGZyb20NCj4gPj4+IHRoZSBhcm02NCBjcHVmZWF0dXJlIGZy YW1ld29yaywgYmVjYXVzZSBpdCBzZWVtcyBsaWtlIGFic29sdXRlIG92ZXJraWxsDQo+ID4+PiBm b3IgYSBzaW1wbGUgUE1VIGRyaXZlciB3aGljaCBpbiBhbGwgcmVhbGl0eSBpcyBvbmx5IGV2ZXIg Z29pbmcgdG8NCj4gPj4+IHdpZ2dsZSBhIGZldyBmbGFncyBpbiBzb21lIGRhdGEgc3RydWN0dXJl Lg0KPiA+Pg0KPiA+PiBZZXMsIHRoaXMgZXJyYXR1bSBmcmFtZXdvcmsgaXMgYmFzZWQgb24gdGhl IGFybV9hcmNoX3RpbWVyIGNvZGUuIEFncmVlDQo+IHRoYXQNCj4gPj4gdGhpcyBpcyBhbiBvdmVy a2lsbCBpZiBpdCBpcyBqdXN0IHRvIHN1cHBvcnQgdGhpcyBoYXJkd2FyZS4gSSBhbSBub3Qgc3Vy ZSB0aGlzIGNhbg0KPiBiZQ0KPiA+PiBleHRlbmRlZCB0byBhZGQgdGhlIElNUExFTUVOVEFUSU9O IERFRklORUQgZXZlbnRzIGluIGZ1dHVyZShJIGhhdmVuJ3QNCj4gPj4gbG9va2VkIGludG8gdGhh dCBub3cpLiBJZiB0aGlzIGlzIG5vdCB0aGF0IHVzZWZ1bCBpbiB0aGUgbmVhciBmdXR1cmUsIEkg d2lsbA0KPiByZW1vdmUNCj4gPj4gdGhlDQo+ID4+IGZyYW1ld29yayBwYXJ0IGFuZCB1c2UgdGhl IE9FTSBpbmZvIGRpcmVjdGx5IHRvIHNldCB0aGUgZmxhZy4gUGxlYXNlIGxldCBtZQ0KPiA+PiBr bm93DQo+ID4+IHlvdXIgdGhvdWdodHMuLg0KPiA+DQo+ID4gQmVsb3cgaXMgYW5vdGhlciB0YWtl IG9uIHRoaXMgcGF0Y2guIFBsZWFzZSBsZXQgbWUga25vdyBpZiB0aGlzIG1ha2VzIGFueQ0KPiBz ZW5zZS4uDQo+ID4NCj4gPiBUaGFua3MsDQo+ID4gU2hhbWVlcg0KPiA+DQo+ID4gLS0tLTgtLS0t DQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGVyZi9hcm1fc21tdXYzX3BtdS5jDQo+IGIvZHJp dmVycy9wZXJmL2FybV9zbW11djNfcG11LmMNCj4gPiBpbmRleCBlZjk0YjkwLi42ZjgxYjk0IDEw MDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvcGVyZi9hcm1fc21tdXYzX3BtdS5jDQo+ID4gKysrIGIv ZHJpdmVycy9wZXJmL2FybV9zbW11djNfcG11LmMNCj4gPiBAQCAtOTYsNiArOTYsOCBAQA0KPiA+ DQo+ID4gICAjZGVmaW5lIFNNTVVfUEFfU0hJRlQgICAgICAgICAgICAgICAgICAgMTINCj4gPg0K PiA+ICsjZGVmaW5lIFNNTVVfUE1VX09QVF9FVkNOVFJfUkRPTkxZCSgxIDw8IDApDQo+ID4gKw0K PiA+ICAgc3RhdGljIGludCBjcHVocF9zdGF0ZV9udW07DQo+ID4NCj4gPiAgIHN0cnVjdCBzbW11 X3BtdSB7DQo+ID4gQEAgLTExMSwxMCArMTEzLDM4IEBAIHN0cnVjdCBzbW11X3BtdSB7DQo+ID4g ICAJc3RydWN0IGRldmljZSAqZGV2Ow0KPiA+ICAgCXZvaWQgX19pb21lbSAqcmVnX2Jhc2U7DQo+ ID4gICAJdm9pZCBfX2lvbWVtICpyZWxvY19iYXNlOw0KPiA+ICsJdTMyIG9wdGlvbnM7DQo+ID4g ICAJdTY0IGNvdW50ZXJfcHJlc2VudF9tYXNrOw0KPiA+ICAgCXU2NCBjb3VudGVyX21hc2s7DQo+ ID4gICB9Ow0KPiA+DQo+ID4gK3N0cnVjdCBlcnJhdHVtX2FjcGlfb2VtX2luZm8gew0KPiA+ICsJ Y2hhciBvZW1faWRbQUNQSV9PRU1fSURfU0laRSArIDFdOw0KPiA+ICsJY2hhciBvZW1fdGFibGVf aWRbQUNQSV9PRU1fVEFCTEVfSURfU0laRSArIDFdOw0KPiA+ICsJdTMyIG9lbV9yZXZpc2lvbjsN Cj4gPiArCXZvaWQgKCplbmFibGUpKHN0cnVjdCBzbW11X3BtdSAqc21tdV9wbXUpOw0KPiA+ICt9 Ow0KPiA+ICsNCj4gPiArdm9pZCBoaXNpX2VycmF0dW1fZXZjbnRyX3Jkb25seShzdHJ1Y3Qgc21t dV9wbXUgKnNtbXVfcG11KQ0KPiA+ICt7DQo+ID4gKwlzbW11X3BtdS0+b3B0aW9ucyB8PSBTTU1V X1BNVV9PUFRfRVZDTlRSX1JET05MWTsNCj4gPiArCWRldl9pbmZvKHNtbXVfcG11LT5kZXYsICJF bmFibGluZyBIaVNpbGljb24gZXJyYXR1bQ0KPiAxNjIwMDE4MDBcbiIpOw0KPiA+ICt9DQo+ID4g Kw0KPiA+ICtzdGF0aWMgc3RydWN0IGVycmF0dW1fYWNwaV9vZW1faW5mbyBhY3BpX29lbV9pbmZv W10gPSB7DQo+ID4gKwkvKg0KPiA+ICsJICogTm90ZSB0aGF0IHRyYWlsaW5nIHNwYWNlcyBhcmUg cmVxdWlyZWQgdG8gcHJvcGVybHkgbWF0Y2gNCj4gPiArCSAqIHRoZSBPRU0gdGFibGUgaW5mb3Jt YXRpb24uDQo+ID4gKwkgKi8NCj4gPiArCXsNCj4gPiArCQkub2VtX2lkICAgICAgICAgPSAiSElT SSAgIiwNCj4gPiArCQkub2VtX3RhYmxlX2lkICAgPSAiSElQMDggICAiLA0KPiA+ICsJCS5vZW1f cmV2aXNpb24gICA9IDAsDQo+ID4gKwkJLmVuYWJsZSA9IGhpc2lfZXJyYXR1bV9ldmNudHJfcmRv bmx5LA0KPiA+ICsJfSwNCj4gPiArCXsgLyogU2VudGluZWwgaW5kaWNhdGluZyB0aGUgZW5kIG9m IHRoZSBPRU0gYXJyYXkgKi8gfSwNCj4gPiArfTsNCj4gPiArDQo+ID4gICAjZGVmaW5lIHRvX3Nt bXVfcG11KHApIChjb250YWluZXJfb2YocCwgc3RydWN0IHNtbXVfcG11LCBwbXUpKQ0KPiA+DQo+ ID4gICAjZGVmaW5lIFNNTVVfUE1VX0VWRU5UX0FUVFJfRVhUUkFDVE9SKF9uYW1lLCBfY29uZmln LCBfc3RhcnQsDQo+IF9lbmQpICAgICAgICBcDQo+ID4gQEAgLTIyNCwxNSArMjU0LDIwIEBAIHN0 YXRpYyB2b2lkIHNtbXVfcG11X3NldF9wZXJpb2Qoc3RydWN0DQo+IHNtbXVfcG11ICpzbW11X3Bt dSwNCj4gPiAgIAl1MzIgaWR4ID0gaHdjLT5pZHg7DQo+ID4gICAJdTY0IG5ldzsNCj4gPg0KPiA+ IC0JLyoNCj4gPiAtCSAqIFdlIGxpbWl0IHRoZSBtYXggcGVyaW9kIHRvIGhhbGYgdGhlIG1heCBj b3VudGVyIHZhbHVlIG9mIHRoZQ0KPiBjb3VudGVyDQo+ID4gLQkgKiBzaXplLCBzbyB0aGF0IGV2 ZW4gaW4gdGhlIGNhc2Ugb2YgZXh0cmVtZSBpbnRlcnJ1cHQgbGF0ZW5jeSB0aGUNCj4gPiAtCSAq IGNvdW50ZXIgd2lsbCAoaG9wZWZ1bGx5KSBub3Qgd3JhcCBwYXN0IGl0cyBpbml0aWFsIHZhbHVl Lg0KPiA+IC0JICovDQo+ID4gLQluZXcgPSBzbW11X3BtdS0+Y291bnRlcl9tYXNrID4+IDE7DQo+ ID4gKwlpZiAoc21tdV9wbXUtPm9wdGlvbnMgJiBTTU1VX1BNVV9PUFRfRVZDTlRSX1JET05MWSkg ew0KPiA+ICsJCW5ldyA9IHNtbXVfcG11X2NvdW50ZXJfZ2V0X3ZhbHVlKHNtbXVfcG11LCBpZHgp Ow0KPiA+ICsJfSBlbHNlIHsNCj4gPiArCQkvKg0KPiA+ICsJCSAqIFdlIGxpbWl0IHRoZSBtYXgg cGVyaW9kIHRvIGhhbGYgdGhlIG1heCBjb3VudGVyIHZhbHVlDQo+ID4gKwkJICogb2YgdGhlIGNv dW50ZXIgc2l6ZSwgc28gdGhhdCBldmVuIGluIHRoZSBjYXNlIG9mIGV4dHJlbWUNCj4gPiArCQkg KiBpbnRlcnJ1cHQgbGF0ZW5jeSB0aGUgY291bnRlciB3aWxsIChob3BlZnVsbHkpIG5vdCB3cmFw DQo+ID4gKwkJICogcGFzdCBpdHMgaW5pdGlhbCB2YWx1ZS4NCj4gPiArCQkgKi8NCj4gPiArCQlu ZXcgPSBzbW11X3BtdS0+Y291bnRlcl9tYXNrID4+IDE7DQo+ID4gKwkJc21tdV9wbXVfY291bnRl cl9zZXRfdmFsdWUoc21tdV9wbXUsIGlkeCwgbmV3KTsNCj4gPiArCX0NCj4gPg0KPiA+ICAgCWxv Y2FsNjRfc2V0KCZod2MtPnByZXZfY291bnQsIG5ldyk7DQo+ID4gLQlzbW11X3BtdV9jb3VudGVy X3NldF92YWx1ZShzbW11X3BtdSwgaWR4LCBuZXcpOw0KPiA+ICAgfQ0KPiA+DQo+ID4gICBzdGF0 aWMgdm9pZCBzbW11X3BtdV9nZXRfZXZlbnRfZmlsdGVyKHN0cnVjdCBwZXJmX2V2ZW50ICpldmVu dCwgdTMyDQo+ICpzcGFuLA0KPiA+IEBAIC02NzAsNiArNzA1LDI4IEBAIHN0YXRpYyB2b2lkIHNt bXVfcG11X3Jlc2V0KHN0cnVjdCBzbW11X3BtdQ0KPiAqc21tdV9wbXUpDQo+ID4gICAJCSAgICAg ICBzbW11X3BtdS0+cmVsb2NfYmFzZSArIFNNTVVfUE1DR19PVlNDTFIwKTsNCj4gPiAgIH0NCj4g Pg0KPiA+ICtzdGF0aWMgdm9pZCBzbW11X3BtdV9jaGVja19hY3BpX3dvcmthcm91bmRzKHN0cnVj dCBzbW11X3BtdQ0KPiAqc21tdV9wbXUpDQo+ID4gK3sNCj4gPiArCXN0YXRpYyBjb25zdCBzdHJ1 Y3QgZXJyYXR1bV9hY3BpX29lbV9pbmZvIGVtcHR5X29lbV9pbmZvID0ge307DQo+ID4gKwljb25z dCBzdHJ1Y3QgZXJyYXR1bV9hY3BpX29lbV9pbmZvICppbmZvID0gYWNwaV9vZW1faW5mbzsNCj4g PiArCXN0cnVjdCBhY3BpX3RhYmxlX2hlYWRlciAqaGRyOw0KPiA+ICsNCj4gPiArCWlmIChBQ1BJ X0ZBSUxVUkUoYWNwaV9nZXRfdGFibGUoQUNQSV9TSUdfSU9SVCwgMCwgJmhkcikpKSB7DQo+ID4g KwkJZGV2X2VycihzbW11X3BtdS0+ZGV2LCAiZmFpbGVkIHRvIGdldCBJT1JUXG4iKTsNCj4gPiAr CQlyZXR1cm47DQo+ID4gKwl9DQo+ID4gKw0KPiA+ICsJLyogSXRlcmF0ZSBvdmVyIHRoZSBBQ1BJ IE9FTSBpbmZvIGFycmF5LCBsb29raW5nIGZvciBhIG1hdGNoICovDQo+ID4gKwl3aGlsZSAobWVt Y21wKGluZm8sICZlbXB0eV9vZW1faW5mbywgc2l6ZW9mKCppbmZvKSkpIHsNCj4gPiArCQlpZiAo IW1lbWNtcChpbmZvLT5vZW1faWQsIGhkci0+b2VtX2lkLCBBQ1BJX09FTV9JRF9TSVpFKQ0KPiAm Jg0KPiA+ICsJCSAgICAhbWVtY21wKGluZm8tPm9lbV90YWJsZV9pZCwgaGRyLT5vZW1fdGFibGVf aWQsDQo+IEFDUElfT0VNX1RBQkxFX0lEX1NJWkUpICYmDQo+ID4gKwkJCWluZm8tPm9lbV9yZXZp c2lvbiA9PSBoZHItPm9lbV9yZXZpc2lvbikNCj4gPiArCQkJaW5mby0+ZW5hYmxlKHNtbXVfcG11 KTsNCj4gPiArDQo+ID4gKwkJaW5mbysrOw0KPiA+ICsJfQ0KPiA+ICt9DQo+IA0KPiBGV0lXLCB0 aGlzIGxvb2tzIGF3ZnVsbHkgbGlrZSBhY3BpX21hdGNoX3BsYXRmb3JtX2xpc3QoKS4uLg0KPiAN Cj4gSG93ZXZlciwgSSBzdGlsbCB0aGluayB0aGF0IGFueSBwYXJzaW5nIG9mIElPUlQgZmllbGRz IGJlbG9uZ3MgaW4NCj4gaW9ydC5jLCBub3QgaW4gZXZlcnkgZHJpdmVyIHdoaWNoIG1pZ2h0IGV2 ZXIgbmVlZCB0byBkZXRlY3QgYSBxdWlyay4gRm9yDQo+IHN0YXJ0ZXJzLCB0aGF0IGNvZGUgaGFz IGlvcnRfdGFibGUgdG8gaGFuZCwgZnVsbCBrbm93bGVkZ2Ugb2YgYWxsIHRoZQ0KPiBvdGhlciBp ZGVudGlmaWFibGUgY29tcG9uZW50cywgYW5kIGEgYWxyZWFkeSBjb250YWlucyBhIGJ1bmNoIG9m DQo+IHN5c3RlbS1zcGVjaWZpYyBxdWlyayBkZXRlY3Rpb24gd2hpY2ggY291bGQgcG90ZW50aWFs bHkgYmUgc2hhcmVkLg0KDQpPay4gSSB3aWxsIHRha2UgYSBsb29rIGludG8gbW92aW5nIHRoaXMg aW50byBJT1JUIGNvZGUgYW5kIHNoYXJpbmcNCnRocm91Z2ggcGxhdGZvcm0gZGF0YS4NCiANCj4g WyBzaWRlIG5vdGU6IGRvIHlvdSBrbm93IGlmIDE2MjAgc3RpbGwgaGFzIHRoZSBzYW1lIElUUyBx dWlyayBhcyAxNjF4LA0KPiBvciBpcyBpdCBqdXN0IHRoZSBTTU1VJ3MgTVNJIG91dHB1dCB0aGF0 IGRpZG4ndCBnZXQgdXBkYXRlZD8gXQ0KDQpXZSBkb27igJl0IGhhdmUgdGhlIE1TSSByZXNlcnZl IHJlZ2lvbiBpc3N1ZSBmb3IgMTYyMC4gQnV0IEkgdGhpbmsgaXQgc3RpbGwNCnVzZXMgdGhlIHVw cGVyIDQgYnl0ZXMgb2YgR0lUU19UUkFOU0xBVEVSIGFuZCByZXF1aXJlcyB0aGUgcGF0Y2ggZnJv bQ0KTGVpIFpoZW4gdGhhdCB0YWtlcyBjYXJlIG9mIHN5bmNfY291bnQgb3ZlcndyaXRlIG1lbW9y eSBjb3JydXB0aW9uIGlzc3VlLg0KDQpUaGFua3MsDQpTaGFtZWVyDQogDQo+IA0KPiA+ICsNCj4g PiAgIHN0YXRpYyBpbnQgc21tdV9wbXVfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRl dikNCj4gPiAgIHsNCj4gPiAgIAlzdHJ1Y3Qgc21tdV9wbXUgKnNtbXVfcG11Ow0KPiA+IEBAIC03 NDksNiArODA2LDggQEAgc3RhdGljIGludCBzbW11X3BtdV9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1f ZGV2aWNlDQo+ICpwZGV2KQ0KPiA+ICAgCQlyZXR1cm4gLUVJTlZBTDsNCj4gPiAgIAl9DQo+ID4N Cj4gPiArCXNtbXVfcG11X2NoZWNrX2FjcGlfd29ya2Fyb3VuZHMoc21tdV9wbXUpOw0KPiA+ICsN Cj4gPiAgIAkvKiBQaWNrIG9uZSBDUFUgdG8gYmUgdGhlIHByZWZlcnJlZCBvbmUgdG8gdXNlICov DQo+ID4gICAJc21tdV9wbXUtPm9uX2NwdSA9IGdldF9jcHUoKTsNCj4gPiAgIAlXQVJOX09OKGly cV9zZXRfYWZmaW5pdHkoc21tdV9wbXUtPmlycSwgY3B1bWFza19vZihzbW11X3BtdS0NCj4gPm9u X2NwdSkpKTsNCj4gPg0K From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-4.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_PASS,URIBL_BLOCKED autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id DA677C43441 for ; Tue, 27 Nov 2018 13:23:35 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 8DB9E2081B for ; Tue, 27 Nov 2018 13:23:35 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 8DB9E2081B Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=huawei.com Authentication-Results: mail.kernel.org; spf=none smtp.mailfrom=linux-kernel-owner@vger.kernel.org Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1727004AbeK1AV2 (ORCPT ); Tue, 27 Nov 2018 19:21:28 -0500 Received: from lhrrgout.huawei.com ([185.176.76.210]:32784 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726789AbeK1AV2 (ORCPT ); Tue, 27 Nov 2018 19:21:28 -0500 Received: from LHREML712-CAH.china.huawei.com (unknown [172.18.7.108]) by Forcepoint Email with ESMTP id 5E575F6A03935; Tue, 27 Nov 2018 13:23:26 +0000 (GMT) Received: from lhreml708-chm.china.huawei.com (10.201.108.57) by LHREML712-CAH.china.huawei.com (10.201.108.35) with Microsoft SMTP Server (TLS) id 14.3.408.0; Tue, 27 Nov 2018 13:23:27 +0000 Received: from lhreml708-chm.china.huawei.com (10.201.108.57) by lhreml708-chm.china.huawei.com (10.201.108.57) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256_P256) id 15.1.1591.10; Tue, 27 Nov 2018 13:23:27 +0000 Received: from FRAEMA701-CHM.china.huawei.com (10.206.14.50) by lhreml708-chm.china.huawei.com (10.201.108.57) with Microsoft SMTP Server (version=TLS1_0, cipher=TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA_P256) id 15.1.1591.10 via Frontend Transport; Tue, 27 Nov 2018 13:23:27 +0000 Received: from FRAEML521-MBB.china.huawei.com ([169.254.3.116]) by FRAEMA701-CHM.china.huawei.com ([169.254.1.152]) with mapi id 14.03.0415.000; Tue, 27 Nov 2018 14:23:17 +0100 From: Shameerali Kolothum Thodi To: Robin Murphy , "lorenzo.pieralisi@arm.com" , "jean-philippe.brucker@arm.com" CC: "mark.rutland@arm.com" , "vkilari@codeaurora.org" , "neil.m.leeder@gmail.com" , "pabba@codeaurora.org" , "will.deacon@arm.com" , "rruigrok@codeaurora.org" , Linuxarm , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: RE: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk Thread-Topic: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk Thread-Index: AQHUhbg35vJqq0o2l0u/bYNy5S0TQqVjlSIQ Date: Tue, 27 Nov 2018 13:23:16 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA83885EDA7@FRAEML521-MBB.china.huawei.com> References: <20181016124920.24708-1-shameerali.kolothum.thodi@huawei.com> <20181016124920.24708-5-shameerali.kolothum.thodi@huawei.com> <0d7a984e-5814-a986-cd48-ef0651079e32@arm.com> <5FC3163CFD30C246ABAA99954A238FA8387A0342@FRAEML521-MBX.china.huawei.com> <5FC3163CFD30C246ABAA99954A238FA8387A0575@FRAEML521-MBX.china.huawei.com> In-Reply-To: Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.237] Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: base64 MIME-Version: 1.0 X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org DQoNCj4gLS0tLS1PcmlnaW5hbCBNZXNzYWdlLS0tLS0NCj4gRnJvbTogUm9iaW4gTXVycGh5IFtt YWlsdG86cm9iaW4ubXVycGh5QGFybS5jb21dDQo+IFNlbnQ6IDI2IE5vdmVtYmVyIDIwMTggMTg6 NDUNCj4gVG86IFNoYW1lZXJhbGkgS29sb3RodW0gVGhvZGkgPHNoYW1lZXJhbGkua29sb3RodW0u dGhvZGlAaHVhd2VpLmNvbT47DQo+IGxvcmVuem8ucGllcmFsaXNpQGFybS5jb207IGplYW4tcGhp bGlwcGUuYnJ1Y2tlckBhcm0uY29tDQo+IENjOiBtYXJrLnJ1dGxhbmRAYXJtLmNvbTsgdmtpbGFy aUBjb2RlYXVyb3JhLm9yZzsNCj4gbmVpbC5tLmxlZWRlckBnbWFpbC5jb207IHBhYmJhQGNvZGVh dXJvcmEub3JnOyB3aWxsLmRlYWNvbkBhcm0uY29tOw0KPiBycnVpZ3Jva0Bjb2RlYXVyb3JhLm9y ZzsgTGludXhhcm0gPGxpbnV4YXJtQGh1YXdlaS5jb20+OyBsaW51eC0NCj4ga2VybmVsQHZnZXIu a2VybmVsLm9yZzsgbGludXgtYWNwaUB2Z2VyLmtlcm5lbC5vcmc7IGxpbnV4LWFybS0NCj4ga2Vy bmVsQGxpc3RzLmluZnJhZGVhZC5vcmcNCj4gU3ViamVjdDogUmU6IFtQQVRDSCB2NCA0LzRdIHBl cmYvc21tdXYzX3BtdTogRW5hYmxlIEhpU2lsaWNvbiBFcnJhdHVtDQo+IDE2MjAwMTgwMCBxdWly aw0KPiANCj4gSGkgU2hhbWVlciwNCj4gDQo+IFNvcnJ5IGZvciB0aGUgZGVsYXkuLi4NCj4gDQo+ IE9uIDE4LzEwLzIwMTggMTY6MjcsIFNoYW1lZXJhbGkgS29sb3RodW0gVGhvZGkgd3JvdGU6DQo+ ID4NCj4gPg0KPiA+PiAtLS0tLU9yaWdpbmFsIE1lc3NhZ2UtLS0tLQ0KPiA+PiBGcm9tOiBMaW51 eGFybSBbbWFpbHRvOmxpbnV4YXJtLWJvdW5jZXNAaHVhd2VpLmNvbV0gT24gQmVoYWxmIE9mDQo+ ID4+IFNoYW1lZXJhbGkgS29sb3RodW0gVGhvZGkNCj4gPj4gU2VudDogMTggT2N0b2JlciAyMDE4 IDE0OjM0DQo+ID4+IFRvOiBSb2JpbiBNdXJwaHkgPHJvYmluLm11cnBoeUBhcm0uY29tPjsgbG9y ZW56by5waWVyYWxpc2lAYXJtLmNvbTsNCj4gPj4gamVhbi1waGlsaXBwZS5icnVja2VyQGFybS5j b20NCj4gPj4gQ2M6IG1hcmsucnV0bGFuZEBhcm0uY29tOyB2a2lsYXJpQGNvZGVhdXJvcmEub3Jn Ow0KPiA+PiBuZWlsLm0ubGVlZGVyQGdtYWlsLmNvbTsgcGFiYmFAY29kZWF1cm9yYS5vcmc7IHdp bGwuZGVhY29uQGFybS5jb207DQo+ID4+IHJydWlncm9rQGNvZGVhdXJvcmEub3JnOyBMaW51eGFy bSA8bGludXhhcm1AaHVhd2VpLmNvbT47IGxpbnV4LQ0KPiA+PiBrZXJuZWxAdmdlci5rZXJuZWwu b3JnOyBsaW51eC1hY3BpQHZnZXIua2VybmVsLm9yZzsgbGludXgtYXJtLQ0KPiA+PiBrZXJuZWxA bGlzdHMuaW5mcmFkZWFkLm9yZw0KPiA+PiBTdWJqZWN0OiBSRTogW1BBVENIIHY0IDQvNF0gcGVy Zi9zbW11djNfcG11OiBFbmFibGUgSGlTaWxpY29uIEVycmF0dW0NCj4gPj4gMTYyMDAxODAwIHF1 aXJrDQo+ID4+DQo+ID4+IEhpIFJvYmluLA0KPiA+Pg0KPiA+Pj4gLS0tLS1PcmlnaW5hbCBNZXNz YWdlLS0tLS0NCj4gPj4+IEZyb206IFJvYmluIE11cnBoeSBbbWFpbHRvOnJvYmluLm11cnBoeUBh cm0uY29tXQ0KPiA+Pj4gU2VudDogMTggT2N0b2JlciAyMDE4IDEyOjQ0DQo+ID4+PiBUbzogU2hh bWVlcmFsaSBLb2xvdGh1bSBUaG9kaQ0KPiA8c2hhbWVlcmFsaS5rb2xvdGh1bS50aG9kaUBodWF3 ZWkuY29tPjsNCj4gPj4+IGxvcmVuem8ucGllcmFsaXNpQGFybS5jb207IGplYW4tcGhpbGlwcGUu YnJ1Y2tlckBhcm0uY29tDQo+ID4+PiBDYzogd2lsbC5kZWFjb25AYXJtLmNvbTsgbWFyay5ydXRs YW5kQGFybS5jb207IEd1b2hhbmp1biAoSGFuanVuDQo+IEd1bykNCj4gPj4+IDxndW9oYW5qdW5A aHVhd2VpLmNvbT47IEpvaG4gR2FycnkgPGpvaG4uZ2FycnlAaHVhd2VpLmNvbT47DQo+ID4+PiBw YWJiYUBjb2RlYXVyb3JhLm9yZzsgdmtpbGFyaUBjb2RlYXVyb3JhLm9yZzsNCj4gcnJ1aWdyb2tA Y29kZWF1cm9yYS5vcmc7DQo+ID4+PiBsaW51eC1hY3BpQHZnZXIua2VybmVsLm9yZzsgbGludXgt a2VybmVsQHZnZXIua2VybmVsLm9yZzsgbGludXgtYXJtLQ0KPiA+Pj4ga2VybmVsQGxpc3RzLmlu ZnJhZGVhZC5vcmc7IExpbnV4YXJtIDxsaW51eGFybUBodWF3ZWkuY29tPjsNCj4gPj4+IG5laWwu bS5sZWVkZXJAZ21haWwuY29tDQo+ID4+PiBTdWJqZWN0OiBSZTogW1BBVENIIHY0IDQvNF0gcGVy Zi9zbW11djNfcG11OiBFbmFibGUgSGlTaWxpY29uIEVycmF0dW0NCj4gPj4+IDE2MjAwMTgwMCBx dWlyaw0KPiA+DQo+ID4gWy4uLl0NCj4gPg0KPiA+Pj4+ICtzdGF0aWMgY29uc3Qgc3RydWN0IHNt bXVfcG11X2VycmF0dW1fd2Egc21tdV9wbXVfd2FbXSA9IHsNCj4gPj4+PiArCXsNCj4gPj4+PiAr CQkubWF0Y2hfdHlwZSA9IHNlX21hdGNoX2FjcGlfb2VtLA0KPiA+Pj4+ICsJCS5pZCA9IGhpc2lf MTYyMDAxODAwX29lbV9pbmZvLA0KPiA+Pj4+ICsJCS5kZXNjX3N0ciA9ICJIaVNpbGljb24gZXJy YXR1bSAxNjIwMDE4MDAiLA0KPiA+Pj4+ICsJCS5lbmFibGUgPSBoaXNpX2VycmF0dW1fZXZjbnRy X3Jkb25seSwNCj4gPj4+PiArCX0sDQo+ID4+Pj4gK307DQo+ID4+Pj4gKw0KPiA+Pj4NCj4gPj4+ IFRoZXJlJ3MgYW4gYXdmdWwgbG90IG9mIHJhdyBBQ1BJIGludGVybmFscyBzcGxhc2hlZCBhYm91 dCBoZXJlIC0NCj4gPj4+IGNvdWxkbid0IGF0IGxlYXN0IHNvbWUgb2YgaXQgYmUgYWJzdHJhY3Rl ZCBiZWhpbmQgdGhlIElPUlQgY29kZT8gSW4NCj4gPj4+IGZhY3QsIGNhbid0IElPUlQganVzdCBz ZXQgYWxsIHRoaXMgc3R1ZmYgdXAgaW4gYWR2YW5jZSBsaWtlIGl0IGRvZXMgZm9yDQo+ID4+PiBT TU1Vcz8NCj4gPj4NCj4gPj4gSG1tbS4uIFNvcnJ5LCBub3QgY2xlYXIgdG8gbWUuIFlvdSBtZWFu IHRvIHNheSBhc3NvY2lhdGUgdGhlIElPUlQgbm9kZQ0KPiA+PiB3aXRoIHBsYXRmb3JtIGRldmlj ZSBhbmQgcmV0cmlldmUgaXQgaW4gZHJpdmVyIGp1c3QgbGlrZSBzbW11IGRvZXMgZm9yDQo+ID4+ ICJtb2RlbCIgY2hlY2tzPyBOb3Qgc3VyZSB0aGF0IHdvcmtzIGhlcmUgaWYgdGhhdOKAmXMgd2hh dCB0aGUgYWJvdmUgbWVhbnQuDQo+IA0KPiBJIGRvbid0IHRoaW5rIHRoZXJlJ3MgbXVjaCBvZiBp bnRlcmVzdCBpbiB0aGUgYWN0dWFsIElPUlQgbm9kZSBpdHNlbGYsDQo+IGJ1dCBJIGNhbid0IHNl ZSB0aGF0IHRoZXJlIHdvdWxkIGJlIGFueSBwYXJ0aWN1bGFyIHByb2JsZW0gd2l0aCBwYXNzaW5n DQo+IGVpdGhlciBzb21lIGltcGxlbWVudGF0aW9uIGlkZW50aWZpZXIgb3IganVzdCBhIHJlYWR5 LW1hZGUgc2V0IG9mIHF1aXJrDQo+IGZsYWdzIHRvIHRoZSBQTUNHIGRyaXZlciB2aWEgcGxhdGRh dGEuDQoNCk9rLg0KDQo+ID4+Pj4gICAgI2RlZmluZSB0b19zbW11X3BtdShwKSAoY29udGFpbmVy X29mKHAsIHN0cnVjdCBzbW11X3BtdSwgcG11KSkNCj4gPj4+Pg0KPiA+Pj4+ICAgICNkZWZpbmUg U01NVV9QTVVfRVZFTlRfQVRUUl9FWFRSQUNUT1IoX25hbWUsIF9jb25maWcsDQo+IF9zdGFydCwN Cj4gPj4+IF9lbmQpICAgICAgICBcDQo+ID4+Pj4gQEAgLTIyNCwxNSArMjcxLDIwIEBAIHN0YXRp YyB2b2lkIHNtbXVfcG11X3NldF9wZXJpb2Qoc3RydWN0DQo+ID4+PiBzbW11X3BtdSAqc21tdV9w bXUsDQo+ID4+Pj4gICAgCXUzMiBpZHggPSBod2MtPmlkeDsNCj4gPj4+PiAgICAJdTY0IG5ldzsN Cj4gPj4+Pg0KPiA+Pj4+IC0JLyoNCj4gPj4+PiAtCSAqIFdlIGxpbWl0IHRoZSBtYXggcGVyaW9k IHRvIGhhbGYgdGhlIG1heCBjb3VudGVyIHZhbHVlIG9mIHRoZQ0KPiA+Pj4gY291bnRlcg0KPiA+ Pj4+IC0JICogc2l6ZSwgc28gdGhhdCBldmVuIGluIHRoZSBjYXNlIG9mIGV4dHJlbWUgaW50ZXJy dXB0IGxhdGVuY3kgdGhlDQo+ID4+Pj4gLQkgKiBjb3VudGVyIHdpbGwgKGhvcGVmdWxseSkgbm90 IHdyYXAgcGFzdCBpdHMgaW5pdGlhbCB2YWx1ZS4NCj4gPj4+PiAtCSAqLw0KPiA+Pj4+IC0JbmV3 ID0gc21tdV9wbXUtPmNvdW50ZXJfbWFzayA+PiAxOw0KPiA+Pj4+ICsJaWYgKHNtbXVfcG11LT5v cHRpb25zICYgU01NVV9QTVVfT1BUX0VWQ05UUl9SRE9OTFkpIHsNCj4gPj4+PiArCQluZXcgPSBz bW11X3BtdV9jb3VudGVyX2dldF92YWx1ZShzbW11X3BtdSwgaWR4KTsNCj4gPj4+DQo+ID4+PiBT b21ldGhpbmcncyBjbGVhcmx5IG1pc3NpbmcsIGJlY2F1c2UgaWYgdGhpcyBoYXBwZW5zIHRvIHN0 YXJ0IGF0IDAsIHRoZQ0KPiA+Pj4gY3VycmVudCBvdmVyZmxvdyBoYW5kbGluZyBjb2RlIGNhbm5v dCBwb3NzaWJseSBnaXZlIHRoZSBjb3JyZWN0IGNvdW50Lg0KPiA+Pj4gTXVjaCBhcyBJIGhhdGUg dGhlIHJlc2V0LXRvLWhhbGYtcGVyaW9kIGlkaW9tIGZvciBiZWluZyBpbXBvc3NpYmxlIHRvDQo+ ID4+PiBtYWtlIHNlbnNlIG9mLCBpdCBkb2VzIG1ha2UgdmFyaW91cyBhc3BlY3RzIGFwcGVhciBh IGxvdCBzaW1wbGVyIHRoYW4NCj4gPj4+IHRoZXkgcmVhbGx5IGFyZS4gV2FpdCwgbWF5YmUgdGhh dCdzIHlldCBhbm90aGVyIHJlYXNvbiB0byBoYXRlIGl0Li4uDQo+ID4+DQo+ID4+IFllcywgIGlm IHRoZSBjb3VudGVyIHN0YXJ0cyBhdCAwIGFuZCBvdmVyZmxvdyBoYXBwZW5zLCBpdCB3b24ndCBw b3NzaWJseSBnaXZlDQo+ID4+IHRoZSBjb3JyZWN0IGNvdW50IGNvbXBhcmVkIHRvIHRoZSByZXNl dC10by1oYWxmLXBlcmlvZCBsb2dpYy4gU2luY2UgdGhpcyBpcyBhDQo+ID4+IDY0IGJpdCBjb3Vu dGVyLCBqdXN0IGhvcGUgdGhhdCwgaXQgd29uJ3QgbmVjZXNzYXJpbHkgaGFwcGVuIHRoYXQgb2Z0 ZW4uDQo+IA0KPiBPSywgaWYgdGhlIGZ1bGwgNjQgY291bnRlciBiaXRzIGFyZSBpbXBsZW1lbnRl ZCwgdGhlbiBJIHN1cHBvc2Ugd2UncmUNCj4gcHJvYmFibHkgT0sgdG8gYXNzdW1lIG5vYm9keSdz IGdvaW5nIHRvIHJ1biBhIHNpbmdsZSBwcm9maWxpbmcgc2Vzc2lvbg0KPiBvdmVyIDQrIHllYXJz IG9yIHNvLiBJdCBtaWdodCBiZSB3b3J0aCBhIGNvbW1lbnQganVzdCB0byByZW1pbmQNCj4gb3Vy c2VsdmVzIHRoYXQgd2UncmUgKGN1cnJlbnRseSkgcmVseWluZyBvbiB0aGUgY291bnRlciBzaXpl IHRvIG1vc3RseQ0KPiBtaXRpZ2F0ZSBvdmVyZmxvdy1yZWxhdGVkIGlzc3VlcyBpbiB0aGlzIGNh c2UuDQoNClN1cmUsIEkgd2lsbCBhZGQgYSBjb21tZW50IHRvIG1ha2UgaXQgY2xlYXIuDQogDQo+ ID4NCj4gPiBbLi4uXQ0KPiA+DQo+ID4+Pj4gK3N0YXRpYyB2b2lkIHNtbXVfcG11X2VuYWJsZV9l cnJhdGEoc3RydWN0IHNtbXVfcG11ICpzbW11X3BtdSwNCj4gPj4+PiArCQkJCWVudW0gc21tdV9w bXVfZXJyYXR1bV9tYXRjaF90eXBlIHR5cGUsDQo+ID4+Pj4gKwkJCQlzZV9tYXRjaF9mbl90IG1h dGNoX2ZuLA0KPiA+Pj4+ICsJCQkJdm9pZCAqYXJnKQ0KPiA+Pj4+ICt7DQo+ID4+Pj4gKwljb25z dCBzdHJ1Y3Qgc21tdV9wbXVfZXJyYXR1bV93YSAqd2EgPSBzbW11X3BtdV93YTsNCj4gPj4+PiAr DQo+ID4+Pj4gKwlmb3IgKDsgd2EtPmRlc2Nfc3RyOyB3YSsrKSB7DQo+ID4+Pj4gKwkJaWYgKHdh LT5tYXRjaF90eXBlICE9IHR5cGUpDQo+ID4+Pj4gKwkJCWNvbnRpbnVlOw0KPiA+Pj4+ICsNCj4g Pj4+PiArCQlpZiAobWF0Y2hfZm4od2EsIGFyZykpIHsNCj4gPj4+PiArCQkJaWYgKHdhLT5lbmFi bGUpIHsNCj4gPj4+PiArCQkJCXdhLT5lbmFibGUoc21tdV9wbXUpOw0KPiA+Pj4+ICsJCQkJZGV2 X2luZm8oc21tdV9wbXUtPmRldiwNCj4gPj4+PiArCQkJCQkiRW5hYmxpbmcgd29ya2Fyb3VuZCBm b3IgJXNcbiIsDQo+ID4+Pj4gKwkJCQkJIHdhLT5kZXNjX3N0cik7DQo+ID4+Pj4gKwkJCX0NCj4g Pj4+DQo+ID4+PiBKdXN0IGhvdyBtYW55IGtpbmRzIG9mIGJyb2tlbiBhcmUgd2UgZXhwZWN0aW5n IGhlcmU/IElzIHRoaXMgbGlmdGVkIGZyb20NCj4gPj4+IHRoZSBhcm02NCBjcHVmZWF0dXJlIGZy YW1ld29yaywgYmVjYXVzZSBpdCBzZWVtcyBsaWtlIGFic29sdXRlIG92ZXJraWxsDQo+ID4+PiBm b3IgYSBzaW1wbGUgUE1VIGRyaXZlciB3aGljaCBpbiBhbGwgcmVhbGl0eSBpcyBvbmx5IGV2ZXIg Z29pbmcgdG8NCj4gPj4+IHdpZ2dsZSBhIGZldyBmbGFncyBpbiBzb21lIGRhdGEgc3RydWN0dXJl Lg0KPiA+Pg0KPiA+PiBZZXMsIHRoaXMgZXJyYXR1bSBmcmFtZXdvcmsgaXMgYmFzZWQgb24gdGhl IGFybV9hcmNoX3RpbWVyIGNvZGUuIEFncmVlDQo+IHRoYXQNCj4gPj4gdGhpcyBpcyBhbiBvdmVy a2lsbCBpZiBpdCBpcyBqdXN0IHRvIHN1cHBvcnQgdGhpcyBoYXJkd2FyZS4gSSBhbSBub3Qgc3Vy ZSB0aGlzIGNhbg0KPiBiZQ0KPiA+PiBleHRlbmRlZCB0byBhZGQgdGhlIElNUExFTUVOVEFUSU9O IERFRklORUQgZXZlbnRzIGluIGZ1dHVyZShJIGhhdmVuJ3QNCj4gPj4gbG9va2VkIGludG8gdGhh dCBub3cpLiBJZiB0aGlzIGlzIG5vdCB0aGF0IHVzZWZ1bCBpbiB0aGUgbmVhciBmdXR1cmUsIEkg d2lsbA0KPiByZW1vdmUNCj4gPj4gdGhlDQo+ID4+IGZyYW1ld29yayBwYXJ0IGFuZCB1c2UgdGhl IE9FTSBpbmZvIGRpcmVjdGx5IHRvIHNldCB0aGUgZmxhZy4gUGxlYXNlIGxldCBtZQ0KPiA+PiBr bm93DQo+ID4+IHlvdXIgdGhvdWdodHMuLg0KPiA+DQo+ID4gQmVsb3cgaXMgYW5vdGhlciB0YWtl IG9uIHRoaXMgcGF0Y2guIFBsZWFzZSBsZXQgbWUga25vdyBpZiB0aGlzIG1ha2VzIGFueQ0KPiBz ZW5zZS4uDQo+ID4NCj4gPiBUaGFua3MsDQo+ID4gU2hhbWVlcg0KPiA+DQo+ID4gLS0tLTgtLS0t DQo+ID4gZGlmZiAtLWdpdCBhL2RyaXZlcnMvcGVyZi9hcm1fc21tdXYzX3BtdS5jDQo+IGIvZHJp dmVycy9wZXJmL2FybV9zbW11djNfcG11LmMNCj4gPiBpbmRleCBlZjk0YjkwLi42ZjgxYjk0IDEw MDY0NA0KPiA+IC0tLSBhL2RyaXZlcnMvcGVyZi9hcm1fc21tdXYzX3BtdS5jDQo+ID4gKysrIGIv ZHJpdmVycy9wZXJmL2FybV9zbW11djNfcG11LmMNCj4gPiBAQCAtOTYsNiArOTYsOCBAQA0KPiA+ DQo+ID4gICAjZGVmaW5lIFNNTVVfUEFfU0hJRlQgICAgICAgICAgICAgICAgICAgMTINCj4gPg0K PiA+ICsjZGVmaW5lIFNNTVVfUE1VX09QVF9FVkNOVFJfUkRPTkxZCSgxIDw8IDApDQo+ID4gKw0K PiA+ICAgc3RhdGljIGludCBjcHVocF9zdGF0ZV9udW07DQo+ID4NCj4gPiAgIHN0cnVjdCBzbW11 X3BtdSB7DQo+ID4gQEAgLTExMSwxMCArMTEzLDM4IEBAIHN0cnVjdCBzbW11X3BtdSB7DQo+ID4g ICAJc3RydWN0IGRldmljZSAqZGV2Ow0KPiA+ICAgCXZvaWQgX19pb21lbSAqcmVnX2Jhc2U7DQo+ ID4gICAJdm9pZCBfX2lvbWVtICpyZWxvY19iYXNlOw0KPiA+ICsJdTMyIG9wdGlvbnM7DQo+ID4g ICAJdTY0IGNvdW50ZXJfcHJlc2VudF9tYXNrOw0KPiA+ICAgCXU2NCBjb3VudGVyX21hc2s7DQo+ ID4gICB9Ow0KPiA+DQo+ID4gK3N0cnVjdCBlcnJhdHVtX2FjcGlfb2VtX2luZm8gew0KPiA+ICsJ Y2hhciBvZW1faWRbQUNQSV9PRU1fSURfU0laRSArIDFdOw0KPiA+ICsJY2hhciBvZW1fdGFibGVf aWRbQUNQSV9PRU1fVEFCTEVfSURfU0laRSArIDFdOw0KPiA+ICsJdTMyIG9lbV9yZXZpc2lvbjsN Cj4gPiArCXZvaWQgKCplbmFibGUpKHN0cnVjdCBzbW11X3BtdSAqc21tdV9wbXUpOw0KPiA+ICt9 Ow0KPiA+ICsNCj4gPiArdm9pZCBoaXNpX2VycmF0dW1fZXZjbnRyX3Jkb25seShzdHJ1Y3Qgc21t dV9wbXUgKnNtbXVfcG11KQ0KPiA+ICt7DQo+ID4gKwlzbW11X3BtdS0+b3B0aW9ucyB8PSBTTU1V X1BNVV9PUFRfRVZDTlRSX1JET05MWTsNCj4gPiArCWRldl9pbmZvKHNtbXVfcG11LT5kZXYsICJF bmFibGluZyBIaVNpbGljb24gZXJyYXR1bQ0KPiAxNjIwMDE4MDBcbiIpOw0KPiA+ICt9DQo+ID4g Kw0KPiA+ICtzdGF0aWMgc3RydWN0IGVycmF0dW1fYWNwaV9vZW1faW5mbyBhY3BpX29lbV9pbmZv W10gPSB7DQo+ID4gKwkvKg0KPiA+ICsJICogTm90ZSB0aGF0IHRyYWlsaW5nIHNwYWNlcyBhcmUg cmVxdWlyZWQgdG8gcHJvcGVybHkgbWF0Y2gNCj4gPiArCSAqIHRoZSBPRU0gdGFibGUgaW5mb3Jt YXRpb24uDQo+ID4gKwkgKi8NCj4gPiArCXsNCj4gPiArCQkub2VtX2lkICAgICAgICAgPSAiSElT SSAgIiwNCj4gPiArCQkub2VtX3RhYmxlX2lkICAgPSAiSElQMDggICAiLA0KPiA+ICsJCS5vZW1f cmV2aXNpb24gICA9IDAsDQo+ID4gKwkJLmVuYWJsZSA9IGhpc2lfZXJyYXR1bV9ldmNudHJfcmRv bmx5LA0KPiA+ICsJfSwNCj4gPiArCXsgLyogU2VudGluZWwgaW5kaWNhdGluZyB0aGUgZW5kIG9m IHRoZSBPRU0gYXJyYXkgKi8gfSwNCj4gPiArfTsNCj4gPiArDQo+ID4gICAjZGVmaW5lIHRvX3Nt bXVfcG11KHApIChjb250YWluZXJfb2YocCwgc3RydWN0IHNtbXVfcG11LCBwbXUpKQ0KPiA+DQo+ ID4gICAjZGVmaW5lIFNNTVVfUE1VX0VWRU5UX0FUVFJfRVhUUkFDVE9SKF9uYW1lLCBfY29uZmln LCBfc3RhcnQsDQo+IF9lbmQpICAgICAgICBcDQo+ID4gQEAgLTIyNCwxNSArMjU0LDIwIEBAIHN0 YXRpYyB2b2lkIHNtbXVfcG11X3NldF9wZXJpb2Qoc3RydWN0DQo+IHNtbXVfcG11ICpzbW11X3Bt dSwNCj4gPiAgIAl1MzIgaWR4ID0gaHdjLT5pZHg7DQo+ID4gICAJdTY0IG5ldzsNCj4gPg0KPiA+ IC0JLyoNCj4gPiAtCSAqIFdlIGxpbWl0IHRoZSBtYXggcGVyaW9kIHRvIGhhbGYgdGhlIG1heCBj b3VudGVyIHZhbHVlIG9mIHRoZQ0KPiBjb3VudGVyDQo+ID4gLQkgKiBzaXplLCBzbyB0aGF0IGV2 ZW4gaW4gdGhlIGNhc2Ugb2YgZXh0cmVtZSBpbnRlcnJ1cHQgbGF0ZW5jeSB0aGUNCj4gPiAtCSAq IGNvdW50ZXIgd2lsbCAoaG9wZWZ1bGx5KSBub3Qgd3JhcCBwYXN0IGl0cyBpbml0aWFsIHZhbHVl Lg0KPiA+IC0JICovDQo+ID4gLQluZXcgPSBzbW11X3BtdS0+Y291bnRlcl9tYXNrID4+IDE7DQo+ ID4gKwlpZiAoc21tdV9wbXUtPm9wdGlvbnMgJiBTTU1VX1BNVV9PUFRfRVZDTlRSX1JET05MWSkg ew0KPiA+ICsJCW5ldyA9IHNtbXVfcG11X2NvdW50ZXJfZ2V0X3ZhbHVlKHNtbXVfcG11LCBpZHgp Ow0KPiA+ICsJfSBlbHNlIHsNCj4gPiArCQkvKg0KPiA+ICsJCSAqIFdlIGxpbWl0IHRoZSBtYXgg cGVyaW9kIHRvIGhhbGYgdGhlIG1heCBjb3VudGVyIHZhbHVlDQo+ID4gKwkJICogb2YgdGhlIGNv dW50ZXIgc2l6ZSwgc28gdGhhdCBldmVuIGluIHRoZSBjYXNlIG9mIGV4dHJlbWUNCj4gPiArCQkg KiBpbnRlcnJ1cHQgbGF0ZW5jeSB0aGUgY291bnRlciB3aWxsIChob3BlZnVsbHkpIG5vdCB3cmFw DQo+ID4gKwkJICogcGFzdCBpdHMgaW5pdGlhbCB2YWx1ZS4NCj4gPiArCQkgKi8NCj4gPiArCQlu ZXcgPSBzbW11X3BtdS0+Y291bnRlcl9tYXNrID4+IDE7DQo+ID4gKwkJc21tdV9wbXVfY291bnRl cl9zZXRfdmFsdWUoc21tdV9wbXUsIGlkeCwgbmV3KTsNCj4gPiArCX0NCj4gPg0KPiA+ICAgCWxv Y2FsNjRfc2V0KCZod2MtPnByZXZfY291bnQsIG5ldyk7DQo+ID4gLQlzbW11X3BtdV9jb3VudGVy X3NldF92YWx1ZShzbW11X3BtdSwgaWR4LCBuZXcpOw0KPiA+ICAgfQ0KPiA+DQo+ID4gICBzdGF0 aWMgdm9pZCBzbW11X3BtdV9nZXRfZXZlbnRfZmlsdGVyKHN0cnVjdCBwZXJmX2V2ZW50ICpldmVu dCwgdTMyDQo+ICpzcGFuLA0KPiA+IEBAIC02NzAsNiArNzA1LDI4IEBAIHN0YXRpYyB2b2lkIHNt bXVfcG11X3Jlc2V0KHN0cnVjdCBzbW11X3BtdQ0KPiAqc21tdV9wbXUpDQo+ID4gICAJCSAgICAg ICBzbW11X3BtdS0+cmVsb2NfYmFzZSArIFNNTVVfUE1DR19PVlNDTFIwKTsNCj4gPiAgIH0NCj4g Pg0KPiA+ICtzdGF0aWMgdm9pZCBzbW11X3BtdV9jaGVja19hY3BpX3dvcmthcm91bmRzKHN0cnVj dCBzbW11X3BtdQ0KPiAqc21tdV9wbXUpDQo+ID4gK3sNCj4gPiArCXN0YXRpYyBjb25zdCBzdHJ1 Y3QgZXJyYXR1bV9hY3BpX29lbV9pbmZvIGVtcHR5X29lbV9pbmZvID0ge307DQo+ID4gKwljb25z dCBzdHJ1Y3QgZXJyYXR1bV9hY3BpX29lbV9pbmZvICppbmZvID0gYWNwaV9vZW1faW5mbzsNCj4g PiArCXN0cnVjdCBhY3BpX3RhYmxlX2hlYWRlciAqaGRyOw0KPiA+ICsNCj4gPiArCWlmIChBQ1BJ X0ZBSUxVUkUoYWNwaV9nZXRfdGFibGUoQUNQSV9TSUdfSU9SVCwgMCwgJmhkcikpKSB7DQo+ID4g KwkJZGV2X2VycihzbW11X3BtdS0+ZGV2LCAiZmFpbGVkIHRvIGdldCBJT1JUXG4iKTsNCj4gPiAr CQlyZXR1cm47DQo+ID4gKwl9DQo+ID4gKw0KPiA+ICsJLyogSXRlcmF0ZSBvdmVyIHRoZSBBQ1BJ IE9FTSBpbmZvIGFycmF5LCBsb29raW5nIGZvciBhIG1hdGNoICovDQo+ID4gKwl3aGlsZSAobWVt Y21wKGluZm8sICZlbXB0eV9vZW1faW5mbywgc2l6ZW9mKCppbmZvKSkpIHsNCj4gPiArCQlpZiAo IW1lbWNtcChpbmZvLT5vZW1faWQsIGhkci0+b2VtX2lkLCBBQ1BJX09FTV9JRF9TSVpFKQ0KPiAm Jg0KPiA+ICsJCSAgICAhbWVtY21wKGluZm8tPm9lbV90YWJsZV9pZCwgaGRyLT5vZW1fdGFibGVf aWQsDQo+IEFDUElfT0VNX1RBQkxFX0lEX1NJWkUpICYmDQo+ID4gKwkJCWluZm8tPm9lbV9yZXZp c2lvbiA9PSBoZHItPm9lbV9yZXZpc2lvbikNCj4gPiArCQkJaW5mby0+ZW5hYmxlKHNtbXVfcG11 KTsNCj4gPiArDQo+ID4gKwkJaW5mbysrOw0KPiA+ICsJfQ0KPiA+ICt9DQo+IA0KPiBGV0lXLCB0 aGlzIGxvb2tzIGF3ZnVsbHkgbGlrZSBhY3BpX21hdGNoX3BsYXRmb3JtX2xpc3QoKS4uLg0KPiAN Cj4gSG93ZXZlciwgSSBzdGlsbCB0aGluayB0aGF0IGFueSBwYXJzaW5nIG9mIElPUlQgZmllbGRz IGJlbG9uZ3MgaW4NCj4gaW9ydC5jLCBub3QgaW4gZXZlcnkgZHJpdmVyIHdoaWNoIG1pZ2h0IGV2 ZXIgbmVlZCB0byBkZXRlY3QgYSBxdWlyay4gRm9yDQo+IHN0YXJ0ZXJzLCB0aGF0IGNvZGUgaGFz IGlvcnRfdGFibGUgdG8gaGFuZCwgZnVsbCBrbm93bGVkZ2Ugb2YgYWxsIHRoZQ0KPiBvdGhlciBp ZGVudGlmaWFibGUgY29tcG9uZW50cywgYW5kIGEgYWxyZWFkeSBjb250YWlucyBhIGJ1bmNoIG9m DQo+IHN5c3RlbS1zcGVjaWZpYyBxdWlyayBkZXRlY3Rpb24gd2hpY2ggY291bGQgcG90ZW50aWFs bHkgYmUgc2hhcmVkLg0KDQpPay4gSSB3aWxsIHRha2UgYSBsb29rIGludG8gbW92aW5nIHRoaXMg aW50byBJT1JUIGNvZGUgYW5kIHNoYXJpbmcNCnRocm91Z2ggcGxhdGZvcm0gZGF0YS4NCiANCj4g WyBzaWRlIG5vdGU6IGRvIHlvdSBrbm93IGlmIDE2MjAgc3RpbGwgaGFzIHRoZSBzYW1lIElUUyBx dWlyayBhcyAxNjF4LA0KPiBvciBpcyBpdCBqdXN0IHRoZSBTTU1VJ3MgTVNJIG91dHB1dCB0aGF0 IGRpZG4ndCBnZXQgdXBkYXRlZD8gXQ0KDQpXZSBkb27igJl0IGhhdmUgdGhlIE1TSSByZXNlcnZl IHJlZ2lvbiBpc3N1ZSBmb3IgMTYyMC4gQnV0IEkgdGhpbmsgaXQgc3RpbGwNCnVzZXMgdGhlIHVw cGVyIDQgYnl0ZXMgb2YgR0lUU19UUkFOU0xBVEVSIGFuZCByZXF1aXJlcyB0aGUgcGF0Y2ggZnJv bQ0KTGVpIFpoZW4gdGhhdCB0YWtlcyBjYXJlIG9mIHN5bmNfY291bnQgb3ZlcndyaXRlIG1lbW9y eSBjb3JydXB0aW9uIGlzc3VlLg0KDQpUaGFua3MsDQpTaGFtZWVyDQogDQo+IA0KPiA+ICsNCj4g PiAgIHN0YXRpYyBpbnQgc21tdV9wbXVfcHJvYmUoc3RydWN0IHBsYXRmb3JtX2RldmljZSAqcGRl dikNCj4gPiAgIHsNCj4gPiAgIAlzdHJ1Y3Qgc21tdV9wbXUgKnNtbXVfcG11Ow0KPiA+IEBAIC03 NDksNiArODA2LDggQEAgc3RhdGljIGludCBzbW11X3BtdV9wcm9iZShzdHJ1Y3QgcGxhdGZvcm1f ZGV2aWNlDQo+ICpwZGV2KQ0KPiA+ICAgCQlyZXR1cm4gLUVJTlZBTDsNCj4gPiAgIAl9DQo+ID4N Cj4gPiArCXNtbXVfcG11X2NoZWNrX2FjcGlfd29ya2Fyb3VuZHMoc21tdV9wbXUpOw0KPiA+ICsN Cj4gPiAgIAkvKiBQaWNrIG9uZSBDUFUgdG8gYmUgdGhlIHByZWZlcnJlZCBvbmUgdG8gdXNlICov DQo+ID4gICAJc21tdV9wbXUtPm9uX2NwdSA9IGdldF9jcHUoKTsNCj4gPiAgIAlXQVJOX09OKGly cV9zZXRfYWZmaW5pdHkoc21tdV9wbXUtPmlycSwgY3B1bWFza19vZihzbW11X3BtdS0NCj4gPm9u X2NwdSkpKTsNCj4gPg0K From mboxrd@z Thu Jan 1 00:00:00 1970 From: shameerali.kolothum.thodi@huawei.com (Shameerali Kolothum Thodi) Date: Tue, 27 Nov 2018 13:23:16 +0000 Subject: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum 162001800 quirk In-Reply-To: References: <20181016124920.24708-1-shameerali.kolothum.thodi@huawei.com> <20181016124920.24708-5-shameerali.kolothum.thodi@huawei.com> <0d7a984e-5814-a986-cd48-ef0651079e32@arm.com> <5FC3163CFD30C246ABAA99954A238FA8387A0342@FRAEML521-MBX.china.huawei.com> <5FC3163CFD30C246ABAA99954A238FA8387A0575@FRAEML521-MBX.china.huawei.com> Message-ID: <5FC3163CFD30C246ABAA99954A238FA83885EDA7@FRAEML521-MBB.china.huawei.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org > -----Original Message----- > From: Robin Murphy [mailto:robin.murphy at arm.com] > Sent: 26 November 2018 18:45 > To: Shameerali Kolothum Thodi ; > lorenzo.pieralisi at arm.com; jean-philippe.brucker at arm.com > Cc: mark.rutland at arm.com; vkilari at codeaurora.org; > neil.m.leeder at gmail.com; pabba at codeaurora.org; will.deacon at arm.com; > rruigrok at codeaurora.org; Linuxarm ; linux- > kernel at vger.kernel.org; linux-acpi at vger.kernel.org; linux-arm- > kernel at lists.infradead.org > Subject: Re: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum > 162001800 quirk > > Hi Shameer, > > Sorry for the delay... > > On 18/10/2018 16:27, Shameerali Kolothum Thodi wrote: > > > > > >> -----Original Message----- > >> From: Linuxarm [mailto:linuxarm-bounces at huawei.com] On Behalf Of > >> Shameerali Kolothum Thodi > >> Sent: 18 October 2018 14:34 > >> To: Robin Murphy ; lorenzo.pieralisi at arm.com; > >> jean-philippe.brucker at arm.com > >> Cc: mark.rutland at arm.com; vkilari at codeaurora.org; > >> neil.m.leeder at gmail.com; pabba at codeaurora.org; will.deacon at arm.com; > >> rruigrok at codeaurora.org; Linuxarm ; linux- > >> kernel at vger.kernel.org; linux-acpi at vger.kernel.org; linux-arm- > >> kernel at lists.infradead.org > >> Subject: RE: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum > >> 162001800 quirk > >> > >> Hi Robin, > >> > >>> -----Original Message----- > >>> From: Robin Murphy [mailto:robin.murphy at arm.com] > >>> Sent: 18 October 2018 12:44 > >>> To: Shameerali Kolothum Thodi > ; > >>> lorenzo.pieralisi at arm.com; jean-philippe.brucker at arm.com > >>> Cc: will.deacon at arm.com; mark.rutland at arm.com; Guohanjun (Hanjun > Guo) > >>> ; John Garry ; > >>> pabba at codeaurora.org; vkilari at codeaurora.org; > rruigrok at codeaurora.org; > >>> linux-acpi at vger.kernel.org; linux-kernel at vger.kernel.org; linux-arm- > >>> kernel at lists.infradead.org; Linuxarm ; > >>> neil.m.leeder at gmail.com > >>> Subject: Re: [PATCH v4 4/4] perf/smmuv3_pmu: Enable HiSilicon Erratum > >>> 162001800 quirk > > > > [...] > > > >>>> +static const struct smmu_pmu_erratum_wa smmu_pmu_wa[] = { > >>>> + { > >>>> + .match_type = se_match_acpi_oem, > >>>> + .id = hisi_162001800_oem_info, > >>>> + .desc_str = "HiSilicon erratum 162001800", > >>>> + .enable = hisi_erratum_evcntr_rdonly, > >>>> + }, > >>>> +}; > >>>> + > >>> > >>> There's an awful lot of raw ACPI internals splashed about here - > >>> couldn't at least some of it be abstracted behind the IORT code? In > >>> fact, can't IORT just set all this stuff up in advance like it does for > >>> SMMUs? > >> > >> Hmmm.. Sorry, not clear to me. You mean to say associate the IORT node > >> with platform device and retrieve it in driver just like smmu does for > >> "model" checks? Not sure that works here if that?s what the above meant. > > I don't think there's much of interest in the actual IORT node itself, > but I can't see that there would be any particular problem with passing > either some implementation identifier or just a ready-made set of quirk > flags to the PMCG driver via platdata. Ok. > >>>> #define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu)) > >>>> > >>>> #define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, > _start, > >>> _end) \ > >>>> @@ -224,15 +271,20 @@ static void smmu_pmu_set_period(struct > >>> smmu_pmu *smmu_pmu, > >>>> u32 idx = hwc->idx; > >>>> u64 new; > >>>> > >>>> - /* > >>>> - * We limit the max period to half the max counter value of the > >>> counter > >>>> - * size, so that even in the case of extreme interrupt latency the > >>>> - * counter will (hopefully) not wrap past its initial value. > >>>> - */ > >>>> - new = smmu_pmu->counter_mask >> 1; > >>>> + if (smmu_pmu->options & SMMU_PMU_OPT_EVCNTR_RDONLY) { > >>>> + new = smmu_pmu_counter_get_value(smmu_pmu, idx); > >>> > >>> Something's clearly missing, because if this happens to start at 0, the > >>> current overflow handling code cannot possibly give the correct count. > >>> Much as I hate the reset-to-half-period idiom for being impossible to > >>> make sense of, it does make various aspects appear a lot simpler than > >>> they really are. Wait, maybe that's yet another reason to hate it... > >> > >> Yes, if the counter starts at 0 and overflow happens, it won't possibly give > >> the correct count compared to the reset-to-half-period logic. Since this is a > >> 64 bit counter, just hope that, it won't necessarily happen that often. > > OK, if the full 64 counter bits are implemented, then I suppose we're > probably OK to assume nobody's going to run a single profiling session > over 4+ years or so. It might be worth a comment just to remind > ourselves that we're (currently) relying on the counter size to mostly > mitigate overflow-related issues in this case. Sure, I will add a comment to make it clear. > > > > [...] > > > >>>> +static void smmu_pmu_enable_errata(struct smmu_pmu *smmu_pmu, > >>>> + enum smmu_pmu_erratum_match_type type, > >>>> + se_match_fn_t match_fn, > >>>> + void *arg) > >>>> +{ > >>>> + const struct smmu_pmu_erratum_wa *wa = smmu_pmu_wa; > >>>> + > >>>> + for (; wa->desc_str; wa++) { > >>>> + if (wa->match_type != type) > >>>> + continue; > >>>> + > >>>> + if (match_fn(wa, arg)) { > >>>> + if (wa->enable) { > >>>> + wa->enable(smmu_pmu); > >>>> + dev_info(smmu_pmu->dev, > >>>> + "Enabling workaround for %s\n", > >>>> + wa->desc_str); > >>>> + } > >>> > >>> Just how many kinds of broken are we expecting here? Is this lifted from > >>> the arm64 cpufeature framework, because it seems like absolute overkill > >>> for a simple PMU driver which in all reality is only ever going to > >>> wiggle a few flags in some data structure. > >> > >> Yes, this erratum framework is based on the arm_arch_timer code. Agree > that > >> this is an overkill if it is just to support this hardware. I am not sure this can > be > >> extended to add the IMPLEMENTATION DEFINED events in future(I haven't > >> looked into that now). If this is not that useful in the near future, I will > remove > >> the > >> framework part and use the OEM info directly to set the flag. Please let me > >> know > >> your thoughts.. > > > > Below is another take on this patch. Please let me know if this makes any > sense.. > > > > Thanks, > > Shameer > > > > ----8---- > > diff --git a/drivers/perf/arm_smmuv3_pmu.c > b/drivers/perf/arm_smmuv3_pmu.c > > index ef94b90..6f81b94 100644 > > --- a/drivers/perf/arm_smmuv3_pmu.c > > +++ b/drivers/perf/arm_smmuv3_pmu.c > > @@ -96,6 +96,8 @@ > > > > #define SMMU_PA_SHIFT 12 > > > > +#define SMMU_PMU_OPT_EVCNTR_RDONLY (1 << 0) > > + > > static int cpuhp_state_num; > > > > struct smmu_pmu { > > @@ -111,10 +113,38 @@ struct smmu_pmu { > > struct device *dev; > > void __iomem *reg_base; > > void __iomem *reloc_base; > > + u32 options; > > u64 counter_present_mask; > > u64 counter_mask; > > }; > > > > +struct erratum_acpi_oem_info { > > + char oem_id[ACPI_OEM_ID_SIZE + 1]; > > + char oem_table_id[ACPI_OEM_TABLE_ID_SIZE + 1]; > > + u32 oem_revision; > > + void (*enable)(struct smmu_pmu *smmu_pmu); > > +}; > > + > > +void hisi_erratum_evcntr_rdonly(struct smmu_pmu *smmu_pmu) > > +{ > > + smmu_pmu->options |= SMMU_PMU_OPT_EVCNTR_RDONLY; > > + dev_info(smmu_pmu->dev, "Enabling HiSilicon erratum > 162001800\n"); > > +} > > + > > +static struct erratum_acpi_oem_info acpi_oem_info[] = { > > + /* > > + * Note that trailing spaces are required to properly match > > + * the OEM table information. > > + */ > > + { > > + .oem_id = "HISI ", > > + .oem_table_id = "HIP08 ", > > + .oem_revision = 0, > > + .enable = hisi_erratum_evcntr_rdonly, > > + }, > > + { /* Sentinel indicating the end of the OEM array */ }, > > +}; > > + > > #define to_smmu_pmu(p) (container_of(p, struct smmu_pmu, pmu)) > > > > #define SMMU_PMU_EVENT_ATTR_EXTRACTOR(_name, _config, _start, > _end) \ > > @@ -224,15 +254,20 @@ static void smmu_pmu_set_period(struct > smmu_pmu *smmu_pmu, > > u32 idx = hwc->idx; > > u64 new; > > > > - /* > > - * We limit the max period to half the max counter value of the > counter > > - * size, so that even in the case of extreme interrupt latency the > > - * counter will (hopefully) not wrap past its initial value. > > - */ > > - new = smmu_pmu->counter_mask >> 1; > > + if (smmu_pmu->options & SMMU_PMU_OPT_EVCNTR_RDONLY) { > > + new = smmu_pmu_counter_get_value(smmu_pmu, idx); > > + } else { > > + /* > > + * We limit the max period to half the max counter value > > + * of the counter size, so that even in the case of extreme > > + * interrupt latency the counter will (hopefully) not wrap > > + * past its initial value. > > + */ > > + new = smmu_pmu->counter_mask >> 1; > > + smmu_pmu_counter_set_value(smmu_pmu, idx, new); > > + } > > > > local64_set(&hwc->prev_count, new); > > - smmu_pmu_counter_set_value(smmu_pmu, idx, new); > > } > > > > static void smmu_pmu_get_event_filter(struct perf_event *event, u32 > *span, > > @@ -670,6 +705,28 @@ static void smmu_pmu_reset(struct smmu_pmu > *smmu_pmu) > > smmu_pmu->reloc_base + SMMU_PMCG_OVSCLR0); > > } > > > > +static void smmu_pmu_check_acpi_workarounds(struct smmu_pmu > *smmu_pmu) > > +{ > > + static const struct erratum_acpi_oem_info empty_oem_info = {}; > > + const struct erratum_acpi_oem_info *info = acpi_oem_info; > > + struct acpi_table_header *hdr; > > + > > + if (ACPI_FAILURE(acpi_get_table(ACPI_SIG_IORT, 0, &hdr))) { > > + dev_err(smmu_pmu->dev, "failed to get IORT\n"); > > + return; > > + } > > + > > + /* Iterate over the ACPI OEM info array, looking for a match */ > > + while (memcmp(info, &empty_oem_info, sizeof(*info))) { > > + if (!memcmp(info->oem_id, hdr->oem_id, ACPI_OEM_ID_SIZE) > && > > + !memcmp(info->oem_table_id, hdr->oem_table_id, > ACPI_OEM_TABLE_ID_SIZE) && > > + info->oem_revision == hdr->oem_revision) > > + info->enable(smmu_pmu); > > + > > + info++; > > + } > > +} > > FWIW, this looks awfully like acpi_match_platform_list()... > > However, I still think that any parsing of IORT fields belongs in > iort.c, not in every driver which might ever need to detect a quirk. For > starters, that code has iort_table to hand, full knowledge of all the > other identifiable components, and a already contains a bunch of > system-specific quirk detection which could potentially be shared. Ok. I will take a look into moving this into IORT code and sharing through platform data. > [ side note: do you know if 1620 still has the same ITS quirk as 161x, > or is it just the SMMU's MSI output that didn't get updated? ] We don?t have the MSI reserve region issue for 1620. But I think it still uses the upper 4 bytes of GITS_TRANSLATER and requires the patch from Lei Zhen that takes care of sync_count overwrite memory corruption issue. Thanks, Shameer > > > + > > static int smmu_pmu_probe(struct platform_device *pdev) > > { > > struct smmu_pmu *smmu_pmu; > > @@ -749,6 +806,8 @@ static int smmu_pmu_probe(struct platform_device > *pdev) > > return -EINVAL; > > } > > > > + smmu_pmu_check_acpi_workarounds(smmu_pmu); > > + > > /* Pick one CPU to be the preferred one to use */ > > smmu_pmu->on_cpu = get_cpu(); > > WARN_ON(irq_set_affinity(smmu_pmu->irq, cpumask_of(smmu_pmu- > >on_cpu))); > >