From mboxrd@z Thu Jan 1 00:00:00 1970 From: Shameerali Kolothum Thodi Subject: RE: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk Date: Thu, 4 Apr 2019 16:31:55 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA8393575FC@lhreml524-mbs.china.huawei.com> References: <20190326151753.19384-1-shameerali.kolothum.thodi@huawei.com> <20190326151753.19384-5-shameerali.kolothum.thodi@huawei.com> <20190404154711.GA27577@fuggles.cambridge.arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT Return-path: In-Reply-To: <20190404154711.GA27577@fuggles.cambridge.arm.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Will Deacon Cc: "lorenzo.pieralisi@arm.com" , "robin.murphy@arm.com" , "andrew.murray@arm.com" , "jean-philippe.brucker@arm.com" , "mark.rutland@arm.com" , "Guohanjun (Hanjun Guo)" , John Garry , "pabba@codeaurora.org" , "vkilari@codeaurora.org" , "rruigrok@codeaurora.org" , "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Linuxarm , "neil.m.leeder@gmail.com" List-Id: linux-acpi@vger.kernel.org > -----Original Message----- > From: Will Deacon [mailto:will.deacon@arm.com] > Sent: 04 April 2019 16:47 > To: Shameerali Kolothum Thodi > Cc: lorenzo.pieralisi@arm.com; robin.murphy@arm.com; > andrew.murray@arm.com; jean-philippe.brucker@arm.com; > mark.rutland@arm.com; Guohanjun (Hanjun Guo) ; > John Garry ; pabba@codeaurora.org; > vkilari@codeaurora.org; rruigrok@codeaurora.org; linux-acpi@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Linuxarm > ; neil.m.leeder@gmail.com > Subject: Re: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 > quirk > > On Tue, Mar 26, 2019 at 03:17:53PM +0000, Shameer Kolothum wrote: > > HiSilicon erratum 162001800 describes the limitation of > > SMMUv3 PMCG implementation on HiSilicon Hip08 platforms. > > > > On these platforms, the PMCG event counter registers > > (SMMU_PMCG_EVCNTRn) are read only and as a result it > > is not possible to set the initial counter period value > > on event monitor start. > > > > To work around this, the current value of the counter > > is read and used for delta calculations. OEM information > > from ACPI header is used to identify the affected hardware > > platforms. > > > > Signed-off-by: Shameer Kolothum > > Reviewed-by: Hanjun Guo > > Reviewed-by: Robin Murphy > > --- > > drivers/acpi/arm64/iort.c | 16 ++++++++++++++- > > drivers/perf/arm_smmuv3_pmu.c | 48 > ++++++++++++++++++++++++++++++++++++------- > > include/linux/acpi_iort.h | 1 + > > 3 files changed, 57 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c > > index e2c9b26..4dc68de 100644 > > --- a/drivers/acpi/arm64/iort.c > > +++ b/drivers/acpi/arm64/iort.c > > @@ -1366,9 +1366,23 @@ static void __init > arm_smmu_v3_pmcg_init_resources(struct resource *res, > > ACPI_EDGE_SENSITIVE, &res[2]); > > } > > > > +static struct acpi_platform_list pmcg_plat_info[] __initdata = { > > + /* HiSilicon Hip08 Platform */ > > + {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, 0, > > Passing integer constant 0 for the reason feels wrong to me. I'm going to > change it to "Erratum #162001800" and also add an entry to > silicon-errata.txt. > > Please shout if that's not ok. Thanks Will for taking a look at this series. The proposed changes are fine to me. Shameer From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=HEADER_FROM_DIFFERENT_DOMAINS, INCLUDES_PATCH,MAILING_LIST_MULTI,SIGNED_OFF_BY,SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 8BDDDC10F0C for ; Thu, 4 Apr 2019 16:32:07 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [209.132.180.67]) by mail.kernel.org (Postfix) with ESMTP id 6512A206BA for ; Thu, 4 Apr 2019 16:32:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1729207AbfDDQcG convert rfc822-to-8bit (ORCPT ); Thu, 4 Apr 2019 12:32:06 -0400 Received: from lhrrgout.huawei.com ([185.176.76.210]:32918 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1727053AbfDDQcE (ORCPT ); Thu, 4 Apr 2019 12:32:04 -0400 Received: from LHREML712-CAH.china.huawei.com (unknown [172.18.7.106]) by Forcepoint Email with ESMTP id 6070DFF7FF970DE39579; Thu, 4 Apr 2019 17:32:03 +0100 (IST) Received: from LHREML524-MBS.china.huawei.com ([169.254.2.229]) by LHREML712-CAH.china.huawei.com ([10.201.108.35]) with mapi id 14.03.0415.000; Thu, 4 Apr 2019 17:31:55 +0100 From: Shameerali Kolothum Thodi To: Will Deacon CC: "lorenzo.pieralisi@arm.com" , "robin.murphy@arm.com" , "andrew.murray@arm.com" , "jean-philippe.brucker@arm.com" , "mark.rutland@arm.com" , "Guohanjun (Hanjun Guo)" , "John Garry" , "pabba@codeaurora.org" , "vkilari@codeaurora.org" , "rruigrok@codeaurora.org" , "linux-acpi@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , Linuxarm , "neil.m.leeder@gmail.com" Subject: RE: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk Thread-Topic: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk Thread-Index: AQHU4+eNGDYznP+LJkGbBgcrT5VMl6YsIsKAgAAVvUA= Date: Thu, 4 Apr 2019 16:31:55 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA8393575FC@lhreml524-mbs.china.huawei.com> References: <20190326151753.19384-1-shameerali.kolothum.thodi@huawei.com> <20190326151753.19384-5-shameerali.kolothum.thodi@huawei.com> <20190404154711.GA27577@fuggles.cambridge.arm.com> In-Reply-To: <20190404154711.GA27577@fuggles.cambridge.arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.237] Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 8BIT MIME-Version: 1.0 X-CFilter-Loop: Reflected Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > -----Original Message----- > From: Will Deacon [mailto:will.deacon@arm.com] > Sent: 04 April 2019 16:47 > To: Shameerali Kolothum Thodi > Cc: lorenzo.pieralisi@arm.com; robin.murphy@arm.com; > andrew.murray@arm.com; jean-philippe.brucker@arm.com; > mark.rutland@arm.com; Guohanjun (Hanjun Guo) ; > John Garry ; pabba@codeaurora.org; > vkilari@codeaurora.org; rruigrok@codeaurora.org; linux-acpi@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Linuxarm > ; neil.m.leeder@gmail.com > Subject: Re: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 > quirk > > On Tue, Mar 26, 2019 at 03:17:53PM +0000, Shameer Kolothum wrote: > > HiSilicon erratum 162001800 describes the limitation of > > SMMUv3 PMCG implementation on HiSilicon Hip08 platforms. > > > > On these platforms, the PMCG event counter registers > > (SMMU_PMCG_EVCNTRn) are read only and as a result it > > is not possible to set the initial counter period value > > on event monitor start. > > > > To work around this, the current value of the counter > > is read and used for delta calculations. OEM information > > from ACPI header is used to identify the affected hardware > > platforms. > > > > Signed-off-by: Shameer Kolothum > > Reviewed-by: Hanjun Guo > > Reviewed-by: Robin Murphy > > --- > > drivers/acpi/arm64/iort.c | 16 ++++++++++++++- > > drivers/perf/arm_smmuv3_pmu.c | 48 > ++++++++++++++++++++++++++++++++++++------- > > include/linux/acpi_iort.h | 1 + > > 3 files changed, 57 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c > > index e2c9b26..4dc68de 100644 > > --- a/drivers/acpi/arm64/iort.c > > +++ b/drivers/acpi/arm64/iort.c > > @@ -1366,9 +1366,23 @@ static void __init > arm_smmu_v3_pmcg_init_resources(struct resource *res, > > ACPI_EDGE_SENSITIVE, &res[2]); > > } > > > > +static struct acpi_platform_list pmcg_plat_info[] __initdata = { > > + /* HiSilicon Hip08 Platform */ > > + {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, 0, > > Passing integer constant 0 for the reason feels wrong to me. I'm going to > change it to "Erratum #162001800" and also add an entry to > silicon-errata.txt. > > Please shout if that's not ok. Thanks Will for taking a look at this series. The proposed changes are fine to me. Shameer From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-7.0 required=3.0 tests=DKIMWL_WL_HIGH,DKIM_SIGNED, DKIM_VALID,HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI, SIGNED_OFF_BY,SPF_PASS,URIBL_BLOCKED autolearn=unavailable autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id AC3C9C4360F for ; Thu, 4 Apr 2019 16:32:22 +0000 (UTC) Received: from bombadil.infradead.org (bombadil.infradead.org [198.137.202.133]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id 79CFB206BA for ; Thu, 4 Apr 2019 16:32:22 +0000 (UTC) Authentication-Results: mail.kernel.org; dkim=pass (2048-bit key) header.d=lists.infradead.org header.i=@lists.infradead.org header.b="EBYGXBMy" DMARC-Filter: OpenDMARC Filter v1.3.2 mail.kernel.org 79CFB206BA Authentication-Results: mail.kernel.org; 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Received: from localhost ([127.0.0.1] helo=bombadil.infradead.org) by bombadil.infradead.org with esmtp (Exim 4.90_1 #2 (Red Hat Linux)) id 1hC5Hm-0001VL-Nz; Thu, 04 Apr 2019 16:32:18 +0000 Received: from lhrrgout.huawei.com ([185.176.76.210] helo=huawei.com) by bombadil.infradead.org with esmtps (Exim 4.90_1 #2 (Red Hat Linux)) id 1hC5Hj-0001Sx-Bj for linux-arm-kernel@lists.infradead.org; Thu, 04 Apr 2019 16:32:17 +0000 Received: from LHREML712-CAH.china.huawei.com (unknown [172.18.7.106]) by Forcepoint Email with ESMTP id 6070DFF7FF970DE39579; Thu, 4 Apr 2019 17:32:03 +0100 (IST) Received: from LHREML524-MBS.china.huawei.com ([169.254.2.229]) by LHREML712-CAH.china.huawei.com ([10.201.108.35]) with mapi id 14.03.0415.000; Thu, 4 Apr 2019 17:31:55 +0100 From: Shameerali Kolothum Thodi To: Will Deacon Subject: RE: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk Thread-Topic: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 quirk Thread-Index: AQHU4+eNGDYznP+LJkGbBgcrT5VMl6YsIsKAgAAVvUA= Date: Thu, 4 Apr 2019 16:31:55 +0000 Message-ID: <5FC3163CFD30C246ABAA99954A238FA8393575FC@lhreml524-mbs.china.huawei.com> References: <20190326151753.19384-1-shameerali.kolothum.thodi@huawei.com> <20190326151753.19384-5-shameerali.kolothum.thodi@huawei.com> <20190404154711.GA27577@fuggles.cambridge.arm.com> In-Reply-To: <20190404154711.GA27577@fuggles.cambridge.arm.com> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-originating-ip: [10.202.227.237] MIME-Version: 1.0 X-CFilter-Loop: Reflected X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20190404_093215_552565_208B2853 X-CRM114-Status: GOOD ( 19.41 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.21 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: "mark.rutland@arm.com" , "vkilari@codeaurora.org" , "lorenzo.pieralisi@arm.com" , "neil.m.leeder@gmail.com" , "jean-philippe.brucker@arm.com" , "pabba@codeaurora.org" , John Garry , Linuxarm , "rruigrok@codeaurora.org" , "linux-kernel@vger.kernel.org" , "linux-acpi@vger.kernel.org" , "Guohanjun \(Hanjun Guo\)" , "andrew.murray@arm.com" , "robin.murphy@arm.com" , "linux-arm-kernel@lists.infradead.org" Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+infradead-linux-arm-kernel=archiver.kernel.org@lists.infradead.org > -----Original Message----- > From: Will Deacon [mailto:will.deacon@arm.com] > Sent: 04 April 2019 16:47 > To: Shameerali Kolothum Thodi > Cc: lorenzo.pieralisi@arm.com; robin.murphy@arm.com; > andrew.murray@arm.com; jean-philippe.brucker@arm.com; > mark.rutland@arm.com; Guohanjun (Hanjun Guo) ; > John Garry ; pabba@codeaurora.org; > vkilari@codeaurora.org; rruigrok@codeaurora.org; linux-acpi@vger.kernel.org; > linux-kernel@vger.kernel.org; linux-arm-kernel@lists.infradead.org; Linuxarm > ; neil.m.leeder@gmail.com > Subject: Re: [PATCH v7 4/4] perf/smmuv3: Enable HiSilicon Erratum 162001800 > quirk > > On Tue, Mar 26, 2019 at 03:17:53PM +0000, Shameer Kolothum wrote: > > HiSilicon erratum 162001800 describes the limitation of > > SMMUv3 PMCG implementation on HiSilicon Hip08 platforms. > > > > On these platforms, the PMCG event counter registers > > (SMMU_PMCG_EVCNTRn) are read only and as a result it > > is not possible to set the initial counter period value > > on event monitor start. > > > > To work around this, the current value of the counter > > is read and used for delta calculations. OEM information > > from ACPI header is used to identify the affected hardware > > platforms. > > > > Signed-off-by: Shameer Kolothum > > Reviewed-by: Hanjun Guo > > Reviewed-by: Robin Murphy > > --- > > drivers/acpi/arm64/iort.c | 16 ++++++++++++++- > > drivers/perf/arm_smmuv3_pmu.c | 48 > ++++++++++++++++++++++++++++++++++++------- > > include/linux/acpi_iort.h | 1 + > > 3 files changed, 57 insertions(+), 8 deletions(-) > > > > diff --git a/drivers/acpi/arm64/iort.c b/drivers/acpi/arm64/iort.c > > index e2c9b26..4dc68de 100644 > > --- a/drivers/acpi/arm64/iort.c > > +++ b/drivers/acpi/arm64/iort.c > > @@ -1366,9 +1366,23 @@ static void __init > arm_smmu_v3_pmcg_init_resources(struct resource *res, > > ACPI_EDGE_SENSITIVE, &res[2]); > > } > > > > +static struct acpi_platform_list pmcg_plat_info[] __initdata = { > > + /* HiSilicon Hip08 Platform */ > > + {"HISI ", "HIP08 ", 0, ACPI_SIG_IORT, greater_than_or_equal, 0, > > Passing integer constant 0 for the reason feels wrong to me. I'm going to > change it to "Erratum #162001800" and also add an entry to > silicon-errata.txt. > > Please shout if that's not ok. Thanks Will for taking a look at this series. The proposed changes are fine to me. Shameer _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel