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From: Richard Henderson <richard.henderson@linaro.org>
To: Idan Horowitz <idan.horowitz@gmail.com>, qemu-arm@nongnu.org
Cc: Peter Maydell <peter.maydell@linaro.org>, qemu-devel@nongnu.org
Subject: Re: [PATCH 2/3] target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk
Date: Tue, 29 Mar 2022 10:36:20 -0600	[thread overview]
Message-ID: <5a395ab9-a7a4-6305-13f0-9808572a9b56@linaro.org> (raw)
In-Reply-To: <20220327093427.1548629-3-idan.horowitz@gmail.com>

On 3/27/22 03:34, Idan Horowitz wrote:
> As per the AArch64.SS2InitialTTWState() psuedo-code in the ARMv8 ARM the
> initial PA space used for stage 2 table walks is assigned based on the SW
> and NSW bits of the VSTCR and VTCR registers.
> This was already implemented for the recursive stage 2 page table walks
> in S1_ptw_translate(), but was missing for the final stage 2 walk.
> 
> Signed-off-by: Idan Horowitz<idan.horowitz@gmail.com>
> ---
>   target/arm/helper.c | 10 ++++++++++
>   1 file changed, 10 insertions(+)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~


  reply	other threads:[~2022-03-29 16:37 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-27  9:34 [PATCH 0/3] Bug fixes related to secure 2 stage translation Idan Horowitz
2022-03-27  9:34 ` [PATCH 1/3] target/arm: Check VSTCR.SW when assigning the stage 2 output PA space Idan Horowitz
2022-03-27 14:24   ` Rémi Denis-Courmont
2022-03-29 14:59     ` Richard Henderson
2022-03-29 14:59   ` Richard Henderson
2022-03-27  9:34 ` [PATCH 2/3] target/arm: Take VSTCR.SW, VTCR.NSW into account in final stage 2 walk Idan Horowitz
2022-03-29 16:36   ` Richard Henderson [this message]
2022-03-27  9:34 ` [PATCH 3/3] target/arm: Determine final stage 2 output PA space based on original IPA Idan Horowitz
2022-03-29 19:09   ` Richard Henderson
2022-03-29 20:18     ` Idan Horowitz
2022-03-31  8:46     ` Peter Maydell
2022-03-31  8:46 ` [PATCH 0/3] Bug fixes related to secure 2 stage translation Peter Maydell

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