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([2600:8800:1700:8300:1d91:43c6:b336:345b]) by smtp.gmail.com with ESMTPSA id b88sm18497532pfe.66.2016.09.24.05.46.24 (version=TLS1_2 cipher=ECDHE-RSA-AES128-GCM-SHA256 bits=128/128); Sat, 24 Sep 2016 05:46:25 -0700 (PDT) To: Andy Duan , "meta-freescale@yoctoproject.org" References: <1474681465-9796-1-git-send-email-eric@nelint.com> From: Eric Nelson Message-ID: <5af9684e-e3d8-cae6-7d73-391e9b53778f@nelint.com> Date: Sat, 24 Sep 2016 05:46:24 -0700 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:45.0) Gecko/20100101 Thunderbird/45.2.0 MIME-Version: 1.0 In-Reply-To: Cc: "andrew@lunn.ch" , "linux@arm.linux.org.uk" , "otavio@ossystems.com.br" Subject: Re: [PATCH][linux-fslc][4.1-1.0.x-imx] net: fec: support RRACC_SHIFT16 to align IP header X-BeenThere: meta-freescale@yoctoproject.org X-Mailman-Version: 2.1.13 Precedence: list List-Id: Usage and development list for the meta-fsl-* layers List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 24 Sep 2016 12:46:30 -0000 Content-Type: text/plain; charset=windows-1252 Content-Transfer-Encoding: 7bit Hi Andy, On 09/23/2016 10:00 PM, Andy Duan wrote: > From: Eric Nelson Sent: Saturday, September 24, 2016 9:44 AM >> To: meta-freescale@yoctoproject.org >> Cc: linux@arm.linux.org.uk; andrew@lunn.ch; Andy Duan >> ; otavio@ossystems.com.br; Eric Nelson >> >> Subject: [PATCH][linux-fslc][4.1-1.0.x-imx] net: fec: support RRACC_SHIFT16 >> to align IP header >> >> The i.MX6 UL and DQLS variants all support shifting the data payload of >> received packets by 16-bits, which aligns the IP header on a longword >> boundary, which is, if not required, at least strongly suggested by the Linux >> networking layer. >> >> Without this patch, a huge number of alignment faults will be taken by the IP >> stack, as seen in /proc/cpu/alignment: >> >> ~/$ cat /proc/cpu/alignment >> User: 0 >> System: 72645 (inet_gro_receive+0x104/0x27c) >> Skipped: 0 >> Half: 0 >> Word: 0 >> DWord: 0 >> Multi: 72645 >> User faults: 3 (fixup+warn) >> >> With this patch, I am still seeing some alignment faults, but on the order of 10 >> after a 100MiB transfer instead of the 72k shown above. >> >> This patch was suggested by Andrew Lunn in this message to linux-netdev: >> http://marc.info/?l=linux-arm-kernel&m=147465452108384&w=2 >> >> and adapted from a patch by Russell King from 2014: >> http://git.arm.linux.org.uk/cgit/linux-arm.git/commit/?h=fec- >> testing&id=70d8a8a >> >> Signed-off-by: Eric Nelson >> --- >> I've only tested this patch on i.MX6UL at the moment, an encourage others >> using 4.1.x to try it out. >> >> I did look at the RM for the i.MX6SX and updates will be needed for that >> machine because the bit appears to be in a different location. >> >> Note that there are lots of other patches in Russell's tree that deserve some >> effort in bringing up-stream and I encourage others to make use of his work. >> >> drivers/net/ethernet/freescale/fec.h | 4 ++++ >> drivers/net/ethernet/freescale/fec_main.c | 36 > > Test pass the patch on i.MX6UL. > But still have some comments as below. > >> +++++++++++++++++++++++++------ >> 2 files changed, 34 insertions(+), 6 deletions(-) >> >> diff --git a/drivers/net/ethernet/freescale/fec.h >> b/drivers/net/ethernet/freescale/fec.h >> index 65a3cd3..5ed0a5c 100644 >> --- a/drivers/net/ethernet/freescale/fec.h >> +++ b/drivers/net/ethernet/freescale/fec.h >> @@ -436,6 +436,7 @@ struct bufdesc_ex { >> #define FEC_QUIRK_SINGLE_MDIO (1 << 11) >> /* Controller supports RACC register */ >> #define FEC_QUIRK_HAS_RACC (1 << 12) >> + >> /* >> * i.MX6Q/DL ENET cannot wake up system in wait mode because ENET tx & >> rx >> * interrupt signal don't connect to GPC. So use pm qos to avoid cpu enter >> @@ -443,6 +444,9 @@ struct bufdesc_ex { >> */ >> #define FEC_QUIRK_BUG_WAITMODE (1 << 13) >> >> +/* Controller has ability to offset rx packets */ >> +#define FEC_QUIRK_RX_SHIFT16 (1 << 14) >> + > > It is not necessary to define the quirk flag. > All SOCs with RACC register has the bit. > I just checked, and I was wrong in my comment about the SoloX using a different bit. I think I was looking at the bitfield in the ENETx_TACC register. Okay. I'll re-work this for a V3 on linux-fslc.