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[189.204.159.168]) by smtp.gmail.com with ESMTPSA id r17sm10662388qtx.62.2021.03.23.05.14.59 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 23 Mar 2021 05:14:59 -0700 (PDT) Subject: Re: [PATCH] i386/cpu_dump: support AVX512 ZMM regs dump To: Robert Hoo , pbonzini@redhat.com, ehabkost@redhat.com References: <1616410796-43167-1-git-send-email-robert.hu@linux.intel.com> <6afd2662-d9eb-35c1-4401-6e699c8f861e@linaro.org> <705f02a0903fc40d7328b506ebe8517f007a5d9d.camel@linux.intel.com> From: Richard Henderson Message-ID: <5b016ffe-8e55-df3d-e2f9-fef9452a7e5c@linaro.org> Date: Tue, 23 Mar 2021 06:14:56 -0600 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.7.1 MIME-Version: 1.0 In-Reply-To: <705f02a0903fc40d7328b506ebe8517f007a5d9d.camel@linux.intel.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::729; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x729.google.com X-Spam_score_int: 12 X-Spam_score: 1.2 X-Spam_bar: + X-Spam_report: (1.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_SBL_CSS=3.335, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=no autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: qemu-devel@nongnu.org Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 3/23/21 1:00 AM, Robert Hoo wrote: > On Mon, 2021-03-22 at 15:06 -0600, Richard Henderson wrote: >> On 3/22/21 4:59 AM, Robert Hoo wrote: >>> Since commit fa4518741e (target-i386: Rename struct XMMReg to >>> ZMMReg), >>> CPUX86State.xmm_regs[] has already been extended to 512bit to >>> support >>> AVX512. >>> Also, other qemu level supports for AVX512 registers are there for >>> years. >>> But in x86_cpu_dump_state(), still only dump XMM registers. >>> This patch is just to complement this part, let it dump ZMM of >>> 512bits. >> >> I think you should examine the state of the cpu to determine what of >> SSE, AVX >> or AVX512 is currently enabled, then dump that. > > Thanks Richard for review. > > Uh, looks like the existing code doesn't have this logic yet. > OK, I'm to add this logic. Correct. >>> - if (env->hflags & HF_CS64_MASK) >>> - nb = 16; >>> - else >>> - nb = 8; >>> - for(i=0;i>> - qemu_fprintf(f, "XMM%02d=%08x%08x%08x%08x", >>> + >>> + nb = sizeof(env->xmm_regs) / sizeof(env->xmm_regs[0]); >> >> E.g., you're dumping all of the registers in 32-bit mode, which is >> restricted >> to 8 registers, not 32. > > In typedef struct CPUX86State { > ... > ZMMReg xmm_regs[CPU_NB_REGS == 8 ? 8 : 32]; > ... > } > > where in cpu.h > > #define CPU_NB_REGS64 16 > #define CPU_NB_REGS32 8 > > #ifdef TARGET_X86_64 > #define CPU_NB_REGS CPU_NB_REGS64 > #else > #define CPU_NB_REGS CPU_NB_REGS32 > #endif > > so the register number is 8 in 32-bit mode and 32 in 64-bit mode. The array size is the maximum. But of course a 64-bit cpu can be put into 32-bit mode. You removed the exact check for that, using HF_CS64_MASK, quoted above. r~