From mboxrd@z Thu Jan 1 00:00:00 1970 From: Patrick DELAUNAY Date: Thu, 14 May 2020 09:39:57 +0000 Subject: [PATCH v4 2/2] arm: stm32mp: activate data cache on DDR in SPL In-Reply-To: <20200430163010.v4.2.Ib571c64a8c50fcbe386e728e38bbd320427e4efb@changeid> References: <20200430143021.3636-1-patrick.delaunay@st.com> <20200430163010.v4.2.Ib571c64a8c50fcbe386e728e38bbd320427e4efb@changeid> Message-ID: <5b1f4f8c0b774a759b4b92be183078ce@SFHDAG6NODE3.st.com> List-Id: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit To: u-boot@lists.denx.de Hi > From: Patrick DELAUNAY > Sent: jeudi 30 avril 2020 16:30 > > Activate cache on DDR to improve the accesses to DDR used by SPL: > - CONFIG_SPL_BSS_START_ADDR > - CONFIG_SYS_SPL_MALLOC_START > > Cache is configured only when DDR is fully initialized, to avoid speculative access > and issue in get_ram_size(). > Data cache is deactivated at the end of SPL, to flush the data cache and the TLB. > > Reviewed-by: Patrice Chotard > Signed-off-by: Patrick Delaunay > --- > > Changes in v4: > - fix commit message and add Patrice Chotard reviewed-by > > Changes in v3: > - remove debug message "bye" > > Changes in v2: > - new > > arch/arm/mach-stm32mp/spl.c | 19 +++++++++++++++++++ > 1 file changed, 19 insertions(+) > Applied to u-boot-stm/master, thanks! Regards Patrick