From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 72AD7C433EF for ; Fri, 8 Oct 2021 06:22:01 +0000 (UTC) Received: from phobos.denx.de (phobos.denx.de [85.214.62.61]) (using TLSv1.2 with cipher ECDHE-RSA-AES128-GCM-SHA256 (128/128 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPS id EA06B60F94 for ; Fri, 8 Oct 2021 06:22:00 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.1 mail.kernel.org EA06B60F94 Authentication-Results: mail.kernel.org; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: mail.kernel.org; spf=pass smtp.mailfrom=lists.denx.de Received: from h2850616.stratoserver.net (localhost [IPv6:::1]) by phobos.denx.de (Postfix) with ESMTP id 4927E835C9; Fri, 8 Oct 2021 08:21:58 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=pass smtp.mailfrom=u-boot-bounces@lists.denx.de DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=denx.de; s=phobos-20191101; t=1633674119; bh=Lex4EoAkTYg7F0OKK8gjjQLgy+VzWwsECBc7CKZtAbI=; h=Subject:To:Cc:References:From:Date:In-Reply-To:List-Id: List-Unsubscribe:List-Archive:List-Post:List-Help:List-Subscribe: From; b=DXGFiX6ndo4zDkdqL6eDQqROilw3JFyHEOSqBG1CrB3VquGVz8gjPcgv60vcb1dIW 1Ca65GsvtjZyQenUqYp64yV2KjRtyBG1T6eAFL/QzVPssK1WKDKKoJtT6DpclcNrAo dclBCsVWrAYy0+ZWLOtN8VhygavtylaVcvnNxbaF7raLF2cBQSj/BaYTuqva1PNRzS NlloWh4t2C6LcI7I5IPgICox3ZsSnoHjzJuTwo9BXvUkEJkQ2xeiM9FQnZnSM1sfsq TsroCL7gShyQKd5mDQ6j0+KS6MNoqNuLIYMk9/aUNnzbYIbdU3qeypzi6UUj8gV3JE Sv5zlEGp3/UkA== Received: by phobos.denx.de (Postfix, from userid 109) id 40350835CD; Fri, 8 Oct 2021 08:21:55 +0200 (CEST) Received: from mout-u-205.mailbox.org (mout-u-205.mailbox.org [91.198.250.254]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits)) (No client certificate requested) by phobos.denx.de (Postfix) with ESMTPS id 58785835D8 for ; Fri, 8 Oct 2021 08:21:48 +0200 (CEST) Authentication-Results: phobos.denx.de; dmarc=none (p=none dis=none) header.from=denx.de Authentication-Results: phobos.denx.de; spf=fail smtp.mailfrom=sr@denx.de Received: from smtp2.mailbox.org (smtp2.mailbox.org [IPv6:2001:67c:2050:105:465:1:2:0]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-384) server-signature RSA-PSS (4096 bits) server-digest SHA256) (No client certificate requested) by mout-u-205.mailbox.org (Postfix) with ESMTPS id 4HQdPm1YrszQkwj; Fri, 8 Oct 2021 08:21:48 +0200 (CEST) Subject: Re: [PATCH u-boot-marvell v2 4/6] arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port To: =?UTF-8?Q?Marek_Beh=c3=ban?= Cc: u-boot@lists.denx.de, pali@kernel.org, =?UTF-8?Q?Marek_Beh=c3=ban?= References: <20210925225446.1872-1-kabel@kernel.org> <20210925225446.1872-5-kabel@kernel.org> From: Stefan Roese Message-ID: <5b7a975e-cadf-3398-6204-e0b09a61d712@denx.de> Date: Fri, 8 Oct 2021 08:21:44 +0200 MIME-Version: 1.0 In-Reply-To: <20210925225446.1872-5-kabel@kernel.org> Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: de-DE Content-Transfer-Encoding: 8bit X-Rspamd-Queue-Id: 6ACE4182D X-BeenThere: u-boot@lists.denx.de X-Mailman-Version: 2.1.34 Precedence: list List-Id: U-Boot discussion List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: u-boot-bounces@lists.denx.de Sender: "U-Boot" X-Virus-Scanned: clamav-milter 0.103.2 at phobos.denx.de X-Virus-Status: Clean On 26.09.21 00:54, Marek Behún wrote: > From: Pali Rohár > > Now that PCI Bridge (PCIe Root Port) for Aardvark is emulated in U-Boot, > add support for handling and propagation of CRSSVE bit. > > When CRSSVE bit is unset (default), driver has to reissue config > read/write request on CRS response. > > CRSSVE bit is supported only when CRSVIS bit is provided in read-only > Root Capabilities register. So manually inject this CRSVIS bit into read > response for that register. > > Signed-off-by: Pali Rohár > Reviewed-by: Marek Behún Reviewed-by: Stefan Roese Thanks, Stefan > --- > drivers/pci/pci-aardvark.c | 26 ++++++++++++++++++++++---- > include/pci.h | 4 ++++ > 2 files changed, 26 insertions(+), 4 deletions(-) > > diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c > index 8c025dc45d..53e9e23d4a 100644 > --- a/drivers/pci/pci-aardvark.c > +++ b/drivers/pci/pci-aardvark.c > @@ -41,6 +41,7 @@ > #define PCIE_CORE_CMD_MEM_IO_REQ_EN BIT(2) > #define PCIE_CORE_DEV_REV_REG 0x8 > #define PCIE_CORE_EXP_ROM_BAR_REG 0x30 > +#define PCIE_CORE_PCIEXP_CAP_OFF 0xc0 > #define PCIE_CORE_DEV_CTRL_STATS_REG 0xc8 > #define PCIE_CORE_DEV_CTRL_STATS_RELAX_ORDER_DISABLE (0 << 4) > #define PCIE_CORE_DEV_CTRL_STATS_SNOOP_DISABLE (0 << 11) > @@ -201,6 +202,7 @@ struct pcie_advk { > struct udevice *dev; > struct gpio_desc reset_gpio; > u32 cfgcache[0x34 - 0x10]; > + bool cfgcrssve; > }; > > static inline void advk_writel(struct pcie_advk *pcie, uint val, uint reg) > @@ -413,6 +415,18 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, > data |= PCI_HEADER_TYPE_BRIDGE << 16; > } > > + if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) { > + /* CRSSVE bit is stored only in cache */ > + if (pcie->cfgcrssve) > + data |= PCI_EXP_RTCTL_CRSSVE; > + } > + > + if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + > + (PCI_EXP_RTCAP & ~3)) { > + /* CRS is emulated below, so set CRSVIS capability */ > + data |= PCI_EXP_RTCAP_CRSVIS << 16; > + } > + > *valuep = pci_conv_32_to_size(data, offset, size); > > return 0; > @@ -423,13 +437,14 @@ static int pcie_advk_read_config(const struct udevice *bus, pci_dev_t bdf, > * OS is allowed only for 4-byte PCI_VENDOR_ID config read request and > * only when CRSSVE bit in Root Port PCIe device is enabled. In all > * other error PCIe Root Complex must return all-ones. > - * Aardvark HW does not have Root Port PCIe device and U-Boot does not > - * implement emulation of this device. > + * > * U-Boot currently does not support handling of CRS return value for > * PCI_VENDOR_ID config read request and also does not set CRSSVE bit. > - * Therefore disable returning CRS response for now. > + * So it means that pcie->cfgcrssve is false. But the code is prepared > + * for returning CRS, so that if U-Boot does support CRS in the future, > + * it will work for Aardvark. > */ > - allow_crs = false; > + allow_crs = pcie->cfgcrssve; > > if (advk_readl(pcie, PIO_START)) { > dev_err(pcie->dev, > @@ -583,6 +598,9 @@ static int pcie_advk_write_config(struct udevice *bus, pci_dev_t bdf, > (offset == PCI_PRIMARY_BUS && size != PCI_SIZE_8)) > pcie->sec_busno = (data >> 8) & 0xff; > > + if ((offset & ~3) == PCIE_CORE_PCIEXP_CAP_OFF + PCI_EXP_RTCTL) > + pcie->cfgcrssve = data & PCI_EXP_RTCTL_CRSSVE; > + > return 0; > } > > diff --git a/include/pci.h b/include/pci.h > index 0fc22adffd..69eafeb4b9 100644 > --- a/include/pci.h > +++ b/include/pci.h > @@ -495,6 +495,10 @@ > #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */ > #define PCI_EXP_SLTCAP 20 /* Slot Capabilities */ > #define PCI_EXP_SLTCAP_PSN 0xfff80000 /* Physical Slot Number */ > +#define PCI_EXP_RTCTL 28 /* Root Control */ > +#define PCI_EXP_RTCTL_CRSSVE 0x0010 /* CRS Software Visibility Enable */ > +#define PCI_EXP_RTCAP 30 /* Root Capabilities */ > +#define PCI_EXP_RTCAP_CRSVIS 0x0001 /* CRS Software Visibility capability */ > #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */ > #define PCI_EXP_DEVCAP2_ARI 0x00000020 /* ARI Forwarding Supported */ > #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */ > Viele Grüße, Stefan -- DENX Software Engineering GmbH, Managing Director: Wolfgang Denk HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de