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From: "Philippe Mathieu-Daudé" <f4bug@amsat.org>
To: qemu-devel@nongnu.org
Cc: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com>,
	Richard Henderson <richard.henderson@linaro.org>,
	Petar Jovanovic <petar.jovanovic@syrmia.com>,
	Filip Vidojevic <Filip.Vidojevic@Syrmia.com>,
	Aurelien Jarno <aurelien@aurel32.net>,
	Vince Del Vecchio <Vince.DelVecchio@mediatek.com>
Subject: Re: [PATCH] target/mips: Fix CACHEE opcode (CACHE using EVA addressing)
Date: Tue, 27 Apr 2021 21:32:46 +0200	[thread overview]
Message-ID: <5bb2dc77-432a-d594-8f8d-bdb34bebf00f@amsat.org> (raw)
In-Reply-To: <20210420175426.1875746-1-f4bug@amsat.org>

On 4/20/21 7:54 PM, Philippe Mathieu-Daudé wrote:
> The CACHEE opcode "requires CP0 privilege".
> 
> The pseudocode checks in the ISA manual is:
> 
>     if is_eva and not C0.Config5.EVA:
>       raise exception('RI')
> 
>     if not IsCoprocessor0Enabled():
>       raise coprocessor_exception(0)
> 
> Add the missing checks.
> 
> Inspired-by: Richard Henderson <richard.henderson@linaro.org>
> Signed-off-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
> ---
>  target/mips/translate.c | 4 +++-
>  1 file changed, 3 insertions(+), 1 deletion(-)

Thanks, applied to mips-next.


      parent reply	other threads:[~2021-04-27 19:33 UTC|newest]

Thread overview: 3+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-04-20 17:54 [PATCH] target/mips: Fix CACHEE opcode (CACHE using EVA addressing) Philippe Mathieu-Daudé
2021-04-21  1:29 ` Richard Henderson
2021-04-27 19:32 ` Philippe Mathieu-Daudé [this message]

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