From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751355AbdJBMaE (ORCPT ); Mon, 2 Oct 2017 08:30:04 -0400 Received: from lelnx194.ext.ti.com ([198.47.27.80]:35041 "EHLO lelnx194.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750978AbdJBMaB (ORCPT ); Mon, 2 Oct 2017 08:30:01 -0400 Subject: Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support To: "matthew.gerlach@linux.intel.com" CC: Marek Vasut , Cyrille Pitchen , David Woodhouse , Brian Norris , Boris Brezillon , Rob Herring , "linux-mtd@lists.infradead.org" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , linux-arm-kernel References: <20170924105924.23923-1-vigneshr@ti.com> <20170924105924.23923-6-vigneshr@ti.com> <3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com> <4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com> <038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com> <7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com> From: Vignesh R Message-ID: <5bc42364-21e1-56b6-788c-2848b8faa50f@ti.com> Date: Mon, 2 Oct 2017 17:58:55 +0530 User-Agent: Mozilla/5.0 (Windows NT 10.0; WOW64; rv:52.0) Gecko/20100101 Thunderbird/52.3.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset="utf-8" Content-Language: en-US Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi, On 9/28/2017 8:31 PM, matthew.gerlach@linux.intel.com wrote: > > Hi Vignesh, > > I tried this patch on an Arria10 SOCFPGA devkit against the 4.1.33-ltsi > kernel, and it did not go well. Commands to the flash chip timedout > resulting in the probe function failing. I ran into other problems, not > related to cadence-quadspi, that prevented me from testing against 4.9 and > 4.12 kernels, but I suspect similar behavior. > Ok, thanks! I will keep the clk_*() calls for now. Regards Vignesh > Matthew Gerlach > > On Wed, 27 Sep 2017, Vignesh R wrote: > >> Hi Matthew, >> >> On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote: >> [...] >>>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for >>>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see >>>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls. >>>>> >>>>> Not of the top of my head, sorry. +CC Matthew, he should know. >>>> >>>> I am not an expert at the clock framework nor the power management, but I >>>> did ask around a bit.  No one I asked was planning to change the clk_*() >>>> calls to pm_*() call, but the feedback was that it would be a good idea. >>> >>> The question is, if we do the replacement, will it break on socfpga ? >>> A quick test might be useful. >>> >> >> yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls >> like below patch would be helpful: >> >> >> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c >> index 53c7d8e0327a..7ad3e176cc88 100644 >> --- a/drivers/mtd/spi-nor/cadence-quadspi.c >> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c >> @@ -34,6 +34,7 @@ >> #include >> #include >> #include >> +#include >> >> #define CQSPI_NAME "cadence-qspi" >> #define CQSPI_MAX_CHIPSELECT 16 >> @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev) >> return -ENXIO; >> } >> >> - ret = clk_prepare_enable(cqspi->clk); >> - if (ret) { >> - dev_err(dev, "Cannot enable QSPI clock.\n"); >> - return ret; >> - } >> + pm_runtime_enable(dev); >> + pm_runtime_get_sync(dev); >> >> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); >> >> >> >> >> >> -- >> Regards >> Vignesh >> > From mboxrd@z Thu Jan 1 00:00:00 1970 From: Vignesh R Subject: Re: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support Date: Mon, 2 Oct 2017 17:58:55 +0530 Message-ID: <5bc42364-21e1-56b6-788c-2848b8faa50f@ti.com> References: <20170924105924.23923-1-vigneshr@ti.com> <20170924105924.23923-6-vigneshr@ti.com> <3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com> <4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com> <038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com> <7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com> Mime-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: Content-Language: en-US Sender: devicetree-owner-u79uwXL29TY76Z2rM5mHXA@public.gmane.org To: "matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org" Cc: Marek Vasut , Cyrille Pitchen , David Woodhouse , Brian Norris , Boris Brezillon , Rob Herring , "linux-mtd-IAPFreCvJWM7uuMidbF8XUB+6BGkLq7r@public.gmane.org" , "devicetree-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , linux-arm-kernel List-Id: devicetree@vger.kernel.org Hi, On 9/28/2017 8:31 PM, matthew.gerlach-VuQAYsv1563Yd54FQh9/CA@public.gmane.org wrote: > > Hi Vignesh, > > I tried this patch on an Arria10 SOCFPGA devkit against the 4.1.33-ltsi > kernel, and it did not go well. Commands to the flash chip timedout > resulting in the probe function failing. I ran into other problems, not > related to cadence-quadspi, that prevented me from testing against 4.9 and > 4.12 kernels, but I suspect similar behavior. > Ok, thanks! I will keep the clk_*() calls for now. Regards Vignesh > Matthew Gerlach > > On Wed, 27 Sep 2017, Vignesh R wrote: > >> Hi Matthew, >> >> On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote: >> [...] >>>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for >>>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see >>>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls. >>>>> >>>>> Not of the top of my head, sorry. +CC Matthew, he should know. >>>> >>>> I am not an expert at the clock framework nor the power management, but I >>>> did ask around a bit.  No one I asked was planning to change the clk_*() >>>> calls to pm_*() call, but the feedback was that it would be a good idea. >>> >>> The question is, if we do the replacement, will it break on socfpga ? >>> A quick test might be useful. >>> >> >> yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls >> like below patch would be helpful: >> >> >> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c >> index 53c7d8e0327a..7ad3e176cc88 100644 >> --- a/drivers/mtd/spi-nor/cadence-quadspi.c >> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c >> @@ -34,6 +34,7 @@ >> #include >> #include >> #include >> +#include >> >> #define CQSPI_NAME "cadence-qspi" >> #define CQSPI_MAX_CHIPSELECT 16 >> @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev) >> return -ENXIO; >> } >> >> - ret = clk_prepare_enable(cqspi->clk); >> - if (ret) { >> - dev_err(dev, "Cannot enable QSPI clock.\n"); >> - return ret; >> - } >> + pm_runtime_enable(dev); >> + pm_runtime_get_sync(dev); >> >> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); >> >> >> >> >> >> -- >> Regards >> Vignesh >> > -- To unsubscribe from this list: send the line "unsubscribe devicetree" in the body of a message to majordomo-u79uwXL29TY76Z2rM5mHXA@public.gmane.org More majordomo info at http://vger.kernel.org/majordomo-info.html From mboxrd@z Thu Jan 1 00:00:00 1970 From: vigneshr@ti.com (Vignesh R) Date: Mon, 2 Oct 2017 17:58:55 +0530 Subject: [PATCH v3 5/5] mtd: spi-nor: cadence-quadspi: Add runtime PM support In-Reply-To: References: <20170924105924.23923-1-vigneshr@ti.com> <20170924105924.23923-6-vigneshr@ti.com> <3a1160f9-a0ae-c84c-d209-af97c3c3b0f6@gmail.com> <4ee69ea4-14cc-4305-bf3f-8fe76d43bf6b@ti.com> <038919d3-ff32-d0a7-4c0a-3be16436052d@ti.com> <7237fa9e-4d3a-8a82-10c6-76737c23ed6f@ti.com> Message-ID: <5bc42364-21e1-56b6-788c-2848b8faa50f@ti.com> To: linux-arm-kernel@lists.infradead.org List-Id: linux-arm-kernel.lists.infradead.org Hi, On 9/28/2017 8:31 PM, matthew.gerlach at linux.intel.com wrote: > > Hi Vignesh, > > I tried this patch on an Arria10 SOCFPGA devkit against the 4.1.33-ltsi > kernel, and it did not go well. Commands to the flash chip timedout > resulting in the probe function failing. I ran into other problems, not > related to cadence-quadspi, that prevented me from testing against 4.9 and > 4.12 kernels, but I suspect similar behavior. > Ok, thanks! I will keep the clk_*() calls for now. Regards Vignesh > Matthew Gerlach > > On Wed, 27 Sep 2017, Vignesh R wrote: > >> Hi Matthew, >> >> On Tuesday 26 September 2017 05:19 AM, Marek Vasut wrote: >> [...] >>>>>> Ok thanks! Do you know if pm_runtime_get_sync() can enable clocks for >>>>>> QSPI on SoCFPGA or if clk_prepare_enable() is needed? Just trying to see >>>>>> if its possible to get rid of clk_*() calls in favor of pm_*() calls. >>>>> >>>>> Not of the top of my head, sorry. +CC Matthew, he should know. >>>> >>>> I am not an expert at the clock framework nor the power management, but I >>>> did ask around a bit.? No one I asked was planning to change the clk_*() >>>> calls to pm_*() call, but the feedback was that it would be a good idea. >>> >>> The question is, if we do the replacement, will it break on socfpga ? >>> A quick test might be useful. >>> >> >> yes, a quick qspi test with clk_prepare_enable() replaced by pm_*() calls >> like below patch would be helpful: >> >> >> diff --git a/drivers/mtd/spi-nor/cadence-quadspi.c b/drivers/mtd/spi-nor/cadence-quadspi.c >> index 53c7d8e0327a..7ad3e176cc88 100644 >> --- a/drivers/mtd/spi-nor/cadence-quadspi.c >> +++ b/drivers/mtd/spi-nor/cadence-quadspi.c >> @@ -34,6 +34,7 @@ >> #include >> #include >> #include >> +#include >> >> #define CQSPI_NAME "cadence-qspi" >> #define CQSPI_MAX_CHIPSELECT 16 >> @@ -1206,11 +1207,8 @@ static int cqspi_probe(struct platform_device *pdev) >> return -ENXIO; >> } >> >> - ret = clk_prepare_enable(cqspi->clk); >> - if (ret) { >> - dev_err(dev, "Cannot enable QSPI clock.\n"); >> - return ret; >> - } >> + pm_runtime_enable(dev); >> + pm_runtime_get_sync(dev); >> >> cqspi->master_ref_clk_hz = clk_get_rate(cqspi->clk); >> >> >> >> >> >> -- >> Regards >> Vignesh >> >