From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Cyrus-Session-Id: sloti22d1t05-66263-1520587188-2-994492144711869708 X-Sieve: CMU Sieve 3.0 X-Spam-known-sender: no ("Email failed DMARC policy for domain") X-Spam-score: 0.0 X-Spam-hits: BAYES_00 -1.9, HEADER_FROM_DIFFERENT_DOMAINS 0.25, RCVD_IN_DNSWL_HI -5, T_RP_MATCHES_RCVD -0.01, LANGUAGES en, BAYES_USED global, SA_VERSION 3.4.0 X-Spam-source: IP='209.132.180.67', Host='vger.kernel.org', Country='CN', FromHeader='com', MailFrom='org' X-Spam-charsets: plain='utf-8' X-IgnoreVacation: yes ("Email failed DMARC policy for domain") X-Resolved-to: greg@kroah.com X-Delivered-to: greg@kroah.com X-Mail-from: linux-usb-owner@vger.kernel.org ARC-Seal: i=1; a=rsa-sha256; cv=none; d=messagingengine.com; s=arctest; t=1520587187; b=Dh656XKfDTcoook4xcu+WKZe+ZWsp1meCj/Xx00gjclfzlw U7N2h3+lEeyRordA1S6yPyz8teU2JwL6fStTKQBfMw5SLlb7f8YwxM+eI1opHdJ7 rTYp3QNwA31mcbNBD+C/N3R4Jg3mXxHCDkBIPxcVGGZAE2Ol5uNf9bDGLKED+WWT kXko3PgwyVP+9Ar+OrLGM6OtCxYWaoAaveunSNglOYFyGENz05NqGtlUnwhPG4Cf tzpEy7KECgrKxyE1TIMvXL5FASUUyUkRrZ/6Lhui45UCo9ClQU/Msuup0DjQvZp4 imZ3PA8O/ukbtMbs83JWwkXPY032ePtLVkBKpXQ== ARC-Message-Signature: i=1; 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spf=none smtp.mailfrom=linux-usb-owner@vger.kernel.org smtp.helo=vger.kernel.org; x-aligned-from=fail; x-category=clean score=-100 state=0; x-ptr=pass x-ptr-helo=vger.kernel.org x-ptr-lookup=vger.kernel.org; x-return-mx=pass smtp.domain=vger.kernel.org smtp.result=pass smtp_org.domain=kernel.org smtp_org.result=pass smtp_is_org_domain=no header.domain=ti.com header.result=pass header_is_org_domain=yes Authentication-Results: mx1.messagingengine.com; arc=none (no signatures found); dkim=fail (body has been altered; 1024-bit rsa key sha256) header.d=ti.com header.i=@ti.com header.b=XuRgwnz2 x-bits=1024 x-keytype=rsa x-algorithm=sha256 x-selector=ti-com-17Q1; dmarc=fail (p=quarantine,has-list-id=yes,d=quarantine) header.from=ti.com; iprev=pass policy.iprev=209.132.180.67 (vger.kernel.org); spf=none smtp.mailfrom=linux-usb-owner@vger.kernel.org smtp.helo=vger.kernel.org; x-aligned-from=fail; x-category=clean score=-100 state=0; x-ptr=pass x-ptr-helo=vger.kernel.org x-ptr-lookup=vger.kernel.org; x-return-mx=pass smtp.domain=vger.kernel.org smtp.result=pass smtp_org.domain=kernel.org smtp_org.result=pass smtp_is_org_domain=no header.domain=ti.com header.result=pass header_is_org_domain=yes Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1751019AbeCIJTn (ORCPT ); Fri, 9 Mar 2018 04:19:43 -0500 Received: from fllnx209.ext.ti.com ([198.47.19.16]:46695 "EHLO fllnx209.ext.ti.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751101AbeCIJTm (ORCPT ); Fri, 9 Mar 2018 04:19:42 -0500 Subject: Re: [PATCH] usb: dwc3: Prevent indefinite sleep in _dwc3_set_mode during suspend/resume To: Felipe Balbi , Baolin Wang CC: USB , LKML References: <1519730526-22274-1-git-send-email-rogerq@ti.com> <87sh9l5z4l.fsf@linux.intel.com> <94cd6377-1327-2309-8d69-6ab0de2bdfd4@ti.com> <87po4i3o1v.fsf@linux.intel.com> <87k1uq3ho6.fsf@linux.intel.com> <8ec0485e-89af-568b-e34a-b0cd490817d0@ti.com> <87h8puwyn5.fsf@linux.intel.com> From: Roger Quadros Message-ID: <5bc56ef5-66b1-d40c-1639-e748fe18cdbd@ti.com> Date: Fri, 9 Mar 2018 11:19:37 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:52.0) Gecko/20100101 Thunderbird/52.6.0 MIME-Version: 1.0 In-Reply-To: <87h8puwyn5.fsf@linux.intel.com> Content-Type: text/plain; charset="utf-8" Content-Language: en-GB Content-Transfer-Encoding: 8bit X-EXCLAIMER-MD-CONFIG: e1e8a2fd-e40a-4ac6-ac9b-f7e9cc9ee180 Sender: linux-usb-owner@vger.kernel.org X-Mailing-List: linux-usb@vger.kernel.org X-getmail-retrieved-from-mailbox: INBOX X-Mailing-List: linux-kernel@vger.kernel.org List-ID: On 05/03/18 13:27, Felipe Balbi wrote: > > Hi, > > Baolin Wang writes: >>>>>>>>>> void dwc3_gadget_exit(struct dwc3 *dwc) >>>>>>>>>> { >>>>>>>>>> + int epnum; >>>>>>>>>> + unsigned long flags; >>>>>>>>>> + >>>>>>>>>> + spin_lock_irqsave(&dwc->lock, flags); >>>>>>>>>> + for (epnum = 2; epnum < DWC3_ENDPOINTS_NUM; epnum++) { >>>>>>>>>> + struct dwc3_ep *dep = dwc->eps[epnum]; >>>>>>>>>> + >>>>>>>>>> + if (!dep) >>>>>>>>>> + continue; >>>>>>>>>> + >>>>>>>>>> + dep->flags &= ~DWC3_EP_END_TRANSFER_PENDING; >>>>>>>>>> + } >>>>>>>>>> + spin_unlock_irqrestore(&dwc->lock, flags); >>>>>>>>>> + >>>>>>>>>> usb_del_gadget_udc(&dwc->gadget); >>>>>>>>>> dwc3_gadget_free_endpoints(dwc); >>>>>>>>> >>>>>>>>> free endpoints is a better place for this. It's already going to free >>>>>>>>> the memory anyway. Might as well clear all flags to 0 there. >>>>>>>>> >>>>>>>> >>>>>>>> But it won't solve the deadlock issue. Since dwc3_gadget_free_endpoints() >>>>>>>> is called after usb_del_gadget_udc() and the deadlock happens when >>>>>>>> >>>>>>>> usb_del_gadget_udc()->udc_stop()->dwc3_gadget_stop()->wait_event_lock_irq() >>>>>>>> >>>>>>>> and DWC3_EP_END_TRANSFER_PENDING flag is set. >>>>>>> >>>>>>> indeed. Iterating twice over the entire endpoint list seems >>>>>>> wasteful. Perhaps we just shouldn't wait when removing the UDC since >>>>>>> that's essentially what this patch will do, right? If you clear the flag >>>>>>> before calling ->udc_stop(), this means the loop in dwc3_gadget_stop() >>>>>>> will do nothing. Might as well remove it. >>>>>>> >>>>>> >>>>>> This means that we will never wait for DWC3_EP_END_TRANSFER_PENDING to clear >>>>>> in dwc3_gadget_stop() like we used to. This is perfectly fine, right? >>>>>> >>>>>> It makes sense to me as dwc3_gadget_stop() calls __dwc3_gadget_stop() which >>>>>> masks all interrupts and nobody will ever clear that flag if it was set. >>>>> >>>>> I don't think so. It can not mask the endpoint events, please check >>>>> the events which will be masked in DEVTEN register. The reason why we >>>>> should wait for DWC3_EP_END_TRANSFER_PENDING to clear is that, >>>>> sometimes the DWC3_DEPEVT_EPCMDCMPLT event will be triggered later >>>>> than 100us, but now we may have freed the gadget irq which will cause >>>>> crash. >>>> >>>> We could mask command complete events as soon as ->udc_stop() is called, >>>> right? Hmm, actually, __dwc3_gadget_stop() already clears DEVTEN >>>> completely. >>> >>> But which bit in DEVTEN says Endpoint events are disabled? >> >> When we set up the DWC3_DEPCMD_ENDTRANSFER command in >> dwc3_stop_active_transfer(), we can do not set DWC3_DEPCMD_CMDIOC, >> then there will no endpoint command complete interrupts I think. >> >> cmd |= DWC3_DEPCMD_CMDIOC; > > I remember some part of the databook mandating CMDIOC to be set. We > could test it out without and see if anything blows up. I would, > however, require a lengthy comment explaining that we're deviating from > databook revision x.yya, section foobar because $reasons. :-) > This is what the v3.10 databook says "When issuing an End Transfer command, software must set the CmdIOC bit (field 8) so that an Endpoint Command Complete event is generated after the transfer ends. This is necessary to synchronize the conclusion of system bus traffic before the End Transfer command is completed." with a note "If GUCTL2[Rst_actbitlater] is set, Software can poll the completion of the End Transfer command by polling the command active bit to be cleared to 0." fyi. Rst_actbitlater - "Enable clearing of the command active bit for the ENDXFER command after the command execution is completed. This bit is valid in device mode only." So I'd prefer not to clear CMDIOC for all cases. Could we some how just tackle the dwc3_gadget_exit case like I did in this patch? -- cheers, -roger Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki From mboxrd@z Thu Jan 1 00:00:00 1970 Content-Type: text/plain; charset="utf-8" MIME-Version: 1.0 Content-Transfer-Encoding: base64 Subject: usb: dwc3: Prevent indefinite sleep in _dwc3_set_mode during suspend/resume From: Roger Quadros Message-Id: <5bc56ef5-66b1-d40c-1639-e748fe18cdbd@ti.com> Date: Fri, 9 Mar 2018 11:19:37 +0200 To: Felipe Balbi , Baolin Wang Cc: USB , LKML List-ID: T24gMDUvMDMvMTggMTM6MjcsIEZlbGlwZSBCYWxiaSB3cm90ZToKPiAKPiBIaSwKPiAKPiBCYW9s aW4gV2FuZyA8YmFvbGluLndhbmdAbGluYXJvLm9yZz4gd3JpdGVzOgo+Pj4+Pj4+Pj4+ICB2b2lk IGR3YzNfZ2FkZ2V0X2V4aXQoc3RydWN0IGR3YzMgKmR3YykKPj4+Pj4+Pj4+PiAgewo+Pj4+Pj4+ Pj4+ICsgIGludCBlcG51bTsKPj4+Pj4+Pj4+PiArICB1bnNpZ25lZCBsb25nIGZsYWdzOwo+Pj4+ Pj4+Pj4+ICsKPj4+Pj4+Pj4+PiArICBzcGluX2xvY2tfaXJxc2F2ZSgmZHdjLT5sb2NrLCBmbGFn cyk7Cj4+Pj4+Pj4+Pj4gKyAgZm9yIChlcG51bSA9IDI7IGVwbnVtIDwgRFdDM19FTkRQT0lOVFNf TlVNOyBlcG51bSsrKSB7Cj4+Pj4+Pj4+Pj4gKyAgICAgICAgICBzdHJ1Y3QgZHdjM19lcCAgKmRl cCA9IGR3Yy0+ZXBzW2VwbnVtXTsKPj4+Pj4+Pj4+PiArCj4+Pj4+Pj4+Pj4gKyAgICAgICAgICBp ZiAoIWRlcCkKPj4+Pj4+Pj4+PiArICAgICAgICAgICAgICAgICAgY29udGludWU7Cj4+Pj4+Pj4+ Pj4gKwo+Pj4+Pj4+Pj4+ICsgICAgICAgICAgZGVwLT5mbGFncyAmPSB+RFdDM19FUF9FTkRfVFJB TlNGRVJfUEVORElORzsKPj4+Pj4+Pj4+PiArICB9Cj4+Pj4+Pj4+Pj4gKyAgc3Bpbl91bmxvY2tf aXJxcmVzdG9yZSgmZHdjLT5sb2NrLCBmbGFncyk7Cj4+Pj4+Pj4+Pj4gKwo+Pj4+Pj4+Pj4+ICAg IHVzYl9kZWxfZ2FkZ2V0X3VkYygmZHdjLT5nYWRnZXQpOwo+Pj4+Pj4+Pj4+ICAgIGR3YzNfZ2Fk Z2V0X2ZyZWVfZW5kcG9pbnRzKGR3Yyk7Cj4+Pj4+Pj4+Pgo+Pj4+Pj4+Pj4gZnJlZSBlbmRwb2lu dHMgaXMgYSBiZXR0ZXIgcGxhY2UgZm9yIHRoaXMuIEl0J3MgYWxyZWFkeSBnb2luZyB0byBmcmVl Cj4+Pj4+Pj4+PiB0aGUgbWVtb3J5IGFueXdheS4gTWlnaHQgYXMgd2VsbCBjbGVhciBhbGwgZmxh Z3MgdG8gMCB0aGVyZS4KPj4+Pj4+Pj4+Cj4+Pj4+Pj4+Cj4+Pj4+Pj4+IEJ1dCBpdCB3b24ndCBz b2x2ZSB0aGUgZGVhZGxvY2sgaXNzdWUuIFNpbmNlIGR3YzNfZ2FkZ2V0X2ZyZWVfZW5kcG9pbnRz KCkKPj4+Pj4+Pj4gaXMgY2FsbGVkIGFmdGVyIHVzYl9kZWxfZ2FkZ2V0X3VkYygpIGFuZCB0aGUg ZGVhZGxvY2sgaGFwcGVucyB3aGVuCj4+Pj4+Pj4+Cj4+Pj4+Pj4+IHVzYl9kZWxfZ2FkZ2V0X3Vk YygpLT51ZGNfc3RvcCgpLT5kd2MzX2dhZGdldF9zdG9wKCktPndhaXRfZXZlbnRfbG9ja19pcnEo KQo+Pj4+Pj4+Pgo+Pj4+Pj4+PiBhbmQgRFdDM19FUF9FTkRfVFJBTlNGRVJfUEVORElORyBmbGFn IGlzIHNldC4KPj4+Pj4+Pgo+Pj4+Pj4+IGluZGVlZC4gSXRlcmF0aW5nIHR3aWNlIG92ZXIgdGhl IGVudGlyZSBlbmRwb2ludCBsaXN0IHNlZW1zCj4+Pj4+Pj4gd2FzdGVmdWwuIFBlcmhhcHMgd2Ug anVzdCBzaG91bGRuJ3Qgd2FpdCB3aGVuIHJlbW92aW5nIHRoZSBVREMgc2luY2UKPj4+Pj4+PiB0 aGF0J3MgZXNzZW50aWFsbHkgd2hhdCB0aGlzIHBhdGNoIHdpbGwgZG8sIHJpZ2h0PyBJZiB5b3Ug Y2xlYXIgdGhlIGZsYWcKPj4+Pj4+PiBiZWZvcmUgY2FsbGluZyAtPnVkY19zdG9wKCksIHRoaXMg bWVhbnMgdGhlIGxvb3AgaW4gZHdjM19nYWRnZXRfc3RvcCgpCj4+Pj4+Pj4gd2lsbCBkbyBub3Ro aW5nLiBNaWdodCBhcyB3ZWxsIHJlbW92ZSBpdC4KPj4+Pj4+Pgo+Pj4+Pj4KPj4+Pj4+IFRoaXMg bWVhbnMgdGhhdCB3ZSB3aWxsIG5ldmVyIHdhaXQgZm9yIERXQzNfRVBfRU5EX1RSQU5TRkVSX1BF TkRJTkcgdG8gY2xlYXIKPj4+Pj4+IGluIGR3YzNfZ2FkZ2V0X3N0b3AoKSBsaWtlIHdlIHVzZWQg dG8uIFRoaXMgaXMgcGVyZmVjdGx5IGZpbmUsIHJpZ2h0Pwo+Pj4+Pj4KPj4+Pj4+IEl0IG1ha2Vz IHNlbnNlIHRvIG1lIGFzIGR3YzNfZ2FkZ2V0X3N0b3AoKSBjYWxscyBfX2R3YzNfZ2FkZ2V0X3N0 b3AoKSB3aGljaAo+Pj4+Pj4gbWFza3MgYWxsIGludGVycnVwdHMgYW5kIG5vYm9keSB3aWxsIGV2 ZXIgY2xlYXIgdGhhdCBmbGFnIGlmIGl0IHdhcyBzZXQuCj4+Pj4+Cj4+Pj4+IEkgZG9uJ3QgdGhp bmsgc28uIEl0IGNhbiBub3QgbWFzayB0aGUgZW5kcG9pbnQgZXZlbnRzLCBwbGVhc2UgY2hlY2sK Pj4+Pj4gdGhlIGV2ZW50cyB3aGljaCB3aWxsIGJlIG1hc2tlZCBpbiBERVZURU4gcmVnaXN0ZXIu IFRoZSByZWFzb24gd2h5IHdlCj4+Pj4+IHNob3VsZCB3YWl0IGZvciBEV0MzX0VQX0VORF9UUkFO U0ZFUl9QRU5ESU5HIHRvIGNsZWFyIGlzIHRoYXQsCj4+Pj4+IHNvbWV0aW1lcyB0aGUgRFdDM19E RVBFVlRfRVBDTURDTVBMVCBldmVudCB3aWxsIGJlIHRyaWdnZXJlZCBsYXRlcgo+Pj4+PiB0aGFu IDEwMHVzLCBidXQgbm93IHdlIG1heSBoYXZlIGZyZWVkIHRoZSBnYWRnZXQgaXJxIHdoaWNoIHdp bGwgY2F1c2UKPj4+Pj4gY3Jhc2guCj4+Pj4KPj4+PiBXZSBjb3VsZCBtYXNrIGNvbW1hbmQgY29t cGxldGUgZXZlbnRzIGFzIHNvb24gYXMgLT51ZGNfc3RvcCgpIGlzIGNhbGxlZCwKPj4+PiByaWdo dD8gSG1tLCBhY3R1YWxseSwgX19kd2MzX2dhZGdldF9zdG9wKCkgYWxyZWFkeSBjbGVhcnMgREVW VEVOCj4+Pj4gY29tcGxldGVseS4KPj4+Cj4+PiBCdXQgd2hpY2ggYml0IGluIERFVlRFTiBzYXlz IEVuZHBvaW50IGV2ZW50cyBhcmUgZGlzYWJsZWQ/Cj4+Cj4+IFdoZW4gd2Ugc2V0IHVwIHRoZSBE V0MzX0RFUENNRF9FTkRUUkFOU0ZFUiBjb21tYW5kIGluCj4+IGR3YzNfc3RvcF9hY3RpdmVfdHJh bnNmZXIoKSwgd2UgY2FuIGRvIG5vdCBzZXQgRFdDM19ERVBDTURfQ01ESU9DLAo+PiB0aGVuIHRo ZXJlIHdpbGwgbm8gZW5kcG9pbnQgY29tbWFuZCBjb21wbGV0ZSBpbnRlcnJ1cHRzIEkgdGhpbmsu Cj4+Cj4+IGNtZCB8PSBEV0MzX0RFUENNRF9DTURJT0M7Cj4gCj4gSSByZW1lbWJlciBzb21lIHBh cnQgb2YgdGhlIGRhdGFib29rIG1hbmRhdGluZyBDTURJT0MgdG8gYmUgc2V0LiBXZQo+IGNvdWxk IHRlc3QgaXQgb3V0IHdpdGhvdXQgYW5kIHNlZSBpZiBhbnl0aGluZyBibG93cyB1cC4gSSB3b3Vs ZCwKPiBob3dldmVyLCByZXF1aXJlIGEgbGVuZ3RoeSBjb21tZW50IGV4cGxhaW5pbmcgdGhhdCB3 ZSdyZSBkZXZpYXRpbmcgZnJvbQo+IGRhdGFib29rIHJldmlzaW9uIHgueXlhLCBzZWN0aW9uIGZv b2JhciBiZWNhdXNlICRyZWFzb25zLiA6LSkKPiAKClRoaXMgaXMgd2hhdCB0aGUgdjMuMTAgZGF0 YWJvb2sgc2F5cwoKIldoZW4gaXNzdWluZyBhbiBFbmQgVHJhbnNmZXIgY29tbWFuZCwgc29mdHdh cmUgbXVzdCBzZXQgdGhlIENtZElPQyBiaXQgKGZpZWxkIDgpIHNvIHRoYXQgYW4gRW5kcG9pbnQK Q29tbWFuZCBDb21wbGV0ZSBldmVudCBpcyBnZW5lcmF0ZWQgYWZ0ZXIgdGhlIHRyYW5zZmVyIGVu ZHMuIFRoaXMgaXMgbmVjZXNzYXJ5IHRvIHN5bmNocm9uaXplIHRoZQpjb25jbHVzaW9uIG9mIHN5 c3RlbSBidXMgdHJhZmZpYyBiZWZvcmUgdGhlIEVuZCBUcmFuc2ZlciBjb21tYW5kIGlzIGNvbXBs ZXRlZC4iCgp3aXRoIGEgbm90ZQoiSWYgR1VDVEwyW1JzdF9hY3RiaXRsYXRlcl0gaXMgc2V0LCBT b2Z0d2FyZSBjYW4gcG9sbCB0aGUgY29tcGxldGlvbiBvZiB0aGUgRW5kIFRyYW5zZmVyCmNvbW1h bmQgYnkgcG9sbGluZyB0aGUgY29tbWFuZCBhY3RpdmUgYml0IHRvIGJlIGNsZWFyZWQgdG8gMC4i CgpmeWkuClJzdF9hY3RiaXRsYXRlciAtICJFbmFibGUgY2xlYXJpbmcgb2YgdGhlIGNvbW1hbmQg YWN0aXZlIGJpdCBmb3IgdGhlIEVORFhGRVIKY29tbWFuZCBhZnRlciB0aGUgY29tbWFuZCBleGVj dXRpb24gaXMgY29tcGxldGVkLgpUaGlzIGJpdCBpcyB2YWxpZCBpbiBkZXZpY2UgbW9kZSBvbmx5 LiIKClNvIEknZCBwcmVmZXIgbm90IHRvIGNsZWFyIENNRElPQyBmb3IgYWxsIGNhc2VzLgoKQ291 bGQgd2Ugc29tZSBob3cganVzdCB0YWNrbGUgdGhlIGR3YzNfZ2FkZ2V0X2V4aXQgY2FzZSBsaWtl IEkgZGlkIGluIHRoaXMgcGF0Y2g/Cg==