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From: Stefan Roese <sr@denx.de>
To: "Marek Behún" <kabel@kernel.org>
Cc: u-boot@lists.denx.de, pali@kernel.org,
	"Marek Behún" <marek.behun@nic.cz>
Subject: Re: [PATCH u-boot-marvell v2 1/6] arm: a37xx: pci: Fix pcie_advk_link_up()
Date: Fri, 8 Oct 2021 08:20:47 +0200	[thread overview]
Message-ID: <5bd3ed43-7a73-8f89-62e8-28aac5375b72@denx.de> (raw)
In-Reply-To: <20210925225446.1872-2-kabel@kernel.org>

On 26.09.21 00:54, Marek Behún wrote:
> From: Pali Rohár <pali@kernel.org>
> 
> Aardvark reports Disabled and Hot Reset LTSSM states as values >= 0x20.
> Link is not up in these states, so fix pcie_advk_link_up() function.
> 
> Signed-off-by: Pali Rohár <pali@kernel.org>
> Reviewed-by: Marek Behún <marek.behun@nic.cz>

Reviewed-by: Stefan Roese <sr@denx.de>

Thanks,
Stefan

> ---
>   drivers/pci/pci-aardvark.c | 3 ++-
>   1 file changed, 2 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/pci/pci-aardvark.c b/drivers/pci/pci-aardvark.c
> index cf6e30f936..741e0431e1 100644
> --- a/drivers/pci/pci-aardvark.c
> +++ b/drivers/pci/pci-aardvark.c
> @@ -145,6 +145,7 @@
>   #define     LTSSM_SHIFT				24
>   #define     LTSSM_MASK				0x3f
>   #define     LTSSM_L0				0x10
> +#define     LTSSM_DISABLED			0x20
>   #define VENDOR_ID_REG				(LMI_BASE_ADDR + 0x44)
>   
>   /* PCIe core controller registers */
> @@ -569,7 +570,7 @@ static int pcie_advk_link_up(struct pcie_advk *pcie)
>   
>   	val = advk_readl(pcie, CFG_REG);
>   	ltssm_state = (val >> LTSSM_SHIFT) & LTSSM_MASK;
> -	return ltssm_state >= LTSSM_L0;
> +	return ltssm_state >= LTSSM_L0 && ltssm_state < LTSSM_DISABLED;
>   }
>   
>   /**
> 


Viele Grüße,
Stefan

-- 
DENX Software Engineering GmbH,      Managing Director: Wolfgang Denk
HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany
Phone: (+49)-8142-66989-51 Fax: (+49)-8142-66989-80 Email: sr@denx.de

  reply	other threads:[~2021-10-08  6:20 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2021-09-25 22:54 [PATCH u-boot-marvell v2 0/6] A3720 PCIe enhancements Marek Behún
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 1/6] arm: a37xx: pci: Fix pcie_advk_link_up() Marek Behún
2021-10-08  6:20   ` Stefan Roese [this message]
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 2/6] arm: a37xx: pci: Add support for accessing PCI Bridge on root bus Marek Behún
2021-10-05 21:55   ` Pali Rohár
2021-10-08  6:20     ` Stefan Roese
2021-10-08  6:21   ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 3/6] arm: a37xx: pci: Do not automatically enable bus mastering on PCI Bridge Marek Behún
2021-10-08  6:21   ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 4/6] arm: a37xx: pci: Handle propagation of CRSSVE bit from PCIe Root Port Marek Behún
2021-10-08  6:21   ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 5/6] arm: a37xx: pci: Cosmetic change Marek Behún
2021-10-08  6:21   ` Stefan Roese
2021-09-25 22:54 ` [PATCH u-boot-marvell v2 6/6] arm: a37xx: pci: Update private structure documentation Marek Behún
2021-10-08  6:22   ` Stefan Roese
2021-10-08  9:18 ` [PATCH u-boot-marvell v2 0/6] A3720 PCIe enhancements Stefan Roese

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