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svr-chch-ex1.atlnz.lc (2001:df5:b000:bc8::77) by svr-chch-ex1.atlnz.lc (2001:df5:b000:bc8::77) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Fri, 13 May 2022 10:10:01 +1200 Received: from svr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8]) by svr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8%12]) with mapi id 15.00.1497.033; Fri, 13 May 2022 10:10:01 +1200 From: Chris Packham To: Marc Zyngier CC: "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "andrew@lunn.ch" , "gregory.clement@bootlin.com" , "sebastian.hesselbarth@gmail.com" , "kostap@marvell.com" , "robert.marko@sartura.hr" , "vadym.kochan@plvision.eu" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Thread-Topic: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Thread-Index: AQHYZbhCZ5RJjp1rLk+xI3fL/9Lp4q0aEemAgADzhwA= Date: Thu, 12 May 2022 22:10:01 +0000 Message-ID: <5c01f20a-acd3-da15-081d-7cf878f8a77a@alliedtelesis.co.nz> References: <20220512042501.3339775-1-chris.packham@alliedtelesis.co.nz> <20220512042501.3339775-3-chris.packham@alliedtelesis.co.nz> <87wnermc9c.wl-maz@kernel.org> In-Reply-To: <87wnermc9c.wl-maz@kernel.org> Accept-Language: en-NZ, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.32.1.11] Content-Type: text/plain; charset="utf-8" Content-ID: <5848BA660A99C1408566F27C8D8FD044@atlnz.lc> Content-Transfer-Encoding: base64 MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=U+Hs8tju c=1 sm=1 tr=0 a=Xf/6aR1Nyvzi7BryhOrcLQ==:117 a=xqWC_Br6kY4A:10 a=oKJsc7D3gJEA:10 a=IkcTkHD0fZMA:10 a=oZkIemNP1mAA:10 a=aQaD7UiZWn3mriizGz8A:9 a=QEXdDO2ut3YA:10 X-SEG-SpamProfiler-Score: 0 Precedence: bulk List-ID: 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Received: from svr-chch-ex1.atlnz.lc (2001:df5:b000:bc8::77) by svr-chch-ex1.atlnz.lc (2001:df5:b000:bc8::77) with Microsoft SMTP Server (TLS) id 15.0.1497.32; Fri, 13 May 2022 10:10:01 +1200 Received: from svr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8]) by svr-chch-ex1.atlnz.lc ([fe80::409d:36f5:8899:92e8%12]) with mapi id 15.00.1497.033; Fri, 13 May 2022 10:10:01 +1200 From: Chris Packham To: Marc Zyngier CC: "robh+dt@kernel.org" , "krzysztof.kozlowski+dt@linaro.org" , "catalin.marinas@arm.com" , "will@kernel.org" , "andrew@lunn.ch" , "gregory.clement@bootlin.com" , "sebastian.hesselbarth@gmail.com" , "kostap@marvell.com" , "robert.marko@sartura.hr" , "vadym.kochan@plvision.eu" , "devicetree@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" Subject: Re: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Thread-Topic: [PATCH v7 2/3] arm64: dts: marvell: Add Armada 98DX2530 SoC and RD-AC5X board Thread-Index: AQHYZbhCZ5RJjp1rLk+xI3fL/9Lp4q0aEemAgADzhwA= Date: Thu, 12 May 2022 22:10:01 +0000 Message-ID: <5c01f20a-acd3-da15-081d-7cf878f8a77a@alliedtelesis.co.nz> References: <20220512042501.3339775-1-chris.packham@alliedtelesis.co.nz> <20220512042501.3339775-3-chris.packham@alliedtelesis.co.nz> <87wnermc9c.wl-maz@kernel.org> In-Reply-To: <87wnermc9c.wl-maz@kernel.org> Accept-Language: en-NZ, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: x-ms-exchange-messagesentrepresentingtype: 1 x-ms-exchange-transport-fromentityheader: Hosted x-originating-ip: [10.32.1.11] Content-ID: <5848BA660A99C1408566F27C8D8FD044@atlnz.lc> MIME-Version: 1.0 X-SEG-SpamProfiler-Analysis: v=2.3 cv=U+Hs8tju c=1 sm=1 tr=0 a=Xf/6aR1Nyvzi7BryhOrcLQ==:117 a=xqWC_Br6kY4A:10 a=oKJsc7D3gJEA:10 a=IkcTkHD0fZMA:10 a=oZkIemNP1mAA:10 a=aQaD7UiZWn3mriizGz8A:9 a=QEXdDO2ut3YA:10 X-SEG-SpamProfiler-Score: 0 X-CRM114-Version: 20100106-BlameMichelson ( TRE 0.8.0 (BSD) ) MR-646709E3 X-CRM114-CacheID: sfid-20220512_151007_207318_8CB53F3D X-CRM114-Status: GOOD ( 39.90 ) X-BeenThere: linux-arm-kernel@lists.infradead.org X-Mailman-Version: 2.1.34 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=archiver.kernel.org@lists.infradead.org Hi Marc, On 12/05/22 19:38, Marc Zyngier wrote: > On Thu, 12 May 2022 05:25:00 +0100, > Chris Packham wrote: >> The 98DX2530 SoC is the Control and Management CPU integrated into >> the Marvell 98DX25xx and 98DX35xx series of switch chip (internally >> referred to as AlleyCat5 and AlleyCat5X). >> >> These files have been taken from the Marvell SDK and lightly cleaned >> up with the License and copyright retained. >> >> Signed-off-by: Chris Packham >> Reviewed-by: Andrew Lunn >> --- >> >> Notes: >> The Marvell SDK has a number of new compatible strings. I've brought >> through some of the drivers or where possible used an in-tree >> alternative (e.g. there is SDK code for a ac5-gpio but two instances of >> the existing marvell,orion-gpio seems to cover what is needed if you use >> an appropriate binding). I expect that there will a new series of >> patches when I get some different hardware (or additions to this series >> depending on if/when it lands). >> >> Changes in v7: >> - Add missing compatible on usb1 >> - Add "rd-ac5x" compatible for board >> - Move aliases to board dts >> - Move board specific usb info to board dts >> - Consolidate usb1 board settings and remove unnecessary compatible >> - Add Allied Telesis copyright >> - Rename files after mailng-list discussion >> Changes in v6: >> - Move CPU nodes above the SoC (Krzysztof) >> - Minor formatting clean ups (Krzysztof) >> - Run through `make dtbs_check` >> - Move gic nodes inside SoC >> - Group clocks under a clock node >> Changes in v5: >> - add #{address,size}-cells property to i2c nodes >> - make i2c nodes disabled in the SoC and enable them in the board >> - add interrupt controller attributes to gpio nodes >> - Move fixed-clock nodes up a level and remove unnecessary @0 >> Changes in v4: >> - use 'phy-handle' instead of 'phy' >> - move status="okay" on usb nodes to board dts >> - Add review from Andrew >> Changes in v3: >> - Move memory node to board >> - Use single digit reg value for phy address >> - Remove MMC node (driver needs work) >> - Remove syscon & simple-mfd for pinctrl >> Changes in v2: >> - Make pinctrl a child node of a syscon node >> - Use marvell,armada-8k-gpio instead of orion-gpio >> - Remove nand peripheral. The Marvell SDK does have some changes for the >> ac5-nand-controller but I currently lack hardware with NAND fitted so >> I can't test it right now. I've therefore chosen to omit the node and >> not attempted to bring in the driver or binding. >> - Remove pcie peripheral. Again there are changes in the SDK and I have >> no way of testing them. >> - Remove prestera node. >> - Remove "marvell,ac5-ehci" compatible from USB node as >> "marvell,orion-ehci" is sufficient >> - Remove watchdog node. There is a buggy driver for the ac5 watchdog in >> the SDK but it needs some work so I've dropped the node for now. >> >> arch/arm64/boot/dts/marvell/Makefile | 1 + >> .../boot/dts/marvell/armada-98dx25xx.dtsi | 295 ++++++++++++++++++ >> .../boot/dts/marvell/armada-98dx35xx-rd.dts | 101 ++++++ >> .../boot/dts/marvell/armada-98dx35xx.dtsi | 13 + >> 4 files changed, 410 insertions(+) >> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx-rd.dts >> create mode 100644 arch/arm64/boot/dts/marvell/armada-98dx35xx.dtsi >> >> diff --git a/arch/arm64/boot/dts/marvell/Makefile b/arch/arm64/boot/dts/marvell/Makefile >> index 1c794cdcb8e6..b7a4c715afbb 100644 >> --- a/arch/arm64/boot/dts/marvell/Makefile >> +++ b/arch/arm64/boot/dts/marvell/Makefile >> @@ -24,3 +24,4 @@ dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db.dtb >> dtb-$(CONFIG_ARCH_MVEBU) += cn9132-db-B.dtb >> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-A.dtb >> dtb-$(CONFIG_ARCH_MVEBU) += cn9130-crb-B.dtb >> +dtb-$(CONFIG_ARCH_MVEBU) += armada-98dx35xx-rd.dtb >> diff --git a/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >> new file mode 100644 >> index 000000000000..55ab4cd843a9 >> --- /dev/null >> +++ b/arch/arm64/boot/dts/marvell/armada-98dx25xx.dtsi >> @@ -0,0 +1,295 @@ >> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) >> +/* >> + * Device Tree For AC5. >> + * >> + * Copyright (C) 2021 Marvell >> + * Copyright (C) 2022 Allied Telesis Labs >> + */ >> + >> +#include >> +#include >> + >> +/ { >> + model = "Marvell AC5 SoC"; >> + compatible = "marvell,ac5"; >> + interrupt-parent = <&gic>; >> + #address-cells = <2>; >> + #size-cells = <2>; >> + >> + cpus { >> + #address-cells = <2>; >> + #size-cells = <0>; >> + >> + cpu-map { >> + cluster0 { >> + core0 { >> + cpu = <&cpu0>; >> + }; >> + core1 { >> + cpu = <&cpu1>; >> + }; >> + }; >> + }; >> + >> + cpu0: cpu@0 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x0 0x0>; >> + enable-method = "psci"; >> + next-level-cache = <&l2>; >> + }; >> + >> + cpu1: cpu@1 { >> + device_type = "cpu"; >> + compatible = "arm,armv8"; >> + reg = <0x0 0x100>; >> + enable-method = "psci"; >> + next-level-cache = <&l2>; >> + }; >> + >> + l2: l2-cache { >> + compatible = "cache"; >> + }; >> + }; >> + >> + >> + psci { >> + compatible = "arm,psci-0.2"; >> + method = "smc"; >> + }; >> + >> + timer { >> + compatible = "arm,armv8-timer"; >> + interrupts = , >> + , >> + , >> + ; >> + clock-frequency = <25000000>; > I said no to this hack in a past version of this patch, and I'm going > to say it *again*. Sorry I must have missed it. > Please fix your firmware to program CNTFRQ_EL0, and > remove this useless property. I'm kind of at the mercy of what Marvell have provided for ATF. I am working on the bootloader portion in parallel and am getting things ready for submitting the u-boot support upstream. I was hoping to leave ATF alone I can at least see if they haven't fixed this already (the original dtsi I started with was fairly old) and if they haven't I'll raise it via their support system. > You are also missing a PPI for the EL2 virtual timer which is present > on any ARMv8.1+ CPU (and since this system is using A55, it definitely > has it). > > [...] Will add. >> + >> + gic: interrupt-controller@80600000 { >> + compatible = "arm,gic-v3"; >> + #interrupt-cells = <3>; >> + interrupt-controller; >> + /*#redistributor-regions = <1>;*/ >> + redistributor-stride = <0x0 0x20000>; // 128kB stride > You don't need this at all. This is the architected value for GICv3. Will remove. > >> + reg = <0x0 0x80600000 0x0 0x10000>, /* GICD */ >> + <0x0 0x80660000 0x0 0x40000>; /* GICR */ >> + interrupts = ; >> + }; >> + }; > Thanks, > > M. > _______________________________________________ linux-arm-kernel mailing list linux-arm-kernel@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-arm-kernel