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From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= <clg@kaod.org>
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Date: Wed, 6 Jul 2016 09:53:30 +0200
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Subject: Re: [Qemu-devel] [Qemu-ppc] [PATCH 8/9] ppc: Add missing slbfee.
 instruction on ppc64 BookS processors
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To: Benjamin Herrenschmidt <benh@kernel.crashing.org>, qemu-ppc@nongnu.org
Cc: qemu-devel@nongnu.org, David Gibson <david@gibson.dropbear.id.au>

On 07/06/2016 09:24 AM, Benjamin Herrenschmidt wrote:
> On Wed, 2016-07-06 at 08:57 +0200, C=C3=A9dric Le Goater wrote:
>>
>>> The -1 result is now handled in the JITed code to do the right
>> thing
>>> (well, afaik).
>>
>> well, no. It should be a 0 when the slb is not found, and thus no=20
>> machine check. That is how I understand :=20
>=20
> Right, which is afaik what the current qemu code does no ?
>=20
> The -1 isn't the function return, it's the pointer-argument
> return, which goes into rT.=20

ah yes. the :

 *rt =3D (target_ulong)-1ul;

confused me.

> This is then handled in the generated code:
>=20
>     gen_helper_find_slb_vsid(cpu_gpr[rS(ctx->opcode)], cpu_env,
>                              cpu_gpr[rB(ctx->opcode)]);
>     l1 =3D gen_new_label();
>     l2 =3D gen_new_label();
>     tcg_gen_trunc_tl_i32(cpu_crf[0], cpu_so);
>=20
> We clear CR (except so)
>=20
>     tcg_gen_brcondi_tl(TCG_COND_EQ, cpu_gpr[rS(ctx->opcode)], -1, l1);
>=20
> We branch to l1 if rT is -1
> =20
>     tcg_gen_ori_i32(cpu_crf[0], cpu_crf[0], 1 << CRF_EQ);
>=20
> We set EQ if we didn't branch
>=20
>     tcg_gen_br(l2);
>=20
> Then go to l2 (skip the next bit)
>=20
>     gen_set_label(l1);
>     tcg_gen_movi_tl(cpu_gpr[rS(ctx->opcode)], 0);
>=20
> We clear rS if it was -1
>=20
>     gen_set_label(l2);
>=20

Thanks for the details, sorry for the noise :/

Are there any OSes using it ?=20

C.