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[47.51.160.125]) by smtp.gmail.com with ESMTPSA id s5sm662307pgv.55.2021.02.16.20.31.22 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Feb 2021 20:31:25 -0800 (PST) Subject: Re: [PATCH] pc-bios/s390-ccw: Use memory barriers in virtio code To: Thomas Huth , Halil Pasic References: <20210216110056.1228582-1-thuth@redhat.com> <20210216154010.3691880f.pasic@linux.ibm.com> <72e9a5b3-dd88-85de-e4a8-88a6a9c45099@redhat.com> From: Richard Henderson Message-ID: <5c37f1f1-5538-cd06-55a2-e266cc9a972c@linaro.org> Date: Tue, 16 Feb 2021 20:31:15 -0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.10.0 MIME-Version: 1.0 In-Reply-To: <72e9a5b3-dd88-85de-e4a8-88a6a9c45099@redhat.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62a; envelope-from=richard.henderson@linaro.org; helo=mail-pl1-x62a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Christian Borntraeger , qemu-s390x@nongnu.org, Cornelia Huck , qemu-devel@nongnu.org, Peter Maydell Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/16/21 8:15 AM, Thomas Huth wrote: > On 16/02/2021 15.40, Halil Pasic wrote: >> On Tue, 16 Feb 2021 12:00:56 +0100 >> Thomas Huth wrote: >> >>> According to the virtio specification, a memory barrier should be >>> used before incrementing the idx field in the "available" ring. >>> So far, we did not do this in the s390-ccw bios yet, but recently >>> Peter Maydell saw problems with the s390-ccw bios when running >>> the qtests on an aarch64 host (the bios panic'ed with the message: >>> "SCSI cannot report LUNs: response VS RESP=09"), which could >>> maybe be related to the missing memory barriers. Thus let's add >>> those barriers now. Since we've only seen the problem on TCG so far, >>> a "bcr 14,0" should be sufficient here to trigger the tcg_gen_mb() >>> in the TCG translate code. >>> >>> (Note: The virtio spec also talks about using a memory barrier >>> *after* incrementing the idx field, but if I understood correctly >>> this is only required when using notification suppression - which >>> we don't use in the s390-ccw bios here) >> >> I suggest to the barrier after incrementing the idx field for two >> reasons. First: If the device were to see the notification, but >> not see the incremented idx field, it would effectively loose >> initiative. That is pretty straight forward, because the >> notification just says 'check out that queue', and if we don't >> see the incremented index, miss the buffer that was made available >> by incrementing idx. > > I was just about to reply that this is certainly not necessary, since > the DIAGNOSE instruction that we use for the notification hypercall > should be serializing anyway ... but after looking at the PoP, it > actually is not marked as a serializing instruction! (while e.g. > SVC - supervisor call - is explicitly marked as serializing) > > So maybe that's worth a try: Peter, could you please apply this patch > on top an see whether it makes a difference? > > diff --git a/pc-bios/s390-ccw/virtio.c b/pc-bios/s390-ccw/virtio.c > --- a/pc-bios/s390-ccw/virtio.c > +++ b/pc-bios/s390-ccw/virtio.c > @@ -54,6 +54,7 @@ static long kvm_hypercall(unsigned long nr, unsigned long > param1, >      register ulong r_param3 asm("4") = param3; >      register long retval asm("2"); >   > +    virtio_mb(); >      asm volatile ("diag 2,4,0x500" >                    : "=d" (retval) >                    : "d" (r_nr), "0" (r_param1), "r"(r_param2), "d"(r_param3) This is patching the wrong thing, IMO. You're adding barriers to the guest that I think ought not be architecturally required -- memory accesses on s390x are strongly ordered, with or without diag/svc/whatever. With diff --git a/tcg/aarch64/tcg-target.c.inc b/tcg/aarch64/tcg-target.c.inc index 1376cdc404..3c5f38be62 100644 --- a/tcg/aarch64/tcg-target.c.inc +++ b/tcg/aarch64/tcg-target.c.inc @@ -1622,6 +1622,8 @@ static void tcg_out_tlb_read TCGType mask_type; uint64_t compare_mask; + tcg_out_mb(s, TCG_MO_ALL); + mask_type = (TARGET_PAGE_BITS + CPU_TLB_DYN_MAX_BITS > 32 ? TCG_TYPE_I64 : TCG_TYPE_I32); which is a gigantic hammer, adding a host barrier before every qemu guest access, I can no longer provoke a failure (previously visible 1 in 4, now no failures in 100). With that as a data point for success, I'm going to try to use host load-acquire / store-release instructions, and then apply TCG_GUEST_DEFAULT_MO and see if I can find something that works reasonably. r~