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Wed, 30 Mar 2022 16:27:59 +0800 (CST) Subject: Re: [PATCH qemu v5 05/14] target/riscv: rvv: Add tail agnostic for vector load / store instructions To: =?UTF-8?B?6Zmz57SE5bu3?= , qemu-devel@nongnu.org, qemu-riscv@nongnu.org References: <164845204233.25323.14607469451359734000-5@git.sr.ht> <7f3c995d-182f-f1b3-4e79-94f5b81e1be9@iscas.ac.cn> From: Weiwei Li Message-ID: <5ce85a5a-8309-9016-b88f-69af545e4114@iscas.ac.cn> Date: Wed, 30 Mar 2022 16:27:57 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/alternative; boundary="------------8DB15D91056AD1D602B12DED" Content-Language: en-US X-CM-TRANSID: qwCowADXL6ONFERicF17AA--.34655S2 X-Coremail-Antispam: 1UD129KBjvJXoW3JFyruw1xWr1kCw4UCF1xKrg_yoW7Aw13pr 48Gr47JrWrJrZ7Wr1UGF1UZryrJr1UJw1UJr18tF1UJrW5Gr1IqF1jvF1j9r1UJrs7Ar1r t3WDAr17ua4DZFDanT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUBE14x267AKxVWUJVW8JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26r4j6ryUM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4j 6F4UM28EF7xvwVC2z280aVAFwI0_Cr1j6rxdM28EF7xvwVC2z280aVCY1x0267AKxVW0oV Cq3wAS0I0E0xvYzxvE52x082IY62kv0487McIj6xIIjxv20xvE14v26r1j6r18McIj6I8E 87Iv67AKxVWUJVW8JwAm72CE4IkC6x0Yz7v_Jr0_Gr1lF7xvr2IY64vIr41lF7I21c0EjI I2zVCS5cI20VAGYxC7M4xvF2IEb7IF0Fy264kE64k0F24l7480Y4vEI4kI2Ix0rVAqx4xJ Mxk0xIA0c2IEe2xFo4CEbIxvr21lc7CjxVAKzI0EY4vE52x082I5MxAIw28IcxkI7VAKI4 8JMxC20s026xCaFVCjc4AY6r1j6r4UMI8I3I0E5I8CrVAFwI0_JrI_JrWlx2IqxVCjr7xv wVAFwI0_JrI_JrWlx4CE17CEb7AF67AKxVWUAVWUtwCIc40Y0x0EwIxGrwCI42IY6xIIjx v20xvE14v26r1j6r1xMIIF0xvE2Ix0cI8IcVCY1x0267AKxVWUJVW8JwCI42IY6xAIw20E Y4v20xvaj40_WFyUJVCq3wCI42IY6I8E87Iv67AKxVWUJVW8JwCI42IY6I8E87Iv6xkF7I 0E14v26r4j6r4UJwCE64xvF2IEb7IF0Fy7YxBIdaVFxhVjvjDU0xZFpf9x0JUcqXdUUUUU = X-Originating-IP: [180.156.147.178] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.21; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, HTML_MESSAGE=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is a multi-part message in MIME format. --------------8DB15D91056AD1D602B12DED Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit 在 2022/3/30 下午3:42, 陳約廷 写道: > >> Weiwei Li > 於 >> 2022年3月28日 下午7:56 寫道： >> >> >> 在 2022/3/7 下午3:10, ~eopxd 写道: >>> From: eopXD > >>> >>> Signed-off-by: eop Chen >> > >>> Reviewed-by: Frank Chang >> > >>> --- >>>  target/riscv/insn_trans/trans_rvv.c.inc |  9 +++++++ >>>  target/riscv/vector_helper.c            | 32 +++++++++++++++++++++++++ >>>  2 files changed, 41 insertions(+) >>> >>>  diff --git a/target/riscv/vector_helper.c >>> b/target/riscv/vector_helper.c >>> index 39c79c59c2..1c7015e917 100644 >>> --- a/target/riscv/vector_helper.c >>> +++ b/target/riscv/vector_helper.c >>> @@ -289,6 +289,9 @@ vext_ldst_stride(void *vd, void *v0, >>> target_ulong base, >>>      uint32_t i, k; >>>      uint32_t nf = vext_nf(desc); >>>      uint32_t max_elems = vext_max_elems(desc, log2_esz); >>> +    uint32_t esz = 1 << log2_esz; >>> +    uint32_t total_elems = vext_get_total_elems(desc, esz); >>> +    uint32_t vta = vext_vta(desc); >>>        for (i = env->vstart; i < env->vl; i++, env->vstart++) { >>>          if (!vm && !vext_elem_mask(v0, i)) { >>> @@ -303,6 +306,11 @@ vext_ldst_stride(void *vd, void *v0, >>> target_ulong base, >>>          } >>>      } >>>      env->vstart = 0; >>> +    /* set tail elements to 1s */ >>> +    for (k = 0; k < nf; ++k) { >>> +        vext_set_elems_1s_fns[log2_esz](vd, vta, env->vl + k * >>> total_elems, >>> +                                        env->vl * esz, total_elems >>> * esz); >>> +    } >>>  } >>>    #define GEN_VEXT_LD_STRIDE(NAME, ETYPE, LOAD_FN) >>>                        \ >>> @@ -348,6 +356,9 @@ vext_ldst_us(void *vd, target_ulong base, >>> CPURISCVState *env, uint32_t desc, >>>      uint32_t i, k; >>>      uint32_t nf = vext_nf(desc); >>>      uint32_t max_elems = vext_max_elems(desc, log2_esz); >>> +    uint32_t esz = 1 << log2_esz; >>> +    uint32_t total_elems = vext_get_total_elems(desc, esz); >>> +    uint32_t vta = vext_vta(desc); >>>        /* load bytes from guest memory */ >>>      for (i = env->vstart; i < evl; i++, env->vstart++) { >>> @@ -359,6 +370,11 @@ vext_ldst_us(void *vd, target_ulong base, >>> CPURISCVState *env, uint32_t desc, >>>          } >>>      } >>>      env->vstart = 0; >>> +    /* set tail elements to 1s */ >>> +    for (k = 0; k < nf; ++k) { >>> +        vext_set_elems_1s_fns[log2_esz](vd, vta, env->vl + k * >>> total_elems, >>> +                                        env->vl * esz, total_elems >>> * esz); >>> +    } >>>  } >>> >> >> It seems incorrect here. similar to following load/store helper. >> >> In above instructions,  following elements are loaded: >> >> 0       *  max_elems          ...     0      *max_elems + vl - 1 >> >> 1       *  max_elems          ...     1     *max_elems + vl - 1 >> >> ....... >> >> (nf-1)* max_elems         ...    (nf-1)*max_elems + vl - 1 >> >> So,  the elements[vl  .. max_elems  - 1]  are  tail elements, however >> elements[vl ... 1* total_elems - 1] may not: >> >> elements from max_elems to total_elems - 1 are active elements, If >> total_elems > max_elems(LMUL< 1) >> >> Or LMUL should be equal or greater than 1 here? I didn't find any >> description about this from the spec. >> >> I also have another question about the tail elements for these >> load/store instructions: >> >> when nf = 3, LMUL = 1, vl=vlmax,  reg, reg+1, reg+2 will be loaded, >> then whether elements in reg+3 >> >> (if they belong to the same register group) are tail elements? >> >> Regards, >> >> Weiwei Li >> > > The LMUL sent into vector helper function from `trans_rvv.c.inc` takes > EMUL > (effective LMUL) instead of LMUL. Take trans_rvv.c.inc::ld_us_op for > example, > > ``` > /* > * Vector load/store instructions have the EEW encoded > * directly in the instructions. The maximum vector size is > * calculated with EMUL rather than LMUL. > */ > uint8_t emul = vext_get_emul(s, eew); > data = FIELD_DP32(data, VDATA, VM, a->vm); > data = FIELD_DP32(data, VDATA, LMUL, emul); > data = FIELD_DP32(data, VDATA, NF, a->nf); > return ldst_us_trans(a->rd, a->rs1, data, fn, s, false); > ``` > > And vext_get_emul always return something at least the length of a > vector register: > > ``` > static uint8_t vext_get_emul(DisasContext *s, uint8_t eew) > { > int8_t emul = eew - s->sew + s->lmul; > return emul < 0 ? 0 : emul; > } > ``` > > In this case I guess the naming is a little bit misleading, > `vext_max_elems` would be > equivalent to `vext_get_total_elems` for all load / store > instructions, which guarantees > That LMUL is always equal or greater to 1. In conclusion, the behavior > is correct here. OK.  Thanks for your patient explaining. Another question: max_elems is equal to total_elems when lmul >= 0. So max_elems can be reused  here instead of caculating total_elems again. > > I don’t understand your second question though. If nf = 3, there will > be 3 registers > involved with the instruction (namely reg, reg+1, reg+2). Why do we > care about > (reg+3)? > I just consider register group here. Reg, reg+1, reg+2 and reg+3 may belong to the same register group. Regards, Weiwei Li > Thanks for pointing out this question and all your efforts for > reviewing. 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