Re: [PATCH V1 2/2] arm64: dts: qcom: sc7280: add QCrypto nodes

From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
To: Om Prakash Singh <quic_omprsing@quicinc.com>
Cc: neil.armstrong@linaro.org, konrad.dybcio@linaro.org,
	agross@kernel.org, andersson@kernel.org, conor+dt@kernel.org,
	davem@davemloft.net, devicetree@vger.kernel.org,
	herbert@gondor.apana.org.au, krzysztof.kozlowski+dt@linaro.org,
	linux-arm-msm@vger.kernel.org, linux-crypto@vger.kernel.org,
	linux-kernel@vger.kernel.org, marijn.suijten@somainline.org,
	robh+dt@kernel.org, vkoul@kernel.org,
	cros-qcom-dts-watchers@chromium.org
Subject: Re: [PATCH V1 2/2] arm64: dts: qcom: sc7280: add QCrypto nodes
Date: Tue, 12 Dec 2023 11:03:15 +0100	[thread overview]
Message-ID: <5cfc4564-fd36-45a3-9293-9757ffbc7e96@linaro.org> (raw)
In-Reply-To: <20231212085454.1238896-3-quic_omprsing@quicinc.com>

On 12/12/2023 09:54, Om Prakash Singh wrote:
> Add the QCE and Crypto BAM DMA nodes.
> 
> Signed-off-by: Om Prakash Singh <quic_omprsing@quicinc.com>
> ---
>  arch/arm64/boot/dts/qcom/sc7280.dtsi | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/sc7280.dtsi b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> index 66f1eb83cca7..7b705df21f4e 100644
> --- a/arch/arm64/boot/dts/qcom/sc7280.dtsi
> +++ b/arch/arm64/boot/dts/qcom/sc7280.dtsi
> @@ -2272,6 +2272,28 @@ ipa: ipa@1e40000 {
>  			status = "disabled";
>  		};
>  
> +		cryptobam: dma-controller@1dc4000 {

Are you sure you placed it in correct place? 1e4 looks higher than 1dc.

> +			compatible = "qcom,bam-v1.7.4", "qcom,bam-v1.7.0";
> +			reg = <0x0 0x01dc4000 0x0 0x28000>;
> +			interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
> +			#dma-cells = <1>;
> +			qcom,ee = <0>;
> +			qcom,controlled-remotely;

These two properties go to the end (vendor properties are after generic
ones).

> +			iommus = <&apps_smmu 0x4E4 0x0011>,
> +				 <&apps_smmu 0x4E6 0x0011>;

Lowercase hex

> +		};
> +
> +		crypto: crypto@1dfa000 {
> +			compatible = "qcom,sc7280-qce", "qcom,sm8150-qce", "qcom,qce";
> +			reg = <0x0 0x01dfa000 0x0 0x6000>;
> +			dmas = <&cryptobam 4>, <&cryptobam 5>;
> +			dma-names = "rx", "tx";
> +			iommus = <&apps_smmu 0x4E4 0x0011>,
> +				 <&apps_smmu 0x4E4 0x0011>;

Lowercase hex

> +			interconnects = <&aggre2_noc MASTER_CRYPTO 0 &mc_virt SLAVE_EBI1 0>;
> +			interconnect-names = "memory";
> +		};

Best regards,
Krzysztof